Abstract: A bonding process includes the following process. A bump is formed on a first electric device. A patterned insulation layer is formed on a second electric device, wherein the patterned insulation layer has a thickness between 5 ?m and 400 ?m, and an opening is in the patterned insulation layer and exposes the second electric device. The bump is joined to the second electric device exposed by the opening in the patterned insulation layer.

Abstract: Various embodiments of a semiconductor chip device that include a circuit board and a stiffener frame and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a circuit board and coupling a stiffener frame to the circuit board. The stiffener frame includes a first opening that defines an interior wall. The interior wall includes a notch.

Abstract: Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.

Abstract: A semiconductor device includes: a mounted body in which a wiring pattern is formed on a first main surface; a semiconductor chip mounted on the surface of the mounted body on which the wiring pattern is formed; an underfill material which is filled between the mounted body and the semiconductor chip and forms a fillet on an outer peripheral part of the semiconductor chip; and an injection section which is disposed on the mounted body and on an outside of a side section, on which the fillet is formed to be longest, of four side sections defining a chip mount area on which the semiconductor chip is mounted, and guides the underfill material to between the mounted body and the semiconductor chip.

Abstract: An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each having a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.

Abstract: A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. The flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer.

Abstract: Methods for applying an underfill with vacuum assistance. The method may include dispensing the underfill onto a substrate proximate to at least one exterior edge of an electronic device attached to the substrate. A space between the electronic device and the substrate is evacuated through at least one gap in the underfill. The method further includes heating the underfill to cause the underfill to flow into the space. Because a vacuum condition is supplied in the open portion of the space before flow is initiated, the incidence of underfill voiding is lowered.

Abstract: A method of manufacture of an integrated circuit packaging system is provided including: providing a substrate; placing a patterned layer over the substrate for substantially removing crying warpage from the substrate, the patterned layer having an opening surrounded by other openings with the substrate exposed from the patterned layer within the other openings; mounting a semiconductor chip within the opening; and attaching a component directly over the other openings, the component having a horizontal length greater than horizontal lengths of the other openings.

Abstract: A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board.

Abstract: A semiconductor device including a semiconductor chip encapsulated by an encapsulation resin and a manufacturing method thereof, in which a size reduction may be attempted. The device includes a semiconductor chip, an external connection terminal pad electrically connected to the semiconductor chip, and an encapsulation resin encapsulating the semiconductor chip, wherein a wiring pattern on which the external connection terminal pad is formed is provided between the semiconductor chip and the external connection terminal pad, and the semiconductor chip is flip-chip bonded to the wiring pattern.

Abstract: Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.

Abstract: A method of manufacture of an integrated circuit packaging system includes: applying a conductive material on a support structure; providing a bottom integrated circuit package having a bottom lead extended therefrom; attaching the bottom lead to the conductive material; stacking a top integrated circuit package over the bottom integrated circuit package, the top integrated circuit package having a top lead extending therefrom and the top lead over the bottom lead; attaching a conductive paste at an end portion of the top lead; and forming a stacking joint by flowing the conductive paste and the conductive material, the stacking joint below the top lead as well as below and above the bottom lead.

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: The extent of a bow of a semiconductor device is suppressed in a case where the fillet width of an underfill resin is asymmetrical. The center position 12 of a chip 1 is caused to deviate from the center position 13 of a wiring substrate 2 in a direction (the direction of the arrow B) reverse to the deviation direction (the direction of the arrow A) of the center position 11 of an underfill resin 4 from the center position 12 of the chip 1. The center position 14 of a resin for encapsulation 6 is caused to deviate from the center position 13 of the wiring substrate 2 in the same direction (the direction of the arrow A) as the deviation direction (the direction of the arrow A) of the center position 11 of the underfill resin 4 from the center position 12 of the chip 1.

Abstract: A method for manufacturing a semiconductor device includes forming an electrode; forming a projection projecting with respect to the electrode by melting a resin; and providing a conductive layer electrically connected to the electrode. The conductive layer is extended to an upper surface of the projection. Therefore, productivity of the semiconductor is improved.

Abstract: A method for manufacturing a semiconductor device is disclosed. In one embodiment a semiconductor die is formed overlying a substrate. The semiconductor die is flip chip mounted to the substrate, wherein the substrate comprises a plurality of conductive traces. The semiconductor die and substrate are encapsulated with an encapsulating material. A top side of the encapsulating material is subjected to one of polishing, etching, and grinding to expose a top side of the semiconductor die. Finally, the bottom side of the substrate is subjected to one of polishing, etching, and grinding to remove the substrate and to reduce a thickness of the plurality of conductive traces.

Abstract: A method of forming a compressible contact structure on a semi-conductor chip which comprises bonding a compressible polymer layer to the chip's surface, forming a plurality of openings within the layer, depositing electrically conductive material within the openings to form electrical connections with the chip's contacts, forming a plurality of electrically conductive line elements on the polymer layer extending from a respective opening and each including an end portion, and forming a plurality of contact members each on a respective one of the line segment end portions. The compressible polymer layer allows the contact members to deflect toward (compress) the chip when the contact members are engaged by an external force or forces. A semi-conductor chip including such a compressible contact structure is also provided.

Abstract: Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.

Abstract: Described herein are stackable semiconductor device packages and related stacked package assemblies and methods. In one embodiment, a manufacturing method includes: (1) providing a substrate including contact pads disposed adjacent to an upper surface of the substrate; (2) applying an electrically conductive material to form conductive bumps disposed adjacent to respective ones of the contact pads; (3) electrically connecting a semiconductor device to the upper surface of the substrate; (4) applying a molding material to form a molded structure covering the conductive bumps and the semiconductor device; (5) forming a set of cutting slits extending partially through the molded structure and the conductive bumps to form truncated conductive bumps; and (6) reflowing the truncated conductive bumps to form reflowed conductive bumps.

Abstract: A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump.

Abstract: A semiconductor device has a semiconductor die mounted over a surface of a substrate. A mold underfill dispensing needle has a width substantially equal to a width of the semiconductor die. The dispensing needle is placed in fluid communication with a side of the semiconductor die. A mold underfill is deposited from an outlet of the dispensing needle evenly across a width of the semiconductor die into an area between the semiconductor die and substrate without motion of the dispensing needle. The dispensing needle has a shank and the outlet in a T-configuration. The dispensing needle can have a plurality of pole portions between a shank and the outlet. The dispensing needle has a plate between a shank and the outlet. The outlet has an upper edge with a length substantially equal to or greater than a length of a lower edge of the outlet.

Abstract: A unit pixel of an image sensor having a three-dimensional structure includes a first chip and a second chip which are stacked, one of the first chip and the second chip having a photodiode, and the other of the first chip and the second chip having a circuit for receiving information from the photodiode and outputting received information. The first chip includes a first pad which is projectedly disposed on an upper surface of the first chip in such a way as to define a concavo-convex structure, and the second chip includes a second pad which is depressedly disposed on an upper surface of the second chip in such a way as to define a concavo-convex structure corresponding to the concavo-convex structure of the first chip. The first chip and the second chip are mated with each other through bonding of the first pad and the second pad.

Abstract: A method of manufacturing a semiconductor device in one exemplary embodiment includes preparing a first substrate and a second substrate, the first substrate including a bump electrode group formed of bump electrodes arrayed with a certain pitch, the number of bump electrodes along a first direction being larger than the number of bump electrodes along a second direction perpendicular to the first direction; joining the first substrate and the second substrate to each other through the bump electrodes so that a gap is formed between the first substrate and the second substrate; and filling the gap with a mold resin by causing the mold resin to flow in the gap from an edge of the first substrate along the second direction of the bump electrode group.

Abstract: A dual molded multi-chip package system is provided including forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto, mounting a semiconductor device over the first encapsulation and connected to the lead, and forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system.

Abstract: A semiconductor substrate has a plurality of different size recesses formed in the substrate to provide a stepped interposer. A conductive via can be formed through the stepped interposer. An insulating layer follows a contour of the stepped interposer. A conductive layer is formed over the insulating layer following the contour of the stepped interposer. A first semiconductor die is partially disposed in a first recess and electrically connected to the conductive layer. A second semiconductor die is partially disposed in a second recess and electrically connected to the conductive layer. The first semiconductor die is electrically connected to the second semiconductor die through the conductive layer. The first and second semiconductor die can be flipchip type semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of the stepped interposer can be removed to reduce thickness.

Abstract: A semiconductor device includes a multi-layer substrate and a semiconductor element mounted on the multi-layer substrate. The multi-layer substrate contains a plurality of circuit-formation layers joined by a first resin material. The semiconductor element is mounted on the multi-layer substrate by being joined to the multi-layer substrate by a second resin material. The first resin material and the second resin material are curable in the same heating condition.

Abstract: A semiconductor device includes a wiring substrate having a mounting surface on which a semiconductor element is mounted. A portion of the mounting surface exposed from the semiconductor element is covered by a solder-resist layer, and an extension portion of the solder-resist layer extends from a dropping-commencing point of a liquid-state under-filling agent on the portion of the mounting surface exposed from the semiconductor element and into an area of the wiring substrate covered by the semiconductor element. A gap between the semiconductor element and the extension portion of the solder-resist layer is formed to be narrower than the gap between the semiconductor element and the mounting surface of the wiring substrate so that liquid drops of the under-filling agent dropped at the dropping-commencing point are sucked into the gap by a capillary phenomenon.

Abstract: Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.

Abstract: An embedded chip package process is disclosed. A first substrate having a first patterned circuit layer is provided. A second substrate having a second patterned circuit layer is provided. A dielectric material layer is formed to cover the first patterned circuit layer. A compression process is performed to cover the second substrate over the dielectric material layer and the second patterned circuit layer is embed into the dielectric material layer. A curing process is performed to cure the dielectric material layer after the step of performing the compression process. At least a conductive plug through the dielectric material layer is formed to electrically connect the first patterned circuit layer to the second patterned circuit layer after the step of performing the curing process. The first substrate, the second substrate and a portion of the at least a conductive plug are removed after the step of forming the conductive through hole.

Abstract: According to an example embodiment, there is method (100) for manufacturing a semiconductor device in an air-cavity package. For a device die having an active surface, a lead frame is provided (5), the lead frame has a top-side surface and an under-side surface, the lead frame has predetermined pad landings on the top-side surface. A laminate material is applied (10) to the top-side surface of the lead frame. In the laminate material, an air-cavity region and contact regions are defined (15, 20, 25, 30, 35). The contact regions provide electrical connections to the predetermined pad landings on the lead frame. With the active circuit surface in an orientation toward the laminate material, the device die is mounted (40, 45). The bond pads of the active surface circuit are connected with ball bonds to the predetermined pad landings on the lead frame. An air-cavity is formed between the active surface of the device die and the top-side surface of the lead frame.

Abstract: Disclosed is a flip-chip bonding method to reduce voids in underfill material. A substrate with connecting pads is provided. At least a chip with a plurality of bumps is bonded on the substrate and then an underfill material is formed between the chip and the substrate. Finally, the substrate is placed in a pressure oven in which a positive pressure greater than one atm is provided, meanwhile, the underfill material is thermally cured with exerted pressures to reduce bubbles or voids trapped inside the underfill material to avoid popcorn issues due to CTE mismatch between the chip and the substrate. In one embodiment, another underfill material is further formed between a plurality of chips and bubbles or voids trapped between the chips are also reduced by the pressurized curing.

Abstract: The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer.

Abstract: A process of forming a semiconductor integrated circuit that includes the steps of: forming at least a first element having a first pattern of conductive material and including a polymer layer surrounding the conductive material, forming at least a second element having a second pattern of conductive material and including a polymer layer surrounding the conductive material, positioning the first element relative to the second element, and bonding the polymer layer of the first and second elements at a temperature below a melting temperature of the conductive materials of the first and second elements wherein the conductive material of the first element contacts the conductive material of the second element and is maintained in position by the bonded polymer layers.

Abstract: A method for fabricating a LED includes: providing a metal substrate; etching the metal substrate to form a first terminal, a second terminal, and a gap between the first terminal and the second terminal, wherein the first terminal has at least one first etching concave and the second terminal has at least one second etching concave; placing at least one LED chip in the at least one first etching concave, wherein the at least one LED chip has a first electrode and a second electrode; electrically connecting the first electrode with the first terminal, and electrically connecting the second electrode with the second terminal; and then covering the at least one LED chip with synthetic polymer, wherein the synthetic polymer is filled into the at least one first etching concave, the at least one second etching concave and the gap to connect the first terminal with the second terminal.

Abstract: A manufacturing method of a semiconductor device includes a film state underfill resin adhering step wherein film state underfill resin in a semi-cured state is adhered on the first surface of the board main body without forming a gap between the first surface of the board main body and the pad; a flattening step wherein an upper surface of the film state underfill resin is flattened; a chip connecting step wherein the semiconductor chip is pressed onto the upper surface of the film state underfill resin after the flattening step so that the semiconductor chip is flip chip connected to the pad; and an underfill resin forming step wherein the film state underfill resin is cured so that the underfill resin is formed between the semiconductor chip and the wiring board.

Abstract: A system for accessing circuitry on a flip chip circuit device with active circuitry and full-thickness bulk silicon includes a moveable surface for supporting and locating the circuit device in a plane, an infrared (IR) imaging device located at a defined perpendicular distance from a surface of the bulk silicon, the surface of the bulk silicon parallel to the plane and a milling chamber configured to direct an etchant and a focused ion beam to the surface of the bulk silicon, resulting in a gas-enhanced milling process that creates a milled cavity in the bulk silicon. The system produces an IR reflective material located at a base of the cavity, wherein the circuit device is located within a field of view of the IR imaging device such that the IR reflective material is brought into focus by moving the IR imaging device an adjustable distance perpendicular to the surface of the bulk silicon, and where the adjustable perpendicular distance is indicative of a depth of the cavity.

Abstract: In a semiconductor light emitting device having a matrix of a plurality of bumps composed of one n-bump formed on an n-electrode layer and of a large number of p-bumps formed on p-electrode layers, the occurrence of a faulty junction after mounting can be suppressed by placement of the n-bump at center of the bump array, because the position at the center is most resistant to occurrence of stress after the mounting. Employment of such a configuration of bump array increases reliability of mounting thereof while improving uniformity of light emission intensity in the semiconductor light emitting device having an increased size.

Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P? layer, and the P? layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P? layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P? layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die and an anisotropic conducing film (ACF) adjoining the back surface of the die. The die includes a front surface; a back surface on an opposite side of the die than the front surface; and a through-silicon via (TSV) exposed through the back surface of the die.

Abstract: An integrated circuit package employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.

Abstract: One method includes fabricating a semiconductor device including providing a dielectric layer. At least one semiconductor chip is provided defining a first surface including contact elements and a second surface opposite to the first surface. The semiconductor chip is placed onto the dielectric layer with the first surface facing the dielectric layer. An encapsulant material is applied over the second surface of the semiconductor chip in a reel-to-reel process.

Abstract: A method for packaging semiconductor device is provided, which comprises: providing a carrier substrate having a top surface and a back surface, a circuit arrangement on the top surface of the carrier substrate, and a through hole is disposed near the center of the carrier substrate and is formed passed through the carrier substrate; providing a chip having an active surface and a back surface, a plurality of pads is disposed on the periphery of the active surface and a plurality of connecting elements is disposed thereon; the active surface of chip is flipped and bonded on the circuit arrangement on the top surface of the carrier substrate, and the plurality of connecting elements is not covering the through hole; filling the underfilling material to encapsulate between the plurality of connecting elements and the top surface of the carrier substrate and to fill with the through hole; and performing a suction process to remove the air within the underfilling material between the plurality of connecting eleme

Abstract: A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate.

Abstract: Provided is a method for manufacturing a semiconductor device in which movement of an island in resin sealing is prevented. A molding die includes an upper die and a lower die. The upper and lower dies are fitted together to form cavities and runners. In the lower die, a pod is provided. After heating and melting of a tablet made of a solid resin and housed in the pod, the melted sealing resin is pressurized by a plunger, and is supplied to each of the cavities. Specifically, a liquid sealing resin is supplied from the pod to the cavities, sequentially, from the upstream of the flow of the sealing resin supplied from the pod. The cavities communicate with each other through the runners. Furthermore, the runners through which the cavities communicate are provided to be tilted with respect to a path for supplying the sealing resin.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an external interconnect; forming a first planar terminal adjacent to the external interconnect and non-planar to a portion the external interconnect; mounting a first integrated circuit over the first planar terminal; connecting the first integrated circuit with the external interconnect; and forming an encapsulation over the first planar terminal covering the first integrated circuit and with the external interconnect extending from a non-horizontal side of the encapsulation and with the first planar terminal coplanar with the adjacent portion of the encapsulation exposing the first planar terminal.

Abstract: In a semiconductor device mounted structure in which device electrodes of a semiconductor device and board electrodes of a board are connected to each other via bump electrodes, respectively, and in which a sealing-bonding resin is placed between the semiconductor device and the board, a void portion is placed at a position corresponding to an edge portion of the semiconductor device in the sealing-bonding resin. Thus, stress loads generated at corner portions of the semiconductor device due to board flexures for differences in thermal expansion and thermal contraction among the individual members caused by heating and cooling during mounting of the semiconductor device, as well as for mechanical loads after the mounting process, can be absorbed by the void portion and thereby reduced, so that breakdown of the semiconductor device mounted structure is prevented.

Abstract: A non-leaded integrated circuits package system is provided including etching differential height lead structures having inner leads at a paddle height, providing mold locks at the bending points of the differential height lead structures, etching an elevated paddle at a same height as the inner leads, mounting a first integrated circuit on the elevated paddle, and electrically connecting first electrical interconnects between the first integrated circuit and the inner leads.

Abstract: A multi-chip stacking method to reduce voids between stacked chips is revealed. A first chip is disposed on a substrate, and a plurality of first bonding wires are formed by wire bonding to electrically connect the first chip and the substrate. A second chip is disposed on an active surface of the first chip where a dielectric layer and a FOW adhesive (film over wire) adhesive are attached onto a back surface of the second chip. The FOW adhesive partially encapsulates the first bonding wires and adheres to the active surface of the first chip. Then, the substrate is placed in a pressure oven to provide a positive pressure greater than one atm during thermally curing the FOW adhesive with exerted pressures. Accordingly, voids can be reduced inside the FOW adhesive during the multi-chip stacked processes where issues of poor adhesion and popcorn between chips can be avoided.

Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract: A contact spring applicator is provided which includes an applicator substrate, a removable encapsulating layer and a plurality of contact springs embedded in the removable encapsulating layer. The contact springs are positioned such that a bond pad on each contact spring is adjacent to an upper surface of the removable encapsulating layer. The contact spring applicator may also include an applicator substrate, a release layer, a plurality of unreleased contact springs on the release layer and a bond pad at an anchor end of each contact spring. The contact spring applicators apply contact springs to an integrated circuit chip, die or package or to a probe card by aligning the bond pads with bond pad landings on the receiving device. The bond pads are adhered to the bond pad landings. The encapsulating or release layer is then removed to separate the contact springs from the contact spring applicator substrate.