With Separation/delamination Along Ion Implanted Layer, E.g., "smart-cut", "unibond" (epo) Patents (Class 257/E21.568)
  • Patent number: 10431714
    Abstract: Engineered substrates for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a transducer structure having a plurality of semiconductor materials including a radiation-emitting active region. The device further includes an engineered substrate having a first material and a second material, at least one of the first material and the second material having a coefficient of thermal expansion at least approximately matched to a coefficient of thermal expansion of at least one of the plurality of semiconductor materials. At least one of the first material and the second material is positioned to receive radiation from the active region and modify a characteristic of the light.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: October 1, 2019
    Assignee: Qromis, Inc.
    Inventors: Martin F. Schubert, Cem Basceri, Vladimir Odnoblyudov, Casey Kurth, Thomas Gehrke
  • Patent number: 10312135
    Abstract: A method for the production of layers of solid material is contemplated. The method may include the steps of providing a solid body for the separation of at least one layer of solid material, generating defects by means of at least one radiation source, in particular a laser, in the inner structure of the solid body in order to determine a detachment plane along which the layer of solid material is separated from the solid body, and applying heat to a polymer layer disposed on the solid body in order to generate, in particular mechanically, stresses in the solid body, due to the stresses a crack propagating in the solid body along the detachment plane, which crack separates the layer of solid material from the solid body.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: June 4, 2019
    Assignee: Siltectra, GmbH
    Inventors: Wolfram Drescher, Jan Richter, Christian Beyer
  • Patent number: 10224203
    Abstract: Provided is a method of producing a semiconductor epitaxial wafer having enhanced gettering ability. The method of producing a semiconductor epitaxial wafer includes: a first step of irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer that is located in a surface portion of the semiconductor wafer and that includes a constituent element of the cluster ions in solid solution; and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer. The first step is performed in a state in which a temperature of the semiconductor wafer is maintained at lower than 25° C.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: March 5, 2019
    Assignee: SUMCO CORPORATION
    Inventors: Ryo Hirose, Ryosuke Okuyama, Kazunari Kurita
  • Patent number: 10096641
    Abstract: According to one embodiment, a CMOS image sensor includes a photoelectric conversion element and an amplifier transistor. The photoelectric conversion element converts incident light into an electric signal. The amplifier transistor has a heterojunction in which a Ge layer and an SiGeSn layer are joined together, as a channel region and amplifies the electric signal resulting from conversion by the photoelectric conversion element.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: October 9, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Ikeda, Tsutomu Tezuka
  • Patent number: 10049916
    Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing (102) a first semiconductor substrate, and a second semiconductor substrate formed with a germanium layer; bonding (102) the first semiconductor substrate to the second semiconductor substrate using at least one dielectric material to form a combined substrate, the germanium layer being arranged intermediate the first and second semiconductor substrates; removing (104) the second semiconductor substrate from the combined substrate to expose at least a portion of the germanium layer with misfit dislocations; and annealing (106) the combined substrate to enable removal of the misfit dislocations from the portion of the germanium layer.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 14, 2018
    Assignees: Massachusetts Institute of Technology, Nanyang Technological University
    Inventors: Kwang Hong Lee, Chuan Seng Tan, Yew Heng Tan, Gang Yih Chong, Eugene A. Fitzgerald, Shuyu Bao
  • Patent number: 9890472
    Abstract: The present invention provides a monolithic integrated lattice mismatched crystal template and a preparation method thereof by using low-viscosity material, the preparation method for the crystal template includes: providing a first crystal layer with a first lattice constant; growing a buffer layer on the first crystal layer; below the melting point of the buffer layer, growing a second crystal layer and a template layer by sequentially performing the growth process of a second crystal layer and the growth process of a first template layer on the buffer layer, or growing a template layer by directly performing a first template layer growth process on the buffer layer; melting and converting the buffer layer to an amorphous state, performing a second template layer growth process on the template layer grown by the first template layer growth process at the growth temperature above the glass transition temperature of the buffer layer, sequentially growing a template layer until the lattice of the template laye
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: February 13, 2018
    Assignee: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventor: Shumin Wang
  • Patent number: 9887124
    Abstract: A process for the manufacture of a composite structure includes the following stages: a) providing a donor substrate comprising a first surface and a support substrate; b) forming a zone of weakening in the donor substrate, the zone of weakening delimiting, with the first surface of the donor substrate, a working layer; c) assembling the support substrate and the donor substrate; d) fracturing the donor substrate along the zone of weakening; and e) thinning the working layer so as to form a thinned working layer. Stage b) is carried out so that the working layer exhibits a thickness profile appropriate for compensating for the nonuniformity in consumption of the working layer during stage e).
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: February 6, 2018
    Assignee: Soitec
    Inventors: Nadia Ben Mohamed, Eric Maze
  • Patent number: 9881832
    Abstract: A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (BOX) of the final semiconductor-on-insulator structure. The handle substrate comprising the stable carrier traps is manufactured by hydrogen ions implantation occurring using at least two different energies, followed by a 2-step thermal treatment. The thermally stable defect structures prepared thereby is stable to anneal at temperatures of at least 1180° C. The defect structure comprises 3-dimensional network of nano-cavities interconnected by dislocations. This wafer can be used as a handle wafer for fabricating silicon-on-insulator (SOI) wafers and further fabricating radio frequency (RF) semiconductor devices.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: January 30, 2018
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventor: Alex Usenko
  • Patent number: 9870940
    Abstract: Methods of forming nanosheets for a semiconductor device are provided including providing a silicon on insulator (SOI) handle wafer, the SOT handle wafer including a silicon layer and a dielectric layer on the silicon layer; providing a first donor wafer; bonding the SOI handle wafer and the first donor wafer together to provide a bonded structure; debonding the bonded structure to provide an intermediate wafer including a plurality of silicon or non-silicon nanosheets and a plurality of dielectric layers alternately stacked; and bonding the intermediate wafer to a second donor wafer to provide a final wafer including a plurality of silicon or non-silicon layers and a plurality of dielectric layers alternately stacked, wherein the final wafer includes at least one more pair of silicon or non-silicon and dielectric layers than the intermediate wafer.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: January 16, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wei-E Wang, Mark Rodder, Borna Obradovic
  • Patent number: 9859371
    Abstract: A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9798251
    Abstract: A method of manufacturing an object holder for use in a lithographic apparatus, the object holder including one or more electrically functional components, the method including: using a composite structure including a carrier sheet different from a main body of the object holder and a layered structure including one or a plurality of layers and formed on the carrier sheet; connecting the composite structure to a surface of the main body such that the layered structure is between the carrier sheet and the surface of the main body; and removing the carrier sheet from the composite structure, leaving the layered structure connected to the main body.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: October 24, 2017
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Raymond Wilhelmus Louis LaFarre, Satish Achanta, Matteo Filippi, Yogesh Karade, Antonius Johannes Maria Nellissen, Ronald Van Der Wilk, Hendrikus Christoffel Maria Van Doremalen, Wilhelmus Jacobus Johannes Welters
  • Patent number: 9793154
    Abstract: The present invention is a method for manufacturing a bonded SOI wafer including: performing a thermal oxidation treatment including at least one of a thermal oxidation during temperature-rising and a thermal oxidation during temperature-falling with the use of a batch type heat treatment furnace, thereby forming a silicon oxide film in such a way that the oxide film buried in the delaminated bonded SOI wafer has a concentric oxide film thickness distribution, and subjecting the bonded SOI wafer after delaminating a bond wafer to a reducing heat treatment to make a film thickness range of the buried oxide film being smaller than a film thickness range before the reducing heat treatment. This provides a method for manufacturing a bonded SOI wafer which can suppress a variation of a radial distribution of a buried oxide film thickness caused by a reducing heat treatment performed after delaminating the SOI layer.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: October 17, 2017
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroji Aga, Norihiro Kobayashi
  • Patent number: 9773694
    Abstract: A method for manufacturing a bonded wafer, includes: ion-implanting a gas ion such as a hydrogen ion from a surface of a bond wafer, thereby forming an ion-implanted layer; bonding the bond wafer and a base wafer; producing a bonded wafer having a thin-film on the base wafer by delaminating the bond wafer along the ion-implanted layer; and performing an RTA treatment on the bonded wafer in a hydrogen gas-containing atmosphere; wherein a protective film is formed onto the surface of the thin-film in a heat treatment furnace in the course of temperature-falling from the maximum temperature of the RTA treatment before the bonded wafer is taken out from the heat treatment furnace; and then the bonded wafer with the protective film being formed thereon is taken out from the heat treatment furnace, and is then cleaned with a cleaning liquid which can etch the protective film and the thin-film.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: September 26, 2017
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro Kobayashi, Hiroji Aga
  • Patent number: 9768261
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: September 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ta Wu, Yi-Hsien Lee, Wei-Ming You, Ting-Chun Wang
  • Patent number: 9761649
    Abstract: A thin film transistor (TFT) array substrate is disclosed. In one aspect, the substrate includes a buffer layer formed over a substrate, a storage capacitor formed in the buffer layer and including a first electrode and a second electrode surrounding and insulated from the first electrode and a driving TFT formed over the buffer layer.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: September 12, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sangjin Park, Myungho Kim, Sanghui Park, Keunchang Lee, Jaesung Cha, Taehyeok Choi
  • Patent number: 9698289
    Abstract: A method for detaching a self-supporting layer of silicon of crystalline orientation <100>, particularly with the aim of applications in the field of photovoltaics, wherein the method includes the steps of: a) Implanting ionic species in a substrate made of silicon having a crystalline orientation <100> so as to create an embrittlement plane in the substrate, delimiting on both sides a self-supporting layer and a negative of the substrate, and b) Applying a heat treatment to the substrate implanted at step a) with a temperature ramp greater than 30° C./s so as to detach the self-supporting layer of silicon.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: July 4, 2017
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Carole Braley, Frédéric Mazen
  • Patent number: 9590118
    Abstract: The present disclosure provides, in a first aspect, a semiconductor device structure, including an SOI substrate comprising a semiconductor base substrate, a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers. The semiconductor device structure further includes a semiconductor device formed in and above an active region of the SOI substrate, and a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: March 7, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Sven Beyer, Nigel Chan, Jan Hoentschel
  • Patent number: 9576844
    Abstract: A composite wafer is manufactured by providing a carrier wafer including graphite and a protective layer, forming a bonding layer, and bonding the carrier wafer to a semiconductor wafer through the bonding layer.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Berger, Hermann Gruber, Wolfgang Lehnert, Guenther Ruhl, Raimund Foerg, Anton Mauder, Hans-Joachim Schulze, Karsten Kellermann, Michael Sommer, Christian Rottmair, Roland Rupp
  • Patent number: 9548237
    Abstract: A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to delimit a first portion and a second portion on either side of the embrittlement region, assembling the donor substrate on the support substrate, fracturing the donor substrate along the embrittlement region. In addition, the method comprises a step consisting of forming a compressive stress layer in the donor substrate so as to delimit a so-called confinement region interposed between the compressive stress layer and the embrittlement region.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: January 17, 2017
    Assignee: SOITEC
    Inventors: Gweltaz Gaudin, Oleg Kononchuk, Ionut Radu
  • Patent number: 9543189
    Abstract: A method of processing a laminated wafer in which a first wafer is laminated on a second wafer, the method including: a laminated wafer forming step of forming the laminated wafer by laminating the first wafer on the second wafer; a modified layer forming step of forming a modified layer within the first wafer by positioning a focusing point of a laser beam within the first wafer and moving the first wafer in a horizontal direction relative to the focusing point while applying the laser beam, the modified layer forming step being performed before or after the laminated wafer forming step is performed; and a separating step of separating part of the first wafer from the laminated wafer with the modified layer as a boundary, the separating step being performed after the laminated wafer forming step and the modified layer forming step are performed.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: January 10, 2017
    Assignee: Disco Corporation
    Inventors: Seiji Harada, Satoshi Kobayashi, Yasuyoshi Yubira
  • Patent number: 9508918
    Abstract: A piezoelectric device is manufactured in which the material of a supporting substrate can be selected from various alternative materials. Ions are implanted into a piezoelectric substrate to form an ion-implanted portion. A temporary supporting substrate is formed on the ion-implanted surface of the piezoelectric substrate. The temporary supporting substrate includes a layer to be etched and a temporary substrate. The piezoelectric substrate is then heated to be divided at the ion-implanted portion to form a piezoelectric thin film. A supporting substrate is then formed on the piezoelectric thin film. The supporting substrate includes a dielectric film and a base substrate. The temporary supporting substrate is made of a material that produces a thermal stress at the interface between the temporary supporting substrate and the piezoelectric thin film less than the thermal stress at the interface between the supporting substrate and the piezoelectric thin film.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: November 29, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takashi Iwamoto
  • Patent number: 9492986
    Abstract: A laminate including a supporting member which is light transmissive; a supported substrate supported by the supporting member; an adhesive layer provided on a surface of the supported substrate which surface faces toward the supporting member; and a release layer which is made of an inorganic material and is provided between the supporting member and the supported substrate, the release layer having a property that changes when the release layer absorbs light coming through the supporting layer, and the release layer having a flat surface which faces the adhesive layer.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: November 15, 2016
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Yoshihiro Inao, Yasushi Fujii, Atsushi Matsushita, Koki Tamura, Atsushi Kubo
  • Patent number: 9368552
    Abstract: A method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: June 14, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ku-Feng Lin, Hung-Chang Yu, Kai-Chun Lin, Yue-Der Chih
  • Patent number: 9337105
    Abstract: A method for fabricating a semiconductor device is provided. The method for fabricating a semiconductor device includes forming transistors on a semiconductor substrate, each of the transistors having a gate structure and source/drain regions, forming an oxide film on the transistors, forming a mask film pattern on the oxide film, the mask film pattern comprising a first pattern having a first width and a second pattern having a second width different from the first width, removing a part of the oxide film using the mask film pattern to form first and second trenches, filling the first and second trenches with a nitride film, removing the rest part of the oxide film to form third and fourth trenches, and forming conductive contacts by filling the third and fourth trenches. A top width of each of the third trenches is equal to the first width, and a top width of each of the fourth trenches is equal to the second width.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: May 10, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Bum Kwon, Sung-Sam Lee
  • Patent number: 9312340
    Abstract: A group III nitride composite substrate with a diameter of 75 mm or more includes a support substrate having a thickness ts of 0.1 mm or more and 1 mm or less and a group III nitride film having a thickness tf, thinner than the thickness ts, of 0.01 mm or more and 0.25 mm or less that are bonded to each other. An absolute value |??| of a difference ?? in thermal expansion coefficient determined by subtracting a thermal expansion coefficient ?s of the support substrate from a thermal expansion coefficient ?f of the group III nitride film is 2.2×10?6 K?1 or less. A Young's modulus Es and the thickness ts of the support substrate, a Young's modulus Ef and the thickness tf of the group III nitride film, and the difference ?? in thermal expansion coefficient satisfy a relation: ts2/tf?6Ef·|??|/Es.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: April 12, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Makoto Kiyama, Keiji Ishibashi, Akihiro Hachigo, Naoki Matsumoto, Fumitake Nakanishi
  • Patent number: 9093580
    Abstract: Provided is a method of manufacturing a solar cell, wherein a solar cell is manufactured by combining a damage removal etching process, a texturing process and an edge isolation process. The method is advantageous in that RIE and DRE are conducted, and then DRE/PSG and/or an edge isolation removal process are simultaneously conducted, so that the movement of a substrate (that is, a wafer) is minimized, thereby reducing the damage rate of the substrate.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: July 28, 2015
    Assignee: HANWHA CHEMICAL CORPORATION
    Inventors: Deoc Hwan Hyun, Jae Eock Cho, Dong Ho Lee, Gui Ryong Ahn, Hyun Cheol Ryu, Yong Hwa Lee, Gang II Kim
  • Patent number: 9041147
    Abstract: According to a semiconductor substrate (40), a space (A) between a plurality of Si thin film (16), which are provide apart from one another on the insulating substrate (30), is (I) larger than a difference between elongation of part of the insulating substrate which part corresponds to the space (A) and elongation of each of Si wafers (10) when a change is made from room temperature to 600° C. and (II) smaller than 5 mm. This causes an increase in a region of each of a plurality of semiconductor thin films which region has a uniform thickness, and therefore prevents transferred semiconductor layers and the insulating substrate from being fractured or chipped.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: May 26, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Mitani
  • Patent number: 9041165
    Abstract: A method for the formation of an at least partially relaxed strained material layer, comprises providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: May 26, 2015
    Assignee: SOITEC
    Inventors: Fabrice Letertre, Bruce Faure, Pascal Guenard
  • Patent number: 8993461
    Abstract: A method for curing defects associated with the implantation of atomic species into a semiconductor layer transferred onto a receiver substrate, wherein the semiconductor layer is thermally insulated from the receiver substrate by a low thermal conductivity layer having thermal conductivity that is lower than that of the transferred semiconductor layer. The method includes applying a selective electromagnetic irradiation to the semiconductor layer to heat that layer to a temperature lower than its temperature of fusion to cure defects without causing an increase in the temperature of the receiver substrate beyond 500° C.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 31, 2015
    Assignee: Soitec
    Inventors: Ionut Radu, Christophe Gourdel, Christelle Vetizou
  • Patent number: 8987922
    Abstract: A semiconductor device includes a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may include a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (PPI) layer in contact with the bond pad, and a connector on the PPI layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. The alignment mark may be at the PPI layer. There may be multiple alignment marks at different layers. There may be multiple alignment marks for the device around the corners or at the edges of an area surrounded by the guard ring.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Wen-Hsiung Lu, Hung-Jen Lin
  • Patent number: 8962352
    Abstract: A method for calculating a warpage of a bonded SOI wafer includes: assuming that the epitaxial growth SOI wafer is a silicon single crystal wafer having the same dopant concentration as dopant concentration of the bond wafer; calculating a warpage A that occurs at the time of performing the epitaxial growth relative to the assumed silicon single crystal wafer; calculating a warpage B caused due to a thickness of the BOX layer of the epitaxial growth SOI wafer; determining a measured value of a warpage of the base wafer before bonding as a warpage C; and calculating a sum of the warpages (A+B+C) as the warpage of the bonded SOI wafer.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: February 24, 2015
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Hiroji Aga, Yasushi Mizusawa
  • Patent number: 8956951
    Abstract: A method for manufacturing an SOI wafer includes performing a flattening heat treatment on an SOI wafer under an atmosphere containing an argon gas, in which conditions of SOI wafer preparation are set so that a thickness of an SOI layer of the SOI wafer to be subjected to the flattening heat treatment is 1.4 or more times thicker than that of a BOX layer, and the thickness of the SOI layer is reduced to less than a thickness 1.4 times the thickness of the BOX layer by performing a sacrificial oxidation treatment on the SOI layer of the SOI wafer after the flattening heat treatment.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: February 17, 2015
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Masahiro Kato, Masayuki Imai
  • Patent number: 8951887
    Abstract: The invention relates to a process for fabricating a semiconductor that comprises providing a handle substrate comprising a seed substrate and a weakened sacrificial layer covering the seed substrate; joining the handle substrate with a carrier substrate; optionally treating the carrier substrate; detaching the handle substrate at the sacrificial layer to form the semiconductor structure; and removing any residue of the sacrificial layer present on the seed substrate.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: February 10, 2015
    Assignee: Soitec
    Inventors: Fabrice Letertre, Didier Landru
  • Patent number: 8946051
    Abstract: It is an object to provide a method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced even when a single crystal semiconductor substrate in which crystal defects exist is used. Such an SOI substrate can be manufactured through the steps of forming a single crystal semiconductor layer which has an extremely small number of defects over a single crystal semiconductor substrate by an epitaxial growth method; forming an oxide film on the single crystal semiconductor substrate by thermal oxidation treatment; introducing ions into the single crystal semiconductor substrate through the oxide film; bonding the single crystal semiconductor substrate into which the ions are introduced and a semiconductor substrate to each other; causing separation by heat treatment; and performing planarization treatment on the single crystal semiconductor layer provided over the semiconductor substrate.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Eriko Nishida
  • Patent number: 8946054
    Abstract: A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Devendra K. Sadana, Katherine L. Saenger, Kuen-Ting Shiu
  • Patent number: 8946053
    Abstract: A method for reducing irregularities at a surface of a layer transferred from a source substrate to a glass-based support substrate, by generating a weakening zone in the source substrate; contacting the source substrate and the glass-based support substrate; and splitting the source substrate at the weakening zone; wherein the glass-based substrate has a thickness of between 300 ?m and 600 ?m.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: February 3, 2015
    Assignee: Soitec
    Inventors: Daniel Delprat, Carine Duret, Nadia Ben-Mohamed, Fabrice Lallement
  • Patent number: 8940617
    Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Oh-Jung Kwon, Junedong Lee, Paul C. Parries, Dominic J. Schepis
  • Patent number: 8936999
    Abstract: An SOI substrate including a semiconductor layer whose thickness is even is provided. According to a method for manufacturing the SOI substrate, the semiconductor layer is formed over a base substrate. In the method, a first surface of a semiconductor substrate is polished to be planarized; a second surface of the semiconductor substrate which is opposite to the first surface is irradiated with ions, so that an embrittled region is formed in the semiconductor substrate; the second surface is attached to the base substrate, so that the semiconductor substrate is attached to the base substrate; and separation in the embrittled region is performed. The value of 3? (? denotes a standard deviation of thickness of the semiconductor layer) is less than or equal to 1.5 nm.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Keiichi Sekiguchi, Kazuya Hanaoka, Daigo Ito
  • Patent number: 8895407
    Abstract: A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base substrate such as a glass substrate, placing a bonding layer therebetween; heating the substrates bonded to each other to separate the semiconductor substrate from the base substrate, leaving a thin semiconductor layer over the base substrate; irradiating the surface of the thin semiconductor layer with laser light to improve the planarity and recover the crystallinity of the thin semiconductor layer; and thinning the thin semiconductor layer. This method allows the formation of an SOI substrate which has a single-crystalline semiconductor layer with a thickness of 100 nm or less over a base substrate.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Akihisa Shimomura, Tatsuya Mizoi, Eiji Higa, Yoji Nagano
  • Patent number: 8884306
    Abstract: A semiconductor device includes a supporting substrate, a conductive layer placed on the supporting substrate, and at least one group III nitride semiconductor layer placed on the conductive layer. Of the group III nitride semiconductor layers, a conductive-layer-neighboring group III nitride semiconductor layer has n type conductivity, dislocation density of at most 1×107 cm?2, and oxygen concentration of at most 5×1018 cm?3. Thus, an n-down type device having a semiconductor layer of high crystallinity can be provided.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: November 11, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Kyono, Kuniaki Ishihara, Akihiro Hachigo, Takahisa Yoshida, Masaki Ueno, Makoto Kiyama
  • Patent number: 8877607
    Abstract: To suppress desorption of hydrogen ions with which a single crystal semiconductor substrate is irradiated. A method for manufacturing an SOI substrate includes the following steps: irradiating a semiconductor substrate with carbon ions; irradiating the semiconductor substrate with a hydrogen ion after the irradiation with the carbon ion so as to form an embrittled region in the semiconductor substrate; disposing a surface of the semiconductor substrate and a surface of a base substrate to face each other and to be in contact with each other so that the semiconductor substrate and the base substrate are bonded; and heating the semiconductor substrate and the base substrate which are bonded to each other and separating the semiconductor substrate along the embrittled region so that a semiconductor layer is formed over the base substrate.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: November 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Junichi Koezuka
  • Patent number: 8865520
    Abstract: The present invention provides a temporary carrier bonding and detaching process. A first surface of a semiconductor wafer is mounted on a first carrier by a first adhesive layer, and a first isolation coating disposed between the first adhesive layer and the first carrier. Then, a second carrier is mounted on the second surface of the semiconductor wafer. The first carrier is detached. Then, the first surface of the semiconductor wafer is mounted on a film frame. The second carrier is detached. The method of the present invention utilizes the second carrier to support and protect the semiconductor wafer, after which the first carrier is detached. Therefore, the semiconductor wafer will not be damaged or broken, thereby improving the yield rate of the semiconductor process. Furthermore, the simplicity of the detaching method for the first carrier allows for improvement in efficiency of the semiconductor process.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: October 21, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo-Pin Yang, Wei-Min Hsiao, Cheng-Hui Hung
  • Patent number: 8859393
    Abstract: Methods and systems are disclosed for performing a passivation process on a silicon-on-insulator wafer in a chamber in which the wafer is cleaved. A bonded wafer pair is cleaved within the chamber to form the silicon-on-insulator (SOI) wafer. A cleaved surface of the SOI wafer is then passivated in-situ by exposing the cleaved surface to a passivating substance. This exposure to a passivating substance results in the formation of a thin layer of oxide on the cleaved surface. The silicon-on-insulator wafer is then removed from the chamber. In other embodiments, the silicon-on-insulator wafer is first transferred to an adjoining chamber where the wafer is then passivated. The wafer is transferred to the adjoining chamber without exposing the wafer to the atmosphere outside the chambers.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: October 14, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Michael J. Ries, Dale A. Witte, Anca Stefanescu, Andrew M. Jones
  • Patent number: 8859425
    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming one or more openings in a front side of the semiconductor device and forming sacrificial plugs in the openings that partially fill the openings. The method further includes further filling the partially filled openings with a conductive material, where individual sacrificial plugs are generally between the conductive material and a substrate of the semiconductor device. The sacrificial plugs are exposed at a backside of the semiconductor device. Contact regions can be formed at the backside by removing the sacrificial plugs.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Kunal R. Parekh
  • Patent number: 8841203
    Abstract: The present disclosure provides a method for forming two device wafers starting from a single base substrate. The method includes first providing a structure which includes a base substrate with device layers located on, or within, a topmost surface and a bottommost surface of the base substrate. The base substrate may have double side polished surfaces. The structure including the device layers is spalled in a region within the base substrate that is between the device layers. The spalling provides a first device wafer including a portion of the base substrate and one of the device layers, and a second device wafer including another portion of the base substrate and the other of the device layer.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana, Davood Shahrjerdi
  • Patent number: 8836033
    Abstract: Embodiments of a method and apparatus for removing metallic nanotubes without transferring CNTs from one substrate to another substrate provide two methods of transferring a thin layer of crystalline ST-cut quartz wafer to the surface of a carrier silicon wafer for subsequent CNT growth, without resorting to CNT transfer. In other words, embodiments of a method and apparatus allow CNTs to be grown on the same substrate that metallic nanotube removal is performed, therefore eliminating the costly and messy step of transferring CNTs from one substrate to another. This is achieved through a residual thin layer of crystalline ST-cut quartz layer on a silicon wafer. The ST-cut quartz wafer promotes aligned growth of CNTs, while the underlying silicon wafer allows backgate burnout.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: September 16, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Silai Krishnaswamy, Joseph Payne, Jeffrey Hartman
  • Patent number: 8822308
    Abstract: A method is disclosed which includes: forming at least one layer of material on at least part of a surface of a first substrate, wherein a first surface of the at least one layer of material is in contact with the first substrate thereby defining an interface; attaching a second substrate to a second surface of the at least one layer of material; forming bubbles at the interface; and applying mechanical force; whereby the second substrate and the at least one layer of material are jointly separated from the first substrate. Related arrangements are also described.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: September 2, 2014
    Assignee: Graphene Frontiers
    Inventor: Bruce Ira Willner
  • Patent number: 8815657
    Abstract: After a single crystal semiconductor layer provided over a base substrate by attaching is irradiated with a laser beam, characteristics thereof are improved by first heat treatment, and after adding an impurity element imparting conductivity to the single crystal semiconductor layer, second heat treatment is performed at lower temperature than that of the first heat treatment.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: August 26, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Suguru Ozawa, Atsuo Isobe, Takashi Hamada, Junpei Momo, Hiroaki Honda, Takashi Shingu, Tetsuya Kakehata
  • Patent number: 8802462
    Abstract: To provide an input device including a display screen which has an image display function and a text information input function by using a display portion in which a pixel includes an optical sensor. An optical sensor is provided in each pixel of the display portion in order to detect position information. A transistor of a pixel circuit in the display portion and the optical sensor are formed using a single crystal semiconductor layer. By using the single crystal semiconductor layer, there is no variation in characteristics among pixels, and position detection with high accuracy is realized. Moreover, the display portion is formed using a substrate which is a light-transmitting substrate such as a glass substrate provided with a single crystal semiconductor layer separated from a single crystal semiconductor substrate.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8802539
    Abstract: The present invention relates to a process for preparing semiconductor-on-insulator type structures that include a semiconductor layer of a donor substrate, an insulator layer and a receiver substrate. The process includes bonding of the donor substrate onto the receiver substrate, with at least one of the substrates being coated with an insulator layer, and forming at the bonding interface a so-called trapping interface of electrically active traps suitable for retaining charge carriers. The invention also relates to a semiconductor-on-insulator type structure that includes such a trapping interface.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: August 12, 2014
    Assignee: Soitec
    Inventors: Frédéric Allibert, Sébastien Kerdiles