Abstract: A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.

Abstract: A process is provided for producing at least one interconnecting well to achieve a conductive pathway between at least two connection layers of a component comprising a stack of at least one first substrate and one second substrate which are electrically insulated from one another, the process including defining a surface contact region of a surface connection layer over a surface of the stack and of at least one first contact region embedded in the stack starting from a first embedded connection layer of the first substrate. A region devoid of material is positioned between the first substrate and second substrates and which comprises a stage of producing a interconnecting well which passes through the second substrate and extends between the surface contact region and the first embedded contact region and passes through the region devoid of material, and also a first layer which covers the first embedded connection layer.

Abstract: A barrier insulating film is constituted from a first SiCN film formed with a tetramethylsilane gas flow rate lower than usual, a second SiCN film formed over the first SiCN film and formed with a usual tetramethylsilane gas flow rate, and a SiCO film formed over the second SiCN film.

Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor layer including a first region and a second region, a first contact plug disposed on the semiconductor layer and electrically connected to the first region, a second contact plug disposed on the semiconductor layer and electrically connected to the second region, a conductive layer electrically connected to the first contact plug, the conductive layer having a side surface and a bottom surface, and an insulating layer disposed between the conductive layer and the second contact plug so as to insulate the conductive layer from the second contact plug, the insulating layer facing the side surface and a portion of the bottom surface of the conductive layer.

Abstract: A semiconductor component includes a semiconductor body having a first surface and a second surface, and having an inner region and an edge region. The semiconductor component further includes a pn-junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the pn-junction extending in a lateral direction of the semiconductor body in the inner region. A first trench extends from the first side in the edge region into the semiconductor body. The trench has sidewalls that are arranged opposite to another and that are beveled relative to a horizontal direction of the semiconductor body.

Abstract: An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks, using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point. The second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern. The third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern and which extends to a second point in the first instance of the parallel route tracks, laterally separated from the first point by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks.

Abstract: An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, and forming a second interconnect pattern in the plurality of parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point in an instance of the first plurality of parallel route tracks, and the second interconnect pattern includes a second lead pattern which extends to a second point in the same instance of the plurality of parallel route tracks, such that the second point is laterally separated from the first point by a distance one to one and one-half times a space between adjacent parallel lead patterns in the plurality of parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern.

Abstract: An integrated circuit is formed by forming a first interconnect pattern in parallel route tracks, and forming a second interconnect pattern in alternating parallel route tracks. The first interconnect pattern includes a first lead pattern in the parallel route tracks, and the second interconnect pattern includes a second lead pattern in an immediately adjacent route track. The first interconnect pattern includes a crossover pattern which extends from the first lead pattern to the second lead pattern. An exclusion zone in the route track immediately adjacent to the crossover pattern is free of a lead pattern for a lateral distance of two to three times the width of the crossover pattern. Metal interconnect lines are form in the first interconnect pattern and the second interconnect pattern areas, including a continuous metal crossover line through the crossover pattern area. The exclusion zone is free of the metal interconnect lines.

Abstract: Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.

Abstract: A semiconductor process is described. A substrate with at least one conductive region is provided, on which a dielectric layer is formed. An opening is formed in the dielectric layer, such that the conductive region is exposed. A first conductive layer is conformally formed on the surface of the opening. A first cleaning step is conducted using a first cleaning solution. A baking step is conducted after the first cleaning step. Afterwards, the opening is filled with a second conductive layer.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of element-separating insulators, and contacts. The plurality of element-separating insulators are formed in an upper layer portion of the semiconductor substrate. The plurality of element-separating insulators partition the upper layer portion into a plurality of active areas extending in a first direction. The contacts are connected to the active areas. A recess is made in a part in the first direction of an upper surface of each of the active areas. The recess is made across the entire active area in a second direction orthogonal to the first direction. Positions in the first direction of two of the contacts connected respectively to mutually-adjacent active areas are different from each other. One of the contacts is in contact with a side surface of the recess and not in contact with a bottom surface of the recess.

Abstract: A semiconductor device includes a first interlayer dielectric layer formed over a semiconductor substrate, contact holes formed to penetrate the first interlayer dielectric layer, contact plugs formed within the contact holes, respectively, and spacers formed to partially cover upper sidewalk of the contact plugs within the contact holes.

Abstract: A method for reducing resist poisoning is provided. The method includes forming a first structure in a dielectric on a substrate and reducing amine related contaminants from the dielectric and the substrate created after the formation of the first structure. The method further includes forming a second structure in the dielectric. A first organic film may be formed on the substrate which is then heated and removed from the substrate to reduce the contaminant. Alternatively, a plasma treatment or cap may be provided. A second organic film is formed on the substrate and patterned to define a second structure in the dielectric.

Abstract: Certain embodiments provide a method for manufacturing a semiconductor device including forming first and second insulating films on first and second regions formed on a semiconductor substrate, respectively, selectively irradiating UV light to a second contact region where the second contact is to be formed in the second insulating film, forming first and second opening on the first and second insulating films by concurrently etching a first contact region in the first insulating film where the first contact is to be formed and the second contact region after having irradiated the UV light, respectively, forming first and second contacts in the first and second openings. The second insulating film differs from the first insulating film in the membrane stress, and is an insulating film with an etching rate that approaches an etching rate of the first insulating film by the UV light being irradiated.

Abstract: A semiconductor device manufacturing method includes forming a first capacitance film formed on the lower electrode; forming an intermediate electrode in a first region on the first capacitance film, wherein the first capacitance is interposed between the intermediate electrode and the lower electrode; forming a second capacitance film on the intermediate electrode to be interposed between the first capacitance film and the second capacitance film; and forming an upper electrode, wherein at least a portion of the second capacitance film is interposed between the upper electrode and the intermediate electrode; the upper electrode extending to a second region outside the first region, and having at least the first capacitance film interposed between the upper electrode and the lower electrode in the second region.

Abstract: A semiconductor device includes a substrate having a via region and a circuit region, an insulation interlayer formed on a top surface of the substrate, a through electrode having a first surface and a second surface, wherein the through electrode penetrates the via region of the substrate and the second surface is substantially coplanar with a bottom surface of the substrate, a first upper wiring formed on a portion of the first surface of the through electrode, a plurality of via contacts formed on a portion of a top surface of the first upper wiring, and a second upper wiring formed on the plurality of via contacts.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate; a plurality of interconnect layers disposed at different heights from the semiconductor substrate, each interconnect layer including an interconnection formed therein; and a via formed in a columnar shape extending in the stack direction of the interconnect layers, the via electrically connecting the interconnections of the different interconnect layers, the interconnections including a plurality of intermediate interconnections in contact with the via in the intermediate portion thereof, the intermediate interconnections including a plurality of first type intermediate interconnections passing through the via in a direction perpendicular to the stack direction, and the first type intermediate interconnection of a first one of the interconnect layer and the first type intermediate interconnection of a second one of the interconnect layer are intersecting each other in the via.

Abstract: An electrical interconnect for providing a temporary interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the conductive traces into the openings. Conductive structures are electrically coupled to the conductive traces over the openings. The conductive structures are adapted to enhance electrical coupling with the terminals on the IC device. Vias electrically extending through the substrate couple the conductive traces to PCB terminals located proximate a second surface of the substrate.

Abstract: The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

Abstract: A semiconductor device comprises a material layer including a first surface and a trench with an opening in the first surface. The trench is formed in the material layer. The trench comprises a tapered portion and a vertical portion. The tapered portion is in contact with the opening and comprises a scalloping-forming trench. The vertical portion has a substantially vertical sidewall. A width of the scalloping-forming trench is larger than a width of the vertical portion.

Abstract: An embodiment of the invention provides an interposer which includes: a substrate having a first surface and a second surface; a first hole extending from the first surface towards the second surface; a second hole extending from the first surface towards the second surface, wherein a width of the first hole is different from a width of the second hole; an insulating layer located on the substrate and extending onto a sidewall of the first hole and a sidewall of the second hole; and a conducting layer located on the insulating layer on the substrate and extending onto the sidewall of the first hole, wherein there is substantially no conducting layer in the second hole.

Abstract: According to an embodiment, a semiconductor device includes a first wiring member, an opening portion and an electrode terminal portion. The first wiring member is provided on a first interlayer insulating film on a semiconductor substrate and used as a wiring layer. The opening portion is provided in a second interlayer insulating film on the first wiring member. The electrode terminal portion is provided on the opening portion and the second interlayer insulating film around the opening portion. In the electrode terminal portion, a barrier metal film in contact with the first wiring member, a seed metal film and a second wiring member are stacked and thus formed in such a manner as to cover the opening portion, and a coating metal film is formed on an upper portion and a side surface of the second wiring member.

Abstract: A self-aligned gate cap dielectric can be employed to form a self-aligned contact to a diffusion region, while preventing electrical short with a gate conductor due to overlay variations. In one embodiment, an electroplatable or electrolessly platable metal is selectively deposited on conductive materials in a gate electrode, while the metal is not deposited on dielectric surfaces. The metal portion on top of the gate electrode is converted into a gate cap dielectric including the metal and oxygen. In another embodiment, a self-assembling monolayer is formed on dielectric surfaces, while exposing metallic top surfaces of a gate electrode. A gate cap dielectric including a dielectric oxide is formed on areas not covered by the self-assembling monolayer. The gate cap dielectric functions as an etch-stop structure during formation of a via hole, so that electrical shorting between a contact via structure formed therein and the gate electrode is avoided.

Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, etching to the exposed first planar area to form a cavity having a first depth in the structure, removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer, forming a doped portion in the sacrificial substrate layer, and etching the cavity to increase the depth of the cavity to expose a first conductor in the structure and to increase the planar area and depth of a portion of the cavity to expose a second conductor in the structure.

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

Abstract: A process for the production of a MWT silicon solar cell comprising the steps: (1) providing a p-type silicon wafer with (i) holes forming vias between the front-side and the back-side of the wafer and (ii) an n-type emitter extending over the entire front-side and the inside of the holes, (2) applying a conductive metal paste to the holes of the silicon wafer to provide at least the inside of the holes with a metallization, (3) drying the applied conductive metal paste, and (4) firing the dried conductive metal paste, whereby the wafer reaches a peak temperature of 700 to 900° C., wherein the conductive metal paste has no or only poor fire-through capability and comprises (a) at least one particulate electrically conductive metal selected from the group consisting of silver, copper and nickel and (b) an organic vehicle.

Abstract: A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other.

Abstract: A method includes forming conductive material in a contact hole and a TSV opening, and then performing one step to remove portions of the conductive material outside the contact hole and the TSV opening to leave the conductive material in the contact hole and the TSV opening, thereby forming a contact plug and a TSV structure, respectively. In some embodiments, the removing step is performed by a CMP process.

Abstract: A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask.

Abstract: An electronic device (50) having a conductive substrate via (70) extending between a conductor (39) on a rear face (22) and a conductor (58) over the front surface (23) of the substrate (21) includes a multi-layered etch-stop (56, 56-2) beneath the front surface conductor (58). The etch-stop (56, 56-2) permits use of a single etchant to penetrate both the substrate (21) and any overlying semiconductor (44) and/or dielectric (34) without attacking the overlying front surface conductor (58). This is especially important when the semiconductor (44) and dielectric (34) are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop (56) is preferably a stack (63, 73) of N?2 pairs (62-i) of sub-layers (62-i1, 62-i2) in either order, where a first sub-layer (62-i1) comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer (62-i2) comprises etch resistant material (e.g., Ni).

Abstract: A substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A, a second metal layer 113 formed in the hole 112A, a dielectric insulating film 135 on the first metal layer 112, and second wiring layers 114-116 on the dielectric insulating film 135, wherein the first metal layer 112 constitutes at least part of the lower electrode, an area, facing the lower electrode, of the second wiring layers 114-116 constitutes the upper electrode, and a capacitor 160 is constructed of the lower electrode, the dielectric insulating film 135 and the upper electrode P1.

Abstract: Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.

Abstract: A method for fabricating an integrated circuit comprising an electromigration barrier in a line of the integrated circuit includes forming a spacer; forming a segmented line adjacent to opposing sides of the spacer, the segmented line formed from a first conductive material; removing the spacer to form an empty line break; and filling the empty line break with a second conductive material to form an electromigration barrier that isolates electromigration effects within individual segments of the segmented line. An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.

Abstract: Some embodiments include methods of forming semiconductor constructions in which a semiconductor material sidewall is along an opening, a protective organic material is over at least one semiconductor material surface, and the semiconductor material sidewall and protective organic material are both exposed to an etch utilizing at least one fluorine-containing composition. The etch is selective for the semiconductor material relative to the organic material, and reduces sharpness of at least one projection along the semiconductor material sidewall. In some embodiments, the opening is a through wafer opening, and subsequent processing forms one or more materials within such through wafer opening to form a through wafer interconnect. In some embodiments, the opening extends to a sensor array, and the protective organic material is comprised by a microlens system over the sensor array. Subsequent processing may form a macrolens structure across the opening.

Abstract: A method of fabricating a semiconductor device may include: alternatively stacking dielectric layers and conductive layers on a substrate to form a stack structure, forming a first photoresist pattern on the stack structure, forming a second photoresist pattern whose thickness is reduced as the second photoresist pattern extends from the center of the stack structure towards a periphery of the stacked structure by performing a heat treatment on the first photoresist pattern, etching the stack structure through the second photoresist pattern to form a slope profile on the stack structure whose thickness is reduced as the slope profile extends from the center of the stack structure towards a periphery of the stacked structure, and forming a step-type profile on the end part of the stack structure by selectively etching the dielectric layer.

Abstract: A method of manufacturing a through-substrate-via structure. The method comprises providing a substrate having a front-side and an opposite back-side. A through-substrate via opening is formed in the front-side of the substrate. The through-substrate-via opening does not penetrate an outer surface of the back-side of the substrate. The through-substrate-via opening is filled with a solid fill material. Portions of the substrate from the outer surface of the back-side of the substrate are removed to thereby expose the fill material. At least portions of the exposed fill material are removed to form a back-side through-substrate via opening that traverses an entire thickness of the substrate. The back-side through-substrate via opening is filled with an electrically conductive material.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which can prevent a short-circuit between a bit line contact plug and a storage node contact plug, resulting in improved semiconductor device characteristics. A method for manufacturing a semiconductor device includes: forming a bit line contact hole from which an active region is protruded, by etching a semiconductor substrate; forming a conductive material over the semiconductor substrate including the bit line contact hole; etching the conductive material to form a bit line contact plug and a bit line, each of which has a smaller width than the bit line contact hole; and forming a spacer insulation film over the entire surface of the semiconductor substrate including the bit line contact hole, the bit line contact plug, and the bit line.

Abstract: A method of forming an interconnect structure and an integrated circuit including the interconnect structure. The method includes: depositing a dielectric layer over a conductive layer; forming an opening in the dielectric layer to expose the conductive layer; forming a barrierless single-phase interconnect comprising a metal or compound having a melting point between a melting point of copper and a melting point of tungsten. Forming includes depositing a layer of metal or compound within the opening and on an upper surface of the dielectric layer Preferably, the barrierless single-phase interconnect comprises cobalt or a cobalt containing compound. Thus, an interconnect structure, including a via and associated line, is made up of a single-phase metal or compound without the use of a different material between the interconnect and the underlying dielectric, thus improving electrical performance and reliability and further simplifying the interconnect formation process.

Abstract: A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.

Abstract: A method for fabricating through-silicon via structure includes the steps of: providing a semiconductor substrate; forming at least one semiconductor device on surface of the semiconductor substrate; forming a dielectric layer on the semiconductor device, in which the dielectric layer includes at least one via hole; forming a first conductive layer on the dielectric layer and filling the via hole; performing an etching process to form a through-silicon via in the first conductive layer, the dielectric layer, and the semiconductor substrate; depositing a second conductive layer in the through-silicon via and partially on the first conductive layer; and planarizing a portion of the second conductive layer until reaching the surface of the first conductive layer.

Abstract: To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1?x):x where 0.01?x?0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced.

Abstract: A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.

Abstract: Openings are formed in first and second mask layers. Next, diameter of the opening in the second mask layer is enlarged so that the diameter of the opening in the second mask layer becomes larger by a length X than diameter of the opening in the first mask layer. Thereafter, mask material is formed into the opening in the second mask layer, to form a cavity with a diameter X within the opening in the second mask layer. There is formed a mask which includes the second mask layer and the mask material having therein opening including the cavity.

Abstract: A through-hole electrode substrate related to an embodiment of the present invention is arranged with a semiconductor substrate having a plurality of through-holes, an insulating layer formed with an insulating material on the inner walls of the plurality of through-holes and on at least one surface of the semiconductor substrate, a plurality of through-hole electrodes formed with a metal material inside the through-hole, and a plurality of gas discharge parts formed to contact with each of the plurality of through-hole electrodes which is exposed on at least one surface of the semiconductor substrate, the plurality of gas discharge parts externally discharges gas which is discharged from the inside of the plurality of through-hole electrodes.

Abstract: A method for fabricating a semiconductor device includes sequentially forming an etch stop layer and a mold layer over a substrate, forming an open region by selectively etching the mold layer until the etch stop layer is exposed, transforming a surface of the mold layer into an insulation layer by performing a surface treatment, and forming a conductive layer inside the open region.

Abstract: A semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface, a chip pad disposed on the first surface of the substrate, and a through-silicon via (TSV) including a plurality of sub vias electrically connected to the chip pad at different positions.

Abstract: A semiconductor package includes a first semiconductor chip formed with a first through-silicon via; a second semiconductor chip stacked over the first semiconductor chip and formed with a second through-silicon via; and a cantilever formed over the first semiconductor chip and electrically connected to the first through-silicon via or the second through-silicon via according to an electrical signal.

Abstract: A method of forming metal lines of a semiconductor device includes forming an etch stop layer over a semiconductor substrate over which underlying structures are formed, forming an insulating layer over the etch stop layer, etching the etch stop layer and the insulating layer to form trenches through which the underlying structures are exposed, shrinking the insulating layer by using a thermal treatment process in order to widen openings of the trenches, and filling the trenches with a conductive material.

Abstract: A semiconductor device includes an embedding layer in which one or more semiconductor element(s) is embedded and one or more interconnect layers as well as one or more insulation layers on one or both sides of the embedding layer. The embedding layer includes a woven cloth formed by reinforcement fibers. The woven cloth has an opening on its site embedding the semiconductor element. The opening is arranged so that direction of the reinforcement fibers will have a preset angle with respect to a direction of a side of or a tangent to at least a portion of the opening, the preset angle being other than a square angle or a zero angle (parallelism).