Abstract: A method for use in the manufacture of an electronic circuit comprising at least one substantially planar electronic device is disclosed.

Abstract: A connection contact layer (4) is disposed between semiconductor bodies (1,2). In the second semiconductor body (2), a recess is provided. A connection layer (7) on the top face extends as far as the recess, in which a metallization (10) is present that conductively connects the connection contact layer (4) to the connection layer (7) in an electrical manner. A polymer (8) or a further metallization is present in the recess.

Abstract: A semiconductor memory device includes a plurality of memory blocks formed over a substrate including source regions and separated from each other by a slit, a plurality of bit lines coupled to the strings of the memory blocks and disposed over the memory blocks, and source contact lines formed within the slits, coupled to the source regions, respectively, and disposed in a direction to cross the plurality of bit lines.

Abstract: An integrated circuit may include a region containing a thermoelectric material and be configured to be subjected to a temperature gradient resulting from a flow of an electric current in a part of the integrated circuit during its operation, and an electrically conducting output coupled to the region for delivering the electrical energy produced by thermoelectric material.

Abstract: In a method of forming a wiring structure, a first insulation layer is formed on a substrate, the first insulation layer comprising a group of hydrocarbon (C?H?) wherein ? and ? are integers. A second insulation layer is formed on the first insulation layer, the second insulation layer being avoid of the group of hydrocarbon. A first opening is formed through the first and the second insulation layers by etching the first and the second insulation layers. A damaged pattern and a first insulation layer pattern are formed by performing a surface treatment on a portion of the first insulation layer corresponding to an inner sidewall of the first opening. A sacrificial spacer is formed in the first opening on the damaged pattern and on the second insulation layer. A conductive pattern is formed in the first opening.

Abstract: A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer.

Abstract: A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer.

Abstract: A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.

Abstract: A process of forming an integrated circuit using a palladium CMP operation in which 25 to 125 ppm aluminum is added to the CMP slurry, allowing a palladium removal rate of at least 80 nanometers per minute at a polish pad pressure less than 9 psi and a surface speed between 1.9 and 2.2 meters per second. The palladium CMP operation may be applied to form a palladium bond pad cap after which an external bond element is formed on the palladium bond pad cap. Alternatively, the palladium CMP operation may be applied to form a palladium interconnect conductor in a first dielectric layer.

Abstract: A method is provided for fabricating an electrical fuse and a field effect transistor having a metal gate which includes removing material from first and second openings in a dielectric region overlying a substrate, wherein the first opening is aligned with an active semiconductor region of the substrate, and the second opening is aligned with an isolation region of the substrate, and the active semiconductor region including a source region and a drain region adjacent edges of the first opening. An electrical fuse can be formed which has a fuse element filling the second opening, the fuse element being a monolithic region of a single conductive material being a metal or a conductive compound of a metal. A metal gate can be formed which extends within the first opening to define a field effect transistor (“FET”) which includes the metal gate and the active semiconductor region.

Abstract: A method of forming an interconnect structure includes providing a dielectric layer; forming a metal line in the dielectric layer; and forming a composite etch stop layer (ESL), which includes forming a lower ESL over the metal line and the dielectric layer; and forming an upper ESL over the lower ESL. The upper ESL and the lower ESL have different compositions. The step of forming the lower ESL and the step of forming the upper ESL are in-situ performed.

Abstract: An interconnect structure is provided that includes at least one patterned and cured low-k material located on a surface of a patterned graded cap layer. The at least one cured and patterned low-k material and the patterned graded cap layer each have conductively filled regions embedded therein. The patterned and cured low-k material is a cured product of a functionalized polymer, copolymer, or a blend including at least two of any combination of polymers and/or copolymers having one or more acid-sensitive imageable groups, and the graded cap layer includes a lower region that functions as a barrier region and an upper region that has antireflective properties of a permanent antireflective coating.

Abstract: A microscopic metallic structure is produced by creating or exposing a patterned region of increased conductivity and then forming a conductor on the region using electrodeposition. In some embodiments, a microscopic metallic structure is formed on a substrate, and then the substrate is etched to remove the structure from the substrate. In some embodiments, a focused beam of gallium ion without a deposition precursor gas scans a pattern on a silicon substrate, to produce a conductive pattern on which a copper structure is then formed by electrochemical deposition of one or more metals. The structure can be freed from the substrate by etching, or can used in place. A beam can be used to access an active layer of a transistor, and then a conductor can be electrodeposited to provide a lead for sensing or modifying the transistor operation while it is functioning.

Abstract: Methods for fabricating array substrates are provided. A method for fabricating an array substrate includes forming a first metal layer over a substrate and then patterned by a first photolithography to forming a gate line, a gate electrode connecting the gate line, and a pad over the substrate. An insulating layer, a semiconductor layer, and an ohmic contact layer are formed over the substrate to cover the gate line, the gate electrode and the pad. The ohmic contact layer, the semiconductor layer, and portions of the insulating layer are patterned by a second photolithography to forming a semiconductor structure over the substrate and a via hole in the insulating layer over the pad to exposing a part of the pad.

Abstract: An image sensor and a method of manufacturing an image sensor. An image sensor may include a readout circuitry having a metal line on and/or over a first substrate. An image sensor may include an image sensing part having a first conductive-type conductive layer and/or a second conductive-type conductive layer over a metal line. An image sensor may include a pixel division area formed on and/or over an image sensing part corresponding to a pixel boundary. An image sensor may include a ground contact on and/or over a pixel division area. An image sensor may include a contact plug connected with a sidewall of an image sensing part. A method of manufacturing an image sensor is disclosed.

Abstract: A method for defining parallel lines extending along a first direction in a same level of an integrated circuit, among which at least first and second lines separated by an even number of lines are interconnected, a space having a width at least equal to the minimum space between two lines separated by one line being left free, in a second direction perpendicular to the first direction, on either side of a minimum rectangle containing the first and the second lines.

Abstract: A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an emitter electrode is formed. By soldering the copper posts onto the electrode, heat generated in the IGBT is transferred to the electrode member and is radiated. In addition, even if a material of which the IGBT is made and copper differ in thermal expansivity, stress on a soldered interface is reduced and distortion is reduced. This suppresses the appearance of a crack. As a result, the heat cycle resistance and power cycle resistance of a power module can be improved.

Abstract: A semiconductor device including a first insulating film formed above a semiconductor substrate and having a first relative dielectric constant; a second insulating film formed above the first insulating film and having a second relative dielectric constant greater than the first relative dielectric constant; a plurality of columnar plugs extending longitudinally through the first and the second insulating films having a first sidewall extending through the first insulating film and a second sidewall extending through the second insulating film, wherein the second sidewall is tapered; a third insulating film formed above the second insulating film and having a third relative dielectric constant less than the second relative dielectric constant of the second insulating film; trenches extending through the third insulating film and reaching an upper portion of the plugs; and an interconnect wiring comprising metal formed within the trenches and contacting the upper portion of the plugs.

Abstract: A GaN layer and an n-type AlGaN layer are formed over an insulating substrate, and thereafter, a gate electrode, a source electrode and a drain electrode are formed on them. Next, an opening reaching at least a surface of the insulating substrate is formed in the source electrode, the GaN layer and the n-type AlGaN layer. Then, a nickel (Ni) layer is formed in the opening. Thereafter, by conducting dry etching from the back side while making the nickel (Ni) layer serve as an etching stopper, a via hole reaching the nickel (Ni) layer is formed in the insulating substrate. Then, a via wiring is formed extending from an inside the via hole to the back surface of the insulating substrate.

Abstract: A semiconductor manufacturing method includes: forming a seed film including a first metal over a bottom surface and a side wall of an opening portion formed over interlayer insulating films and a field portion located over the interlayer insulating film except the opening portion, forming a resist over the seed film and filling the opening portion with the resist, removing part of the resist, exposing the seed film formed over the upper portion of the side walls of the opening portion and the field portion, forming a cover film including a second metal, whose resistivity is higher than that of the first metal, over the seed film located over the upper portion of the side wall of the opening portion and the field portion, exposing the seed film by removing the resist, and forming a plating film including the first metal over the exposed seed film.

Abstract: An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate; a plurality of interconnect layers disposed at different heights from the semiconductor substrate, each interconnect layer including an interconnection formed therein; and a via formed in a columnar shape extending in the stack direction of the interconnect layers, the via electrically connecting the interconnections of the different interconnect layers, the interconnections including an intermediate interconnection in contact with the via in the intermediate portion thereof, and the intermediate interconnection including a first type intermediate interconnection passing through the via in a direction perpendicular to the stack direction and in contact with the via on the top surface, bottom surface, and both side surfaces thereof.

Abstract: Upon forming a complex metallization system, the parasitic capacitance between metal lines of adjacent metallization layers may be reduced by providing a patterned etch stop material. In this manner, the patterning process for forming the via openings may be controlled in a highly reliable manner, while, on the other hand, the resulting overall dielectric constant of the metallization system may be reduced, thereby also significantly reducing the parasitic capacitance between stacked metal lines.

Abstract: An insulated-gate field-effect transistor (220U) is provided with an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.

Abstract: A method for fabricating a semiconductor device includes forming an insulation layer containing an impurity, forming a contact hole by etching the insulation layer, performing a treatment to decrease a concentration of the impurity on a surface of the insulation layer, and rinsing the contact hole.

Abstract: A through substrate structure, an electronic device package using the same, and methods for manufacturing the same are disclosed. First, a via hole pattern is formed by etching an upper surface of a first substrate. A pattern layer of a second substrate is formed on the first substrate by filling the via hole pattern with a material for the second substrate by reflow. A via hole pattern is formed in the pattern layer of the second substrate by patterning the upper surface of the first substrate. Moreover, a via plug filling the via hole pattern is formed by a plating process, for example, thereby forming a through substrate structure, which can be used in an electronic device package.

Abstract: A method for inducing a tensile stress in a channel of a field effect transistor (FET) includes forming a nitride film over the FET; forming a contact hole to the FET through the nitride film; and performing ultraviolet (UV) curing of the nitride film after forming the contact hole to the FET through the nitride film, wherein the UV cured nitride film induces the tensile stress in the channel of the FET.

Abstract: Various systems and methods related to semiconductor devices having a plurality of layers and having a first conductive trace on a first layer electrically connected to a second conductive trace on a second layer and electrically isolated from a third electrical trace on the second layer are provided. A semiconductor structure can include first, second and third layers. The first conducting layer may be etched to form a first trench for the first conductive trace. A layer of material on the second layer in the first trench can define a patch area, wherein the patch area is disposed in a location where the first trench crosses over the third electrical trace. A second trench may be etched in an area defined by the first trench and the patch area to remove material in the second layer exposed by the first trench, leaving material of the layer under the patch area.

Abstract: A semiconductor process is described. A substrate with at least one conductive region is provided, on which a dielectric layer is formed. An opening is formed in the dielectric layer, such that the conductive region is exposed. A first conductive layer is conformally formed on the surface of the opening. A first cleaning step is conducted using a first cleaning solution. A baking step is conducted after the first cleaning step. Afterwards, the opening is filled with a second conductive layer.

Abstract: The present invention provides a semiconductor device and a method of manufacturing the same. According to an embodiment of the present invention, a silicon oxide layer is formed over lower electrode contact plugs by using a selective oxidation process, wherein the silicon oxide layer has a thickness greater than an oxidized portion of an adjacent isolation layer (i.e., an isolation insulating layer). Accordingly, a concave contact area between a lower electrode and the lower electrode contact plug can be desirably be secured following etching of the silicon oxide layer in a subsequent process. Specifically, a width of the adjacent isolation layer does not need to be increased because sequential dry and wet etch processes expose the lower electrode contact plugs in a process of forming the lower electrodes.

Abstract: When performing plasma assisted etch processes for patterning complex metallization systems of microstructure devices, the probability of creating plasma-induced damage, such as arcing, may be reduced or substantially eliminated by using a superior ramp-up system for the high frequency power and the low frequency power. To this end, the high frequency power may be increased at a higher rate compared to the low frequency power component, wherein, additionally, a time delay may be applied so that, at any rate, the high frequency component reaches its target power level prior to the low frequency component.

Abstract: A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack of at least one semiconductor device. In one embodiment, the noble metal-containing material is plug located within the lower region of the contact opening and an upper region of the contact opening includes a conductive metal-containing material. The conductive metal-containing material is separated from plug of noble metal-containing material by a bottom walled portion of a U-shaped diffusion barrier. In another embodiment, the noble metal-containing material is present throughout the entire contact opening.

Abstract: A system on chip comprising a RF shield is disclosed. In one embodiment, the system on chip includes a RF component disposed on a chip, first redistribution lines disposed above the system on chip, the first redistribution lines coupled to I/O connection nodes. The system on chip further includes second redistribution lines disposed above the RF component, the second redistribution lines coupled to ground potential nodes. The second redistribution lines include a first set of parallel metal lines coupled together by a second set of parallel metal lines.

Abstract: A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness TPSD. The FDC has patterned back-face carrier metallizations contacting the front-face device metallization pads, patterned front-face carrier metallization pads and numerous parallelly connected through-carrier conductive vias respectively connecting the back-face carrier metallizations to the front-face carrier metallization pads. The FDC thickness TFDC is large enough to provide structural rigidity to the VSLCPSD.

Abstract: The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

Abstract: There are provided a first waveguide member in an imaging region and a peripheral region of a semiconductor substrate and a via plug penetrating the first waveguide member.

Abstract: In a formation process of a semi-global interconnect in a Cu damascene multilayer wiring structure, it is the common practice, upon formation of the damascene wiring structure, to remove an etch stop insulating film from a via bottom by dry etching and then carry out nitrogen plasma treatment to reduce carbon deposits on the surface of the via bottom. Study by the present inventors has revealed that when a sequence of successive discharging for the removal of electrostatic charge by using nitrogen plasma and transportation of the wafer is performed, a Cu hollow is generated on the via bottom at the end of the via chain coupled to a pad lead interconnect having a length not less than a threshold value.

Abstract: Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.

Abstract: The present invention relates to a contact plug of a semiconductor device and a method of forming the same. The method includes forming an insulating layer over a semiconductor substrate, forming contact holes in the insulating layer, forming a first conductive layer over the insulating layer including the contact holes, etching the first conductive layer so that the first conductive layer remains at lower portions of the contact holes, wherein the insulating layer is also etched in order to widen upper widths of the contact holes, and forming a second conductive layer over the first conductive layer of the contact holes, thus forming the contact plugs.

Abstract: A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask.

Abstract: A wiring structure of a semiconductor device, includes: an insulating layer formed on a base member; a first metal layer covered with the insulating layer; a second metal layer having a plurality of electrode parts which are arranged on the insulating layer to be spaced from each other and which have a thickness larger than the first metal layer, the insulating layer having a plurality of via holes which connect the first metal layer and the plurality of electrode parts; and a plurality of through wiring lines which are located within the plurality of via holes and which electrically connect the plurality of electrode parts to the first metal layer.

Abstract: The present invention relates to a semiconductor device structure and a method for manufacturing the same; the structure comprises: a semiconductor substrate on which a device structure is formed thereon; an interlayer dielectric layer formed on the device structure, wherein a trench is formed in the interlayer dielectric layer, the trench comprises an incorporated via trench and a conductive wiring trench, and the conductive wiring trench is positioned on the via trench; and a conductive layer filled in the trench, wherein the conductive layer is electrically connected with the device structure; wherein the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. Wherein, the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material.

Abstract: An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line.

Abstract: A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has no significant effect in the chemical-mechanical polishing (CMP) process. The noble metal liner layer may be completely removed by sputter etching to facilitate effective planarization by chemical-mechanical polishing to take place.

Abstract: Embodiments of the present invention provide a method of forming borderless contact for transistor. The method may include forming a gate of a transistor, on top of a substrate, and spacers adjacent to sidewalls of the gate; forming a sacrificial layer surrounding the gate; causing the sacrificial layer to expand in height to become higher than the gate, the expanded sacrificial layer covering at most a portion of a top surface of the spacers and thereby leaving an opening on top of the gate surrounded by the spacers; filling the opening with a dielectric cap layer; replacing the expanded sacrificial layer with a dielectric layer; and forming a conductive stud contacting source/drain of the transistor, the conductive stud being isolated from the gate by the dielectric cap layer.

Abstract: A method of manufacturing a memory device is disclosed. The method includes providing a substrate, forming a number of memory sectors on the substrate, wherein each of the memory sectors is coupled to an adjacent one via a first diffused region in the substrate and is coupled to another adjacent one via at least one second diffused region in the substrate, forming a first dielectric layer on the memory sectors, forming a first conductive structure through the first dielectric layer to the first diffused region, and at least one second conductive structure through the first dielectric layer to the at least one second diffused region, forming a patterned first mask layer on the first dielectric layer, the first conductive structure and the at least one second conductive structure, the patterned first mask layer exposing the first conductive structure, and etching back the first conductive structure.

Abstract: A method of fabricating an interconnect structure is provided. The method includes forming a hybrid photo-patternable dielectric material atop a substrate. The hybrid photo-patternable dielectric material has dual-tone properties with a parabola like dissolution response to radiation. The hybrid photo-patternable dielectric material is then image-wise exposed to radiation such that a self-aligned pitch split pattern forms. A portion of the self-aligned split pattern is removed to provide a patterned hybrid photo-patternable dielectric material having at least one opening therein. The patterned hybrid photo-patternable dielectric material is then converted into a cured and patterned dielectric material having the at least one opening therein. The at least one opening within the cured and patterned dielectric material is then filed with at least an electrically conductive material. Also provided are a hybrid photo-patternable dielectric composition and an interconnect structure.

Abstract: Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure that includes a gate structure overlying a semiconductor substrate and a doped region formed in the semiconductor substrate adjacent to the gate structure involves the steps of forming a first layer of dielectric material overlying the gate structure and the doped region, isotropically etching the first layer of dielectric material, forming a second layer of dielectric material overlying the first layer of dielectric material after isotropically etching the first layer, and forming a conductive contact that is electrically connected to the doped region within the first layer and the second layer.