Abstract: Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.

Abstract: A process for the production of a MWT silicon solar cell comprising the steps: (1) providing a p-type silicon wafer with (i) holes forming vias between the front-side and the back-side of the wafer and (ii) an n-type emitter extending over the entire front-side and the inside of the holes, (2) applying a conductive metal paste to the holes of the silicon wafer to provide at least the inside of the holes with a metallization, (3) drying the applied conductive metal paste, and (4) firing the dried conductive metal paste, whereby the wafer reaches a peak temperature of 700 to 900° C., wherein the conductive metal paste has no or only poor fire-through capability and comprises (a) at least one particulate electrically conductive metal selected from the group consisting of silver, copper and nickel and (b) an organic vehicle.

Abstract: A semiconductor device includes a lower layer wiring made of a conductive material; an etching stopper film laminated on the lower layer wiring and having a laminated structure including an SiCO layer and an SiCN layer; an interlayer insulating film laminated on the etching stopper film; an intermediate film laminated on the interlayer insulating film and made of a material having an etching selectivity with respect to a material of the etching stopper film; an upper wiring layer laminated on the intermediate film and having an upper groove formed in a top surface thereof; an upper layer wiring embedded in the upper groove and made of a metal material having Cu as a main component; and a via electrically connecting the lower layer wiring and the upper layer wiring and disposed in a via hole penetrating through the interlayer insulating film and the intermediate film.

Abstract: A method for manufacturing a semiconductor device is disclosed in which, after semiconductor function regions and patterns of interlayer insulating films including required contact holes are formed on one main surface side of a semiconductor substrate, an aluminum film or an aluminum alloy film which is thick is formed all over the main surface side of the semiconductor substrate and brought into conductive contact with the surface of the semiconductor substrate including bottom surfaces of the contact holes so as to form a required electrode film. Formation of the aluminum film or the aluminum alloy film is divided into a plurality of steps so that the thickness of the aluminum film or the aluminum alloy film is formed gradually, and between every two of the plurality of steps of forming the aluminum film or the aluminum alloy film, there is provided a step of performing isotropic etching to flatten irregularities in a surface of the aluminum film or the aluminum alloy film formed in the previous step.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applying unit that is configured to apply a bias voltage to the dummy pattern.

Abstract: A method for cleaning a semiconductor structure includes subjecting a semiconductor structure to an aqueous solution including at least one fluorine compound, and at least one strong acid, the aqueous solution having a pH of less than 1. In one embodiment, the aqueous solution includes water, hydrochloric acid, and hydrofluoric acid at a volumetric ratio of water to hydrochloric acid to hydrofluoric acid of 1000:32.5:1. The aqueous solution may be used to form a contact plug that has better contact resistance and improved critical dimension bias than conventional cleaning solutions.

Abstract: In one embodiment, a method is presented for formation of a through-silicon via in a silicon substrate. A via is etched in the silicon substrate. A first layer of oxide film is deposited on side walls of the via and on a first surface of the silicon substrate. At least a portion of the first layer of oxide film formed on the first surface of the silicon substrate is etched, and a second layer of oxide film is deposited on side walls of the via and. A conductor is deposited in the via.

Abstract: The present disclosure is directed to method of forming dummy structures in accordance with the golden ratio to reduce dishing and erosion during a chemical mechanical polish. The method includes determining at least one unfilled portion of a die prior to a chemical mechanical planarization and filling the at least one unfilled portion with a plurality of dummy structures, a ratio of the dummy structures to a total area of the unfilled portion being in the range of 36 percent and 39 percent. A die formed in accordance with the method may include a plurality of metal levels and a plurality of regions at each metal level, each region having a plurality of dummy structures formed as golden rectangles.

Abstract: A semiconductor package includes a semiconductor device, and a wiring board where the semiconductor device is mounted. The semiconductor device includes a semiconductor substrate, a piercing electrode configured to pierce the semiconductor substrate and electrically connect the wiring board and the semiconductor device, and a ring-shaped concave part provided so as to surround the piercing electrode, the ring-shaped concave part being configured to open to a wiring board side of the semiconductor substrate.

Abstract: Embodiments of the invention provide a method for depositing tungsten-containing materials. In one embodiment, a method includes forming a tungsten nucleation layer over an underlayer disposed on the substrate while sequentially providing a tungsten precursor and a reducing gas into a process chamber during an atomic layer deposition (ALD) process and depositing a tungsten bulk layer over the tungsten nucleation layer, wherein the reducing gas contains hydrogen gas and a hydride compound (e.g., diborane) and has a hydrogen/hydride flow rate ratio of about 500:1 or greater. In some examples, the method includes flowing the hydrogen gas into the process chamber at a flow rate within a range from about 1 slm to about 20 slm and flowing a mixture of the hydride compound and a carrier gas into the process chamber at a flow rate within a range from about 50 sccm to about 500 sccm.

Abstract: A metal wiring layer and a method of fabricating the metal wiring layer are provided. The method includes forming a dielectric layer on a substrate, forming a plurality of dielectric layer patterns and holes therein on the substrate by etching part of the dielectric layer, with a cross sectional area of the holes in the dielectric layer patterns decreasing with increasing distance away from the substrate and the holes exposing the substrate, forming a trench by etching a portion of the substrate exposed through the holes in the dielectric layer patterns, and forming a metal layer which fills the trench and the holes in the dielectric layer patterns. Thus, it is possible to prevent the occurrence of an edge build-up phenomenon by forming a metal layer in a plurality of holes in the dielectric layer patterns having a cross sectional area decreasing with increasing distance away from the substrate.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes: preparing a substrate with an etching target, and etching the etching target through a plasma-free etching process that uses an etching gas including one of interhalogen compound, F2, XeF2 and combinations thereof.

Abstract: An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.

Abstract: Disclosed are a semiconductor package and a manufacturing method thereof. The semiconductor package can include a semiconductor substrate, having one surface on which a conductive pad is formed; an insulating layer, being formed on one surface of the semiconductor substrate; a metal post, penetrating through the conductive pad, the semiconductor substrate, and the insulating layer; and an outer-layer circuit, being electrically connected to the metal post. With the present invention, it can become unnecessary to form an additional via for electrically connecting both surfaces of the semiconductor substrate, thereby simplifying the manufacturing process, reducing the manufacturing cost, and improving the coupling reliability.

Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metal liner layers comprising cobalt and a metal selected from the group consisting of Ru, Pt, Ir, Pd, Re, or Rh. Devices having barrier layers comprising ruthenium and cobalt are provided. Methods include providing a substrate having a trench or via formed therein, forming a metal layer, the metal being selected from the group consisting of Ru, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer comprising a cobalt dopant, and depositing copper into the feature.

Abstract: Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction, and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions.

Abstract: Etched wafers and methods of forming the same are disclosed. In one embodiment, a method of etching a wafer is provided. The method includes forming a metal hard mask on the wafer using electroless plating, patterning the metal hard mask, and etching a plurality of features on the wafer using an etcher. The plurality of featured are defined by the metal hard mask.

Abstract: A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact.

Abstract: A method for fabricating through-silicon via structure includes the steps of: providing a semiconductor substrate; forming at least one semiconductor device on surface of the semiconductor substrate; forming a dielectric layer on the semiconductor device, in which the dielectric layer includes at least one via hole; forming a first conductive layer on the dielectric layer and filling the via hole; performing an etching process to form a through-silicon via in the first conductive layer, the dielectric layer, and the semiconductor substrate; depositing a second conductive layer in the through-silicon via and partially on the first conductive layer; and planarizing a portion of the second conductive layer until reaching the surface of the first conductive layer.

Abstract: A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.

Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

Abstract: A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof.

Abstract: A process of forming an integrated circuit using a palladium CMP operation in which 25 to 125 ppm aluminum is added to the CMP slurry, allowing a palladium removal rate of at least 80 nanometers per minute at a polish pad pressure less than 9 psi and a surface speed between 1.9 and 2.2 meters per second. The palladium CMP operation may be applied to form a palladium bond pad cap after which an external bond element is formed on the palladium bond pad cap. Alternatively, the palladium CMP operation may be applied to form a palladium interconnect conductor in a first dielectric layer.

Abstract: A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs.

Abstract: A method of forming metal lines of a semiconductor device includes forming an etch stop layer over a semiconductor substrate over which underlying structures are formed, forming an insulating layer over the etch stop layer, etching the etch stop layer and the insulating layer to form trenches through which the underlying structures are exposed, shrinking the insulating layer by using a thermal treatment process in order to widen openings of the trenches, and filling the trenches with a conductive material.

Abstract: A method of manufacturing a semiconductor device including a plurality of hole patterns is disclosed. The method includes: forming a plurality of first line patterns and a plurality of first space patterns extending in a first direction; forming a plurality of second line patterns and a plurality of second space patterns extending in a second direction, on the plurality of first line patterns and the plurality of first space patterns; forming a plurality of first hole patterns where the plurality of first space patterns and the plurality of second space patterns cross each other; and forming a plurality of second hole patterns where the plurality of first line patterns and the plurality of second line patterns cross each other.

Abstract: A Cu-CMP step applied to processes for 130 nm, 90 nm, and 65 nm technical nodes or the like mainly employs slurry to which an anticorrosive agent is added for preventing corrosion of Cu wiring. The inventors of the present application have studied and clearly found that in the Cu-CMP step using the slurry with the anticorrosive agent added thereto, the anticorrosive agent often forms complexes with Cu, which remain as foreign matter on a wafer in large quantity, leading to a reduction in yield, and in reliability of TDDB characteristics of the Cu wiring. In the invention of the present application, a post-CMP cleaning process involves applying wet cleaning to a wafer by supplying a cleaning solution, such as a chemical solution or pure water, to a device surface of the wafer substantially in a vertical direction with respect to the horizontal device surface, while rotating the wafer substantially about its center in the horizontal plane.

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (?) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming conductive patterns on a substrate; forming an interlayer dielectric between the conductive patterns; defining contact holes in the interlayer dielectric to expose portions of the substrate between the conductive patterns; forming a first conductive layer on a surface including the contact holes; forming contact plugs in such a way as to be isolated in the respective contact holes, by etching a surface of the first conductive layer to expose upper end surfaces of the conductive patterns; etching a partial thickness of the conductive patterns so that the upper end surfaces of the conductive patterns are lower than an upper end surface of the interlayer dielectric; and forming an insulation layer on the resultant structure.

Abstract: A method for manufacturing a semiconductor device includes providing a patterned hard-mask layer. The hard-mask layer is provided on an exposed surface of one or more layers to be patterned of a semiconductor intermediate product. The hard-mask layer covers the exposed surface in covered areas of the one or more layers to be patterned and does not cover the exposed surface in bared areas of the one or more layers to be patterned. One or more recesses are formed in the layers to be patterned by at least partially removing the layers to be patterned in the bared areas. The hard-mask layer is ten removed. After removing the hard-mask layer the recess is filled with a filling material.

Abstract: An integrated circuit includes a metal seed layer contacting a metal element of a top interconnect layer, a plated copper pad over the seed layer, a plated metal cap layer on the top surface of the copper pad, an upper protective overcoat covering a lateral surface of the copper pad and overlapping a top surface of the cap layer with a bond pad opening exposing the cap layer, and a bond pad of electroless plated metal in the bond pad opening.

Abstract: A wiring substrate is provided with a first wiring layer including a first land, a first insulative layer formed on the first wiring layer, a second wiring layer formed on the first insulative layer, a second insulative layer formed on the second wiring layer, and a via formed extending through the first insulative layer and the second insulative layer in a thicknesswise direction. The via includes one end, which is electrically connected to the first land of the first wiring layer, and another end, which is located opposed to the one end and serves as a pad to which a mounted electronic component is electrically connected. The second wiring layer includes a coupling portion electrically connected to the via. The coupling portion of the second wiring has a width that is smaller than a diameter of the via.

Abstract: A method for manufacturing a semiconductor device includes forming a gate insulating layer, a gate and a protective layer on a semiconductor substrate, forming a spacer on lateral sides of the protective layer and the gate, forming one or more junction regions in the semiconductor substrate at sides of the gate, partially filling a gap between adjacent gates by selectively forming a conductive layer on an exposed portion of the semiconductor substrate between the adjacent gates, forming an insulating layer over the semiconductor substrate so as to fill a full height of the gap between the adjacent gates, and forming a contact hole partially exposing the conductive layer by etching the insulating layer.

Abstract: A first metal mask has a portion exposed at an opening of a second metal mask. The second metal mask is formed to be thicker than the first metal mask. The thickness of the first and second metal masks is such that the etching at an opening of the first mask reaches a source electrode when the etching at the opening of the second mask substantially reaches a semiconductor device forming layer.

Abstract: A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

Abstract: A device includes a semiconductor substrate including a front side and a backside. A through-substrate via (TSV) penetrates the semiconductor substrate. A dummy metal line is formed on the backside of the semiconductor substrate, and may be connected to the dummy TSV.

Abstract: A method for fabricating a metal redistribution layer is described. A first opening and a second opening are formed in a dielectric layer over a first region and a second region thereof, respectively. A plurality of third openings are formed in the dielectric layer exposed by the first opening in the first region and a plurality of fourth openings are formed in the dielectric layer exposed by the second opening in the second region. A metal material is formed over the dielectric layer and in the first, second, third and fourth openings. A plurality of recesses is formed in the metal materials overlying the third and fourth openings. The metal material in the first region is patterned by using the recesses formed in portions of the metal material overlying the fourth openings in the second region as an alignment mark to form a metal redistribution layer.

Abstract: A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface.

Abstract: The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.

Abstract: The invention provides a semiconductor device comprising: a substrate; a gate, which is formed on the substrate; a source and a drain, which are located on opposite sides of the gate, respectively; a contact, which contacts with the source and/or the drain, wherein the contact has an enlarged end at an end which is in contact with the source and/or the drain. In the present invention, since the contact area of the contact is increased on the interface in contact with the source/the drain, the contact resistance can be reduced, and thus the performances of the semiconductor device can be guaranteed/improved. The present invention further provides a method of fabricating the semiconductor device (especially the contact therein) as previously described.

Abstract: A method for fabricating a semiconductor device includes forming first plugs over a substrate, forming contact holes that expose the first plugs, ion-implanting an anti-diffusion material into the first plugs, and forming second plugs filling the contact holes.

Abstract: A method of fabricating a phase change memory device includes the use of first, second and third polishing processes. The first polishing process forms a first contact portion using a first sacrificial layer and the second polishing process forms a phase change material pattern using a second sacrificial layer. After removing the first and second sacrificial layers to expose resultant protruding structures of the first contact portion and the phase change material pattern, a third polishing process is used to polish the resultant protruding structures using an insulation layer as a polishing stopper layer.

Abstract: Methods of making interconnect structures are provided. In one aspect of the innovation, when forming a trench or via in a dielectric layer, the sidewall surface of another via and/or trench is covered with a metal oxide layer. The metal oxide layer can prevent and/or mitigate surface erosion of the sidewall surface. As a result, the methods can improve the controllability of critical dimensions of the via and trench.

Abstract: The present invention provides a semiconductor device including at least one of an insulating layer and a semiconductor layer each including a hole formed therein, and a through electrode provided in the hole. In the semiconductor device, the side wall of the hole is constituted of a first region from the opening of the hole to a predetermined position between the opening of the hole and the bottom surface of the hole, and a second region from the predetermined position to the bottom surface of the hole. The through electrode includes a seed layer and a plating layer. The seed layer covers the second region and the bottom surface of the hole without covering the first region. In addition, the plating layer covers the seed layer and at least a part of the first region.

Abstract: A method for semiconductor fabrication includes etching a via and a trench in a dielectric material to yield an etched surface. The dielectric material may have an ultra-low K value (e.g., a K-value of less than or equal to 2.4). The etched surface is then processed with a gas-phase silylation process to yield a silylated surface. The silylated surface is processed with a plasma treatment process to yield a plasma treated surface. The plasma treated surface, in turn, is processed with a dilute hydrofluoric acid before a conductive metal is deposited in the via and the trench. Inclusion of the plasma treatment process reduces hollow metal defects caused by the silylation process and increases reliability of metal interconnects and improves barrier metallization.

Abstract: The present invention relates to a metal wiring of a semiconductor device and a method for the same, and is directed to disclose a technique forming an additional conductive layer within the metal line, which acts as an etching barrier to increase the etching margin and to improve the RC characteristics between the metal lines, which can prevent the Cu migration.

Abstract: A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.

Abstract: A method and structure of connecting at least two integrated circuits in a 3D arrangement by a through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit.

Abstract: By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.