Abstract: A method for fabricating a capacitor in a semiconductor device includes forming an insulation layer over a substrate, forming a storage node contact plug passing through the insulation layer and coupled to the substrate, recessing the storage node contact plug to a certain depth to obtain a sloped profile, forming a barrier metal over the surface profile of the recessed storage node contact plug, forming a sacrificial layer over the substrate structure, etching the sacrificial layer to form an opening exposing the barrier metal, forming a bottom electrode over the surface profile of the opening, and removing the etched sacrificial layer.

Abstract: A semiconductor device includes a silicon substrate, a capacitor element having a lower electrode, a capacitor dielectric film, a TiN film, and a W film, and an interlayer insulation film covering the end and a portion of the upper surface of the lower electrode and disposed with a concave portion at a position corresponding to the lower electrode. The lower electrode is disposed selectively at the bottom of the concave portion, the upper surface of the lower electrode is exposed from the interlayer insulation film in the region for forming the concave portion, the side wall for the concave portion of the interlayer insulation film situates to the inner side of the lower electrode from the end of the lower electrode, and the capacitor dielectric film is disposed so as to cover the upper surface of the lower electrode and cover the interlayer insulation from the side wall for the concave portion to the upper surface of the interlayer insulation film.

Abstract: There is provided a semiconductor device comprising a dielectric film made of a high dielectric constant material, in which a leak current is reduced in the film and which exhibits improved device reliability. Specifically, a dielectric film 142 is a metal-compound film having a composition represented by the formula MOxCyNz wherein x, y and z meet the conditions: 0<x, 0.1?y?1.25, 0.01?z and x+y+z=2; and M comprises at least Hf or Zr.

Abstract: A method of manufacturing a semiconductor device includes forming an inter-layer insulating film; arranging a plurality of grooves in a surface layer of the inter-layer insulating film; forming embedded insulating films which are embedded in the grooves; arranging a plurality of holes in the inter-layer insulating film and between the embedded insulating films, in a manner such that each hole between the embedded insulating films partially overlaps therewith; forming lower electrodes, each of which has a bottom and a side face, and covers the bottom and side faces of the corresponding hole; forming a capacitance insulating film which covers the lower electrodes; and forming an upper electrode which further covers the capacitance insulating film.

Abstract: Some embodiments include methods of forming capacitors. A first capacitor storage node may be formed within a first opening in a first sacrificial material. A second sacrificial material may be formed over the first capacitor storage node and over the first sacrificial material, and a retaining structure may be formed over the second sacrificial material. A second opening may be formed through the retaining structure and the second sacrificial material, and a second capacitor storage node may be formed within the second opening and against the first storage node. The first and second sacrificial materials may be removed, and then capacitor dielectric material may be formed along the first and second storage nodes. Capacitor electrode material may then be formed along the capacitor dielectric material. Some embodiments include methods of forming DRAM unit cells, and some embodiments include DRAM unit cell constructions.

Abstract: Provided is a method for manufacturing a semiconductor device having a 4F2 transistor. In the method, a gate stack is formed on a semiconductor substrate. A first interlayer dielectric including a contact hole which includes a first region and second regions Spacer layers are formed on both sides of the gate stack and a portion of the second region. Landing plugs are formed on the contact hole, a portion of the semiconductor substrate exposed by a thickness of the spacer layer, and a lateral side of the trench. A second interlayer dielectric is formed to separate the landing plug. The bit line contact plug is connected to a first portion of the landing plug that extends to the lateral side of the trench. The bit line stack is connected to the bit line contact plug. The storage node contact plug is connected to the first portion and a second portion of the landing plug located at a corresponding position in a diagonal direction.

Abstract: A ferroelectric capacitor is formed over a semiconductor substrate (10), and thereafter, interlayer insulating films (48, 50, 52) covering the ferroelectric capacitor are formed. Next, a contact hole (54) reaching a top electrode (40) is formed in the interlayer insulating films (48, 50, 52). Next, a wiring (58) electrically connected to the top electrode (40) through the contact hole (54) is formed on the interlayer insulating films (48, 50, 52). At the time of forming the top electrode (40), conductive oxide films (40a, 40b) are formed, and then a cap film (40c) composed of a noble metal exhibiting less catalytic action than Pt and having a thickness of 150 nm or less is formed on the conductive oxide films (40a, 40b).

Abstract: A semiconductor memory device comprises a heater electrode, a phase change portion, a heat insulation portion and an upper electrode. The phase change portion comprises a concave portion and a contact portion. The concave portion is in contact with the heater electrode. The contact portion is formed integrally with the concave portion. The heat insulation portion is formed in the concave portion. The upper electrode is formed on the contact portion and the heat insulation portion so that the heat insulation portion is positioned between the concave portion and the upper electrode.

Abstract: A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.

Abstract: A method for forming a capacitor of a semiconductor device includes forming a first insulation layer having a storage node plug on a semiconductor substrate; forming an etch stop layer and a second insulation layer sequentially on the substrate having the first insulation layer; forming a hole exposing a portion of the storage node plug by selectively etching the second insulation layer by using the etch stop layer; recessing a portion of the storage node plug exposed by the hole; forming a barrier metal layer on a surface of the recessed storage node plug; forming a storage node electrode connected to the storage node plug through the barrier metal layer in the hole; and forming a dielectric layer and a metal layer for a plate electrode sequentially on the storage node electrode.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a transistor including: a source, a drain and a gate; first and second plugs on the source and the drain; a third plug on the gate to have a top face higher than that of the first plug; an interlayer insulating film covering the transistor and the first to the third plugs; a ferroelectric capacitor on the interlayer insulating film, one electrode thereof being connected to the first plug; a barrier film covering surfaces of the ferroelectric capacitor and the interlayer insulating film to prevent a substance affecting the ferroelectric capacitor from entering therethrough; and fourth and fifth plugs disposed on the second and the third plugs and connected thereto through connection holes formed in the barrier film.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.

Abstract: Method of forming a high-reliability contact plug which prevents a short circuit between the plug and a bit line by applying a material having an etching rate ratio of 100 or more with respect to a silicon nitride film which forms a self-aligned contact plug. After the formation of a bit line, whose top surface and side surfaces are covered with a silicon nitride film, a sacrificial interlayer film is formed which covers the whole surface of the bit line, and a contact hole is formed by etching the sacrificial interlayer film and then the lower-layer interlayer insulating film to form a capacitance contact plug. A column of a capacitance contact plug is then formed by removing the sacrificial interlayer film, a third interlayer insulating film is formed on the column, and part of this interlayer is removed to expose a surface of the contact plug.

Abstract: Some embodiments include memory cells that contain a dynamic random access memory (DRAM) element and a nonvolatile memory (NVM) element. The DRAM element contains two types of DRAM nanoparticles that differ in work function. The NVM contains two types of NVM nanoparticles that differ in trapping depth. The NVM nanoparticles may be in vertically displaced charge-trapping planes. The memory cell contains a tunnel dielectric, and one of the charge-trapping planes of the NVM may be further from the tunnel dielectric than the other. The NVM charge-trapping plane that is further from the tunnel dielectric may contain larger NVM nanoparticles than the other NVM charge-trapping plane. The DRAM element may contain a single charge-trapping plane that has both types of DRAM nanoparticles therein. The memory cells may be incorporated into electronic systems.

Abstract: A manufacturing method of a semiconductor device having a highly reliable capacitor, and the semiconductor device are provided.

Abstract: Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode formed on the same layer as the light blocking film and the second electrode formed from a semiconductor film of the same composition as the drain region, and the first base insulating film is removed at the part of the storage capacitance so that the second base insulating film is used as the dielectric of the storage capacitance. This structure provides a large storage capacitance in a small area.

Abstract: HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.

Abstract: In an embodiment, a storage electrode of a capacitor in a semiconductor device is resistant to inadvertent etching during its manufacturing processes. A method of forming the storage electrode of the capacitor is described. The storage electrode of the capacitor may include a first metal layer electrically connected with a source region of a transistor through a contact plug penetrating an insulating layer on a semiconductor substrate. A polysilicon layer may then be formed on the first metal layer. A second metal layer is formed on the polysilicon layer.

Abstract: The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.

Abstract: Dynamic random access memory (DRAM) devices include first node pads and second node pads alternately arranged in a first direction on a substrate to form a first pad column. A width of the second node pads in a second direction, perpendicular to the first direction, is greater than a width of the first node pads in the second direction. Storage electrodes are electrically connected to the first node pads and the second node pads. Bit line pads may be arranged in the first direction on the substrate to form a second pad column. The second pad column is adjacent the first pad column and displaced therefrom in the second direction.

Abstract: A method for fabricating a storage node contact in a semiconductor device includes forming a landing plug over a substrate, forming a first insulation layer over the landing plug, forming a bit line pattern over the first insulation layer, forming a second insulation layer over the bit line pattern, forming a mask pattern for forming a storage node contact over the second insulation layer, etching the second and first insulation layers until the landing plug is exposed to form a storage node contact hole including a portion having a rounded profile, filling a conductive material in the storage node contact hole to form a contact plug, and forming a storage node over the contact plug.

Abstract: A storage capacitor includes a first capacitor portion and a second capacitor portion, the second capacitor portion being disposed above the first capacitor portion, thereby defining a first direction. The first and the second portions each include a hollow body made of a conductive material, respectively, thereby forming a first capacitor electrode. An upper diameter of each of the hollow bodies is larger than a lower diameter of the hollow body, the diameter being measured perpendicularly with respect to the first direction. The storage capacitor also includes a second capacitor electrode and a dielectric material disposed between the first and the second capacitor electrodes. The storage capacitor also includes an insulating material disposed outside the hollow bodies, and a layer of an insulating material. A lower side of the insulating layer is disposed at a height of an upper side of the first capacitor portion.

Abstract: Disclosed herein is a method of fabricating a memory device. The method includes forming an etch stop layer, bit lines, and a first hard mask pattern over a semiconductor substrate. A first SNC plug is formed between the bit lines, and an etch process is performed to reduce the height of the first hard mask pattern and the first SNC plug, to increase a top width of the first hard mask pattern, and to reduce a top width of the first SNC plug. The method also includes forming a second hard mask pattern on the first hard mask pattern, and forming a second SNC plug between the second hard mask patterns.

Abstract: A method of fabricating an image sensor which reduces fabricating costs through simultaneous formation of capacitor structures and contact structures may be provided. The method may include forming a lower electrode on a substrate, forming an interlayer insulating film on the substrate, the interlayer insulating film may have a capacitor hole to expose a first portion of the lower electrode.

Abstract: A semiconductor device provided with a field-effect transistor, the field-effect transistor including: a active region defined by element isolating region 3 formed on semiconductor substrate 1; gate electrode 5 provided so as to intersect the active region and having at least a part thereof embedded in a gate trench formed on semiconductor substrate 1; and SOI structure channel layer 4 formed in the active region so that one lateral face thereof is opposite to a part of gate electrode 5 embedded in the gate trench and the other lateral face thereof is in contact with a lateral face of element isolating region 3, wherein impurity diffusion layer 5 that functions as a source/drain region is disposed above channel layer 4, and impurity diffusion layer 9 and channel layer 4 are formed spaced apart from each other.

Abstract: When adopting a stack-type capacitor structure for a ferroelectric capacitor structure (30), an interlayer insulating film (27) is formed between a lower electrode (39) (or a barrier conductive film) and a conductive plug (22) to eliminate an impact of orientation/level difference on a surface of the conductive plug (22) onto the ferroelectric film (40). Differently from a conductive film like the lower electrode (39) or the barrier conductive film, the interlayer insulating film (27) can be formed without inheriting the orientation/level difference from its lower layers by planarizing the surface thereof.

Abstract: Container capacitor structure and method of construction. An etch mask and etch are used to expose portions of an exterior surface of an electrode (“bottom electrodes”) of the structure. The etch provides a recess between proximal pairs of container capacitor structures, which is available for forming additional capacitance. A capacitor dielectric and top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Surface area common to both the first electrode and second electrodes is increased over using only the interior surface, providing additional capacitance without decreasing spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

Abstract: In the process for manufacturing a semiconductor device of the present invention, a capacitor dielectric film is deposited via an atomic layer deposition employing an organic source material containing one or more metallic element(s) selected from the group consisting of Zr, Hf, La and Y as a deposition gas. The process for manufacturing a capacitor of the present invention includes obtaining a boundary temperature T (degree C.), at which an increase in a deposition rate for depositing the capacitor dielectric film as increasing the temperature is detected, on the basis of a correlation data of a deposition temperature in the atomic layer deposition employing the deposition gas with a deposition rate for depositing the capacitor dielectric film at the deposition temperature (S100 and S102); and depositing the capacitor dielectric film via the atomic layer deposition employing the deposition gas at a temperature within a range of from (T?20) (degree C.) to (T+20) (degree C.) (S104 to S112).

Abstract: A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause device failure.

Abstract: A method of fabricating a capacitor over bit line (COB) is provided. First, a substrate is provided and a plurality of word lines is formed on the substrate. Next, a plurality of landing plug contacts (LPCs) are formed between the word lines and a plurality of first contacts is then formed on the LPCs. Thereafter, a plurality of second contacts is formed on a first portions of the first contacts and a plurality of bit lines connecting a second portions of the first contacts is formed, simultaneously. An inter-layer dielectric (ILD) layer is formed on the substrate to cover the second contacts and the bit lines. Subsequently, a plurality of capacitors is formed in the ILD layer. Thus, the fabrication of the capacitor is simplified.

Abstract: A method for fabricating a semiconductor device includes forming an insulation structure over a substrate structure including contact plugs, etching the insulation structure to form opening regions each of which has a lower opening portion having a critical dimension wider than an upper opening portion, and forming a conductive layer contacting the contact plugs inside the opening regions.

Abstract: This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier structure encircling the polysilicon layer and the one or more barrier layers. In an alternate embodiment, a contact structure is fabricated by forming a polysilicon layer on a substrate, forming a tungsten nitride layer above the polysilicon layer, and etching the polysilicon layer and the tungsten nitride layer to a level below the surface of a substrate structure. A silicon nitride layer is formed above the tungsten nitride layer, and a ruthenium silicide layer is formed above the silicon nitride layer. The ruthenium silicide layer is then polished.

Abstract: As an oxygen diffusion prevention layer, a multilayer film formed by a metal nitride and a noble metal element. As an interlayer insulation film on the oxygen diffusion prevention layer, a plasma CVD oxide film is used. Moreover, as an interlayer insulation film on a capacitor, an ozone TEOS film is used.

Abstract: A multilayer electrode structure has a conductive layer including aluminum, an oxide layer formed on the conductive layer, and an oxygen diffusion barrier layer. The oxide layer includes zirconium oxide and/or titanium oxide. The oxygen diffusion barrier layer is formed at an interface between the conductive layer and the oxide layer by re-oxidizing the oxide layer. The oxygen diffusion barrier layer includes aluminum oxide.

Abstract: A method for production of a semiconductor device including the steps of: forming a gate insulating film, a polysilicon film and a first insulating film on a silicon substrate; patterning the first insulating film; forming a metal film; forming a silicide layer by reacting the polysilicon film with the metal film; forming a second insulating film after removing an unreacted metal film; removing the second insulating film such that the first insulating film is exposed and the second insulating film remains on a region which is not covered with the first insulating film; forming a gate electrode having a silicide layer on the upper layer side and a polysilicon layer on the lower layer side by carrying out etching using the second insulating film as a mask after removing the first insulating film; forming a third insulating film on the side surface of the gate electrode; and forming an interlayer insulating film and forming a contact hole therein.

Abstract: A radio frequency arrangement is disclosed, having a first semiconductor body with an integrated circuit formed therein and also with first and second terminal locations. A second semiconductor body with a charge store integrated therein and with a first and second contact locations is arranged with its contact locations mutually facing the terminal locations of the first semiconductor body. The first terminal and the first contact location and also the second terminal and the second contact location are coupled to one another in order thus to form an integrated circuit and also a charge store for supplying the integrated circuit. Realizing the integrated circuit and the charge store separately enables a simple and cost-effective manufacturing procedure for the individual components.

Abstract: A method for reducing the size of a patterned semiconductor feature includes forming a first layer over a substrate to be patterned, and forming a photoresist layer over the first layer. The photoresist layer is patterned so as to expose portions of the first layer, and the exposed portions of the first layer are removed in a manner so as to create an undercut region beneath the patterned photoresist layer. The patterned photoresist layer is reflowed so as to cause reflowed portions of the patterned photoresist layer to occupy at least a portion of the undercut region.

Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer, and portions of the electrode most distant from the substrate may be free of the insulating spacer. Related methods and structures are also discussed.

Abstract: A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are formed at the first region. After forming bitline pattern openings at the second region, poly spacers are formed on sidewalls of the cell bitline contacts and the bitline pattern openings. A substrate contact and a gate contact are then formed within the openings at the second region. After forming a trench around each of the substrate contact and the gate contact by performing an etching process, cell-bitline contact plugs, a substrate contact plug, and a gate contact plug are formed.

Abstract: A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a substrate, forming a conformal first barrier metal layer on the insulating layer pattern, and forming a second barrier metal layer on the first barrier metal layer in such a way that the second barrier metal layer will facilitate the growing of metal from the bottom of the recess such that the metal can fill a bottom part of the recess completely and thus, form damascene wiring. An etch stop layer pattern is formed after the damascene wiring is formed so as to fill the portion of the recess which is not occupied by the damascene wiring.

Abstract: A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

Abstract: A method of making a semiconductor structure includes etching an isolation oxide. The isolation oxide is in a substrate, a gate layer is on the substrate, a patterned metallic layer is on the gate layer, and a first patterned etch-stop layer is on the metallic layer.

Abstract: A method for forming a landing contact plug in a semiconductor device is provided. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer over the gate structures; planarizing the inter-layer insulation layer until the gate hard mask is exposed; forming an etch barrier layer on the inter-layer insulation layer; etching a predetermined portion of the inter-layer insulation layer by using the etch barrier layer as an etch barrier to form a plurality of contact holes; forming a conductive layer until the conductive layer fills the contact holes; removing surface roughness created during the formation of the conductive layer by a first etch-back process; and planarizing the conductive layer by a second etch-back process until the gate hard mask is exposed.

Abstract: A method for decreasing a PN junction leakage current of a dynamic random access memory (DRAM), includes the steps of: preparing an NMOS transistor formed on a P-type silicon substrate and comprising a drain; forming an insulation oxide layer on the P-type silicon substrate; etching the insulation oxide layer until the P-type silicon substrate is exposed so as to form a bit line contact hole on the drain; implanting arsenic ions into the P-type silicon substrate via the bit line contact hole to form an arsenic bit line contact window; and implanting phosphor ions into the P-type silicon substrate via the bit line contact hole to form a phosphor bit line contact window below the arsenic bit line contact window. In this way, a concentration gradient of N-type ions can be reduced at the bit line contact window, and further a PN junction leakage current can be reduced, thus lowing the power consumption of the DRAM when the DRAM is used in a low power consumption product.

Abstract: Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting layer has a compound formed from a reaction between the polymer or insulating oxide compound and a transition metal, a representative metal, or a metalloid.

Abstract: In a node structure under a capacitor in a ferroelectric random access memory device and a method of forming the same, top surfaces of the node structures are disposed at substantially the same level as a top surface of an interlayer insulating layer surrounding the node structures, and thus crystal growth of a ferroelectric in the capacitor can be stabilized. To this end, a node insulating pattern is formed on a semiconductor substrate. A node defining pattern surrounding the node insulating pattern is disposed under the node insulating pattern. A node conductive pattern is disposed between the node defining pattern and the node insulating pattern.

Abstract: A method includes preparing a semiconductor substrate having a cell region, a core NMOS region, and a core PMOS region; defining a cell active region, an NMOS active region, and a PMOS active region in the cell region, the core NMOS region, and the core PMOS region, respectively, by forming an isolation layer in predetermined regions of the semiconductor substrate; forming a cell gate pattern, an NMOS gate pattern, and a PMOS gate pattern crossing the cell active region, the NMOS active region, and the PMOS active region, respectively; forming an interlayer-insulating layer on the semiconductor substrate having the gate patterns; simultaneously forming a storage node landing pad, a bit line landing pad, and NMOS landing pads; and patterning the interlayer-insulating layer of the core PMOS region to form PMOS interconnection contact holes that expose predetermined regions of the PMOS active region adjacent to the PMOS gate pattern.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a sacrificial plug made of a first material surrounded by an isolation layer between two adjacent gate stacks in the first region; depositing a planarisation layer over said plurality of gate stacks in said first region and said at least one gate stack in said second region; backpolishing said planarisation layer such that the upper surface of said sacrificial plug is exposed; forming a structured hardmask layer made of said first material on said backpolished planarisation layer which structured hardmask layer adjoins said sacrificial plug and has at least one opening in said second region; forming at least one contact hole in said second region under said at least one opening in said second region, said at least one contact hole exposing a substra

Abstract: In a capacitor device of the present invention, a capacitor parts that has a pair of terminals on both end sides respectively is embedded in an insulating film in a state that a lower surface of the capacitor parts is not covered with the insulating film, then upper wiring patterns that are connected to upper surfaces of a pair of terminals via holes formed in the insulating film on a pair of terminals are formed on an upper surface side of the insulating film respectively, and then lower wiring patterns that are connected to lower surfaces of a pair of terminals are formed on a lower surface side of the insulating film respectively.

Abstract: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.