Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.

Abstract: Embodiments of three-dimensional (3D) memory devices formed by bonded semiconductor devices and methods for forming the same are disclosed. In an example, a method for forming a semiconductor device is disclosed. The method includes the following operations. First, an insulating material layer can be formed over a substrate. In an example, single-crystalline silicon is not essential to the substrate. The insulating material layer can be patterned to form an isolation structure and a plurality of trenches in the isolation structure. A semiconductor material can be deposited to fill up the plurality of trenches to form a plurality of array-base regions in the isolation structure, the isolation structure insulating the plurality of array-base regions from one another. Further, a plurality of memory arrays can be formed over the plurality of array-base regions, and an insulating structure can be formed to cover the plurality of memory arrays and the plurality of array-base regions.

Abstract: Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.

Abstract: Embodiments of the present disclosure provide a forming method of a semiconductor structure and a semiconductor structure. The forming method includes: providing a base, the base includes a central region and dummy regions, and the central region includes a molding region and cutting regions; forming multiple spaced core pillars on the base; forming an initial mask layer surrounding and covering a sidewall of each core pillar on the base; removing the initial mask layers located in each cutting region to form multiple spaced mask sidewall strips in the molding region, and retaining at least one of the initial mask layers in each dummy region as a ring-shaped sidewall; removing the core pillars located in the central region and the dummy regions; and etching the base to form multiple functional structures, and etching the base to form dummy functional structures on two sides of the multiple functional structures.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: Provided are a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a base; a bit line; and a semiconductor channel including a first doped region, a channel region, and a second doped region that are sequentially arranged, where the first doped region contacts the bit line, and the first doped region, the channel region, and the second doped region are doped with first-type doped ions. The channel region is further doped with second-type doped ions, enabling a concentration of majority carriers in the channel region to be less than a concentration of majority carriers in the first doped region and a concentration of majority carriers in the second doped region. The first-type doped ions are one of N-type ions or P-type ions, and the second-type doped ions are the other of N-type ions or P-type ions.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive region positioned in the substrate; a first gate structure positioned on the substrate; a first drain region positioned in the substrate and adjacent to one sidewall of the first gate structure; and a first extended conductive region positioned in the substrate, under the first drain region, contacting a bottom surface of the first drain region, and distant from the bottom conductive region. A top surface of the first drain region and a top surface of the substrate are substantially coplanar. The bottom conductive region and the first extended conductive region include the same electrical type. The first drain region and the first extended conductive region include different electrical types.

Abstract: A memory cell structure includes a silicon substrate, a transistor, a bit line, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The bit line is electrically coupled to the first conductive region of the transistor and positioned under the silicon surface. The capacitor is over the transistor and electrically coupled to the second conductive region of the transistor.

Abstract: A semiconductor device includes a semiconductor switching element having a drift layer, a body region, a first impurity region, trench gate structures, a high impurity concentration layer, an interlayer insulation film, an upper electrode and a lower electrode. The body region is arranged on the drift layer. The first impurity region is arranged in a surface portion of the body region in the body region and has an impurity concentration higher than the drift layer. Each of the trench gate structures includes a trench. A shield electrode, an intermediate insulation film and a gate electrode layer are stacked through an insulation film in the trench. The high impurity concentration layer is arranged on a side opposite to the body region to sandwich the drift layer between the high impurity concentration layer and the body region. The interlayer insulation film is arranged on the trench gate structures.

Abstract: A semiconductor device includes a substrate; an isolation structure over the substrate; a fin over the substrate and the isolation structure; a gate structure engaging a first portion of the fin; first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin; source/drain (S/D) features adjacent to the first sidewall spacers; and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride. The second sidewall spacers and the second portion of the fin include a same dopant, wherein the dopant includes phosphorus.

Abstract: Methods for depositing a metal containing material formed on a certain material of a substrate using an atomic layer deposition process for semiconductor applications are provided. In one embodiment, a method of forming a metal containing material on a substrate comprises pulsing a first gas precursor comprising a metal containing precursor to a surface of a substrate, pulsing a second gas precursor comprising a silicon containing precursor to the surface of the substrate, forming a metal containing material selectively on a first material of the substrate, and thermal annealing the metal containing material formed on the substrate.

Abstract: A manufacturing method for memory includes providing a substrate; forming a first isolation layer on the substrate; forming a first mask layer on the first isolation layer; forming a second isolation layer on the first mask layer and part of the first isolation layer; forming a second mask layer on the second isolation layer; removing part of the second mask layer and part of the second isolation layer; removing the first mask layer and the remaining second mask layer; forming a third mask layer on the first isolation layer and the remaining second isolation layer; removing part of the third mask layer; and etching the remaining part of the second isolation layer and the first isolation layer below the second isolation layer, by taking the remaining third mask layer as a mask.

Abstract: An approach for representing both positive and negative weights in neuromorphic computing is disclosed. The approach leverages a double gate FeFET (ferroelectric field effect transistor) device. The device leverages a double-gate FeFET with four terminals (two separate gates and source and drain) and ferroelectric gate dielectric. The device may have a junction-less channel. A synaptic weight is programmed by biasing one of the two gates. The store weight is sensed via a current flow from source to drain. A pre-defined bias is applied to the other gate during the sensing, such that a reference current is subtracted from the drain current. The net current for sensing is current from the synaptic devices subtracted by the pre-defined reference current.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, an NMOS transistor, and a PMOS transistor. The NMOS transistor includes a first dielectric layer, a first work function layer, and a first conductive layer that are stacked in sequence. The PMOS transistor includes a second dielectric layer, a second work function layer, and a second conductive layer that are stacked in sequence.

Abstract: A semiconductor device includes a substrate, a bottom etch stop layer over the substrate, a middle etch stop layer over the bottom etch stop layer, and a top etch stop layer over the middle etch stop layer. The top, middle, and bottom etch stop layers include different material compositions from each other. The semiconductor device further includes a dielectric layer over the top etch stop layer and a via extending through the dielectric layer and the top, middle, and bottom etch stop layers. The via has a first sidewall in contact with the dielectric layer and slanted inwardly from top to bottom towards a center of the via and a second sidewall in contact with the bottom etch stop layer and slanted outwardly from top to bottom away from the center of the via.

Abstract: An image sensor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a protection oxide film, and a nitride hard mask. The gate dielectric layer is over the semiconductor substrate. The gate electrode is over the gate dielectric layer. An entirety of a first portion of the gate dielectric layer directly under the gate electrode is of uniform thickness. The protection oxide film is in contact with a top surface of the gate electrode. The gate dielectric layer extends beyond a sidewall of the protection oxide film. The nitride hard mask is in contact with a top surface of the protection oxide film.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: Provided are a trench gate IGBT and a device. The trench gate IGBT includes an emitting electrode, a p well region, a gate, a gate oxide layer, a drift region and a back collecting electrode. The gate is located in a trench; the gate is isolated from the emitting electrode, the p well region and the drift region by the gate oxide layer; the trench is disposed inside a substrate; and recesses are provided at the boundary of the trench and the drift region. During switching on and off the trench gate IGBT, an interface between the drift region and a side surface of the trench is provided with recess gate oxide layers, so that electron charges can be restrained and accumulated, and improving the conduction capacity.

Abstract: A multi-junction VCSEL is formed by as a compact structure that reduces lateral current spreading by reducing the spacing between adjacent active regions in the stack of such regions used to from the multi-junction device. At least two of the active regions within the stack are located adjacent peaks of the intensity profile of the VCSEL, with an intervening tunnel junction positioned at a trough between the two peaks. The alignment of the active regions with the peaks maximizes the generated optical power, while the alignment of the tunnel junction with the trough minimizes optical loss. The close spacing on adjacent peaks forms a compact structure (which may even include a cavity having a sub-? optical length) that lessens the total path traveled by carriers and therefore reduces lateral current spread.

Abstract: The present disclosure provides a method for preparing a semiconductor device. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate. The method also includes depositing a dielectric layer over the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug. A first portion of the dielectric layer extends between the first metal plug and the second metal plug such that the first portion of the dielectric layer and the semiconductor substrate are separated by an airgap while a second portion of the dielectric layer extends between the third metal plug and the fourth metal plug such that the second portion of the dielectric layer is in direct contact with the semiconductor substrate.

Abstract: A method comprises forming a gate structure over a semiconductor substrate; etching back the gate structure; forming a gate dielectric cap over the etched back gate structure; depositing an etch-resistant layer over the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap and an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer and terminating prior to reaching the etch-resistant layer; performing a second etching process to deepen the gate contact opening, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer; and forming a gate contact in the deepened gate contact opening.

Abstract: The present disclosure provides a method for fabricating a semiconductor device with a carbon liner over a gate structure. The method includes forming a first gate structure over a semiconductor substrate; forming a first source/drain region in the semiconductor substrate, wherein the first source/drain region is adjacent to the first gate structure; conformally depositing a carbon liner over the first gate structure and the semiconductor substrate; forming a dielectric layer over the carbon liner; and forming a bit line contact penetrating through the dielectric layer and the carbon liner, wherein the bit line contact is electrically connected to the first source/drain region, and wherein the bit line contact is separated from the first gate structure by the carbon liner.

Abstract: The present disclosure technology provides memory cells and a semiconductor device including the same. According to the present technology, a semiconductor device comprises a plurality of active layers vertically stacked along a first direction over a substrate and horizontally extending along a second direction crossing the first direction; a plurality of bit lines coupled to respective first sides of the active layers and horizontally extending in a third direction crossing the first direction and the second direction; a plurality of capacitors coupled to respective second sides of the active layers; a word line vertically extending through the active layers along the first direction; an upper-level interconnection coupled to an upper end of the word line; and a lower-level interconnection coupled to a lower end of the word line.

Abstract: Solid state lighting (“SSL”) devices with improved current spreading and light extraction and associated methods are disclosed herein. In one embodiment, an SSL device includes a solid state emitter (“SSE”) that has a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The SSL device can further include a first contact on the first semiconductor material and a second contact on the second semiconductor material and opposite the first contact. The second contact can include one or more interconnected fingers. Additionally, the SSL device can include an insulative feature extending from the first contact at least partially into the first semiconductor material. The insulative feature can be substantially aligned with the second contact.

Abstract: Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Two word line plates in a same plane may be activated via a shared electrode. Memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

Abstract: A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a substrate; forming a second dielectric layer on the first dielectric layer; using a photomask to apply a photoresist to cover a first part of the second dielectric layer; removing a second part of the second dielectric layer while retaining the first part of the second dielectric layer; and removing the photoresist. The first part of the second dielectric layer covers a first part of the first dielectric layer in a first area. The second part of the second dielectric layer covers a second part of the first dielectric layer in a second area. The first area is corresponding to a memory device. The second area is corresponding to a logic device.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first bit line structure positioned above the substrate and including a first line portion arranged in parallel to a first direction, and a second line portion connecting to a first end of the first line portion and arranged in parallel to a second direction in perpendicular to the first direction; a first bit line top contact including a first bar portion positioned on the first end of the first line portion and arranged in parallel to the first direction, and a second bar portion connecting to a first end of the first bar portion, positioned on the second line portion, and arranged in parallel to the second direction; and a first top conductive layer electrically coupled to the first bit line top contact.

Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.

Abstract: The present disclosure provides a semiconductor device with a carbon liner over a gate structure and a method for forming the semiconductor device. The semiconductor device includes a gate structure disposed over a semiconductor substrate. The semiconductor device also includes a carbon liner covering a top surface and sidewalls of the gate structure and a top surface of the semiconductor substrate. The semiconductor device further includes a bit line contact disposed over the semiconductor substrate. The bit line contact extends over the gate structure, and the bit line contact is electrically separated from the gate structure by the carbon liner.

Abstract: A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate in the semiconductor substrate, a first STI structure in the semiconductor substrate and surrounding the first vertical diffusion plate, a second vertical diffusion plate in the semiconductor substrate and surrounding the first STI structure, and an ion well in the semiconductor substrate. The ion well is disposed directly under the first vertical diffusion plate, the first STI structure and the second vertical diffusion plate. The second vertical diffusion plate is electrically coupled to an anode of the capacitor structure. The first vertical diffusion plate is electrically coupled to a cathode of the capacitor structure.

Abstract: A Hall sensor structure comprising a semiconductor body of a first conductivity type, a well region of a second conductivity type extending from a top side of the semiconductor body into the semiconductor body, at least three first semiconductor contact regions of the second conductivity type, each extending from a top side of the well region into the well region, at least one second semiconductor contact region of a second conductivity type, wherein the first semiconductor contact regions are spaced apart from one another and from an edge of the well region, a metallic connection contact layer is arranged on each first semiconductor contact region, the at least one second semiconductor contact region extends along the top side of the semiconductor body at least partially around the well region.

Abstract: Disclosed is a display device that is capable of realizing low power consumption. The display device includes a first thin film transistor having a polycrystalline semiconductor layer in an active area and a second thin film transistor having an oxide semiconductor layer in the active area, thereby realizing low power consumption, wherein at least one opening disposed in a bending area has the same depth as one of a plurality of contact holes disposed in the active area, whereby the opening and the contact holes are formed through the same process, and the process is therefore simplified.

Abstract: A multi-junction VCSEL is formed by as a compact structure that reduces lateral current spreading by reducing the spacing between adjacent active regions in the stack of such regions used to from the multi-junction device. At least two of the active regions within the stack are located adjacent peaks of the intensity profile of the VCSEL, with an intervening tunnel junction positioned at a trough between the two peaks. The alignment of the active regions with the peaks maximizes the generated optical power, while the alignment of the tunnel junction with the trough minimizes optical loss. The close spacing on adjacent peaks forms a compact structure (which may even include a cavity having a sub-? optical length) that lessens the total path traveled by carriers and therefore reduces lateral current spread.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region and extends over the isolation structure, the semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, the first doped region extends across the first active region, the spacing region is over the isolation structure, and the spacing region is an undoped region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region.

Abstract: A semiconductor structure includes a substrate, first and second conductors, a passivation material, and a passivation sidewall block. The first and second conductors are on the substrate. The passivation material is between the first and second conductors. The passivation sidewall block is on sidewalls of the first and second conductors and the passivation material.

Abstract: A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate in the semiconductor substrate, a first STI structure in the semiconductor substrate and surrounding the first vertical diffusion plate, a second vertical diffusion plate in the semiconductor substrate and surrounding the first STI structure, and an ion well in the semiconductor substrate. The ion well is disposed directly under the first vertical diffusion plate, the first STI structure and the second vertical diffusion plate. The second vertical diffusion plate is electrically coupled to an anode of the capacitor structure. The first vertical diffusion plate is electrically coupled to a cathode of the capacitor structure.

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.

Abstract: The present disclosure describes apparatuses and methods for manufacturing programmable memory devices with optimized gate oxide thickness. In some aspects, lithography masks are used to fabricate oxide gates for programmable memory devices of an integrated-circuit (IC) die that are thinner than oxide gates fabricated for processor core devices of the IC die. In other aspects, lithography masks are used to fabricate oxide gates for the programmable memory devices of the IC die such that they are thicker than the oxide gates fabricated for the processor core devices of the IC die. By so doing, the programmable memory devices can be manufactured with optimized gate oxide thickness that may reduce programming voltage or increase device reliability of the programmable memory devices.

Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

Abstract: The present disclosure describes apparatuses and methods for manufacturing programmable memory devices with optimized gate oxide thickness. In some aspects, lithography masks are used to fabricate oxide gates for programmable memory devices of an integrated-circuit (IC) die that are thinner than oxide gates fabricated for processor core devices of the IC die. In other aspects, lithography masks are used to fabricate oxide gates for the programmable memory devices of the IC die such that they are thicker than the oxide gates fabricated for the processor core devices of the IC die. By so doing, the programmable memory devices can be manufactured with optimized gate oxide thickness that may reduce programming voltage or increase device reliability of the programmable memory devices.

Abstract: The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.

Abstract: A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first insulation layer. The silicon layer and the insulation layer are removed just from a second substrate area. A second insulation layer is formed over the silicon layer in the substrate first area and over the silicon in the second substrate area. A first plurality of trenches is formed in the first substrate area that each extends through all the layers and into the silicon. A second plurality of trenches is formed in the second substrate area that each extends through the second insulation layer and into the silicon. An insulation material is formed in the first and second trenches. Logic devices are formed in the first substrate area, and memory cells are formed in the second substrate area.

Abstract: A method for planarizing a semiconductor device is provided. The method includes steps hereinafter. A substrate is provided with a first dielectric layer covering at least one electrode structure formed thereon. A chemical-mechanical polishing (CMP) process is performed on the first dielectric layer until the at least one electrode structure is exposed. A second dielectric layer is deposited covering the at least one electrode structure and the first dielectric layer. An etching-back process is performed on the second dielectric layer until the at least one electrode structure is exposed.

Abstract: Semiconductor fins having isolation regions of different thicknesses on the same integrated circuit are disclosed. Nitride spacers protect the lower portion of some fins, while other fins do not have spacers on the lower portion. The exposed lower portion of the fins are oxidized to provide isolation regions of different thicknesses.

Abstract: Various embodiment integrate embedded dynamic random access memory with fin field effect transistors. In one embodiment, a first fin structure and at least a second fin structure are formed on a substrate. A deep trench area is formed between the first and second fin structures. A high-k metal gate is formed within the deep trench area. The high-k metal gate includes a high-k dielectric layer and a metal layer. A polysilicon material is deposited within the deep trench area adjacent to the metal layer. The high-k metal gate and the polysilicon material are recessed and etched to an area below a top surface of a substrate insulator layer. A poly strap is formed in the deep trench area. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first and second fin structures are electrically coupled to the poly strap.

Abstract: A method for selective oxidation of silicon containing materials in a semiconductor device is disclosed and claimed. In one aspect, a rapid thermal processing apparatus is used to selectively oxidize a substrate by in-situ steam generation at high pressure in a hydrogen rich atmosphere. Other materials, such as metals and barrier layers, in the substrate are not oxidized.

Abstract: In a semiconductor device of the invention, a semiconductor pillar configuring a vertical MOS transistor has an upper pillar having a first width and a lower pillar having a second width. A side surface of the upper pillar is covered with a second insulation film and a third insulation film and the lower pillar is covered with a first insulation film, which is a gate insulation film, from a side surface thereof to the second insulation film. A gate electrode is insulated from an upper conductive layer by the second and third insulation films.

Abstract: A DRAM cell structure with extended trench, the DRAM cell structure comprises: a NMOS transistor and a trench capacitor connected with the source electrode of the NMOS transistor; the trench capacitor comprises: a semiconductor substrate; a multilayer structure as the bottom plate of the trench capacitor, formed over the semiconductor substrate, which is composed of N-type SiGe layers and N-type Si layers arranged alternatively; a trench formed through the multilayer structure deeply into the semiconductor substrate, whose sidewall cross section is serrate-shaped; a dielectric layer formed on the inner face of the trench; a first polycrystalline silicon layer which is filled in the trench as the top plate of the trench capacitor; and a P-type Si layer formed over the multilayer structure. The present invention adopts doping epitaxial growth process to fabricate a multilayer structure composed of N-type SiGe layers and N-type Si layers arranged alternatively as the bottom plate of the trench capacitor.

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a simplified stacked structure and improved operation characteristics includes an upper chip, in which a plurality of pixels are arranged in a two-dimensional array structure, and a lower chip below the upper chip including a logic region having logic circuits and a memory region having embedded therein magnetic random access memory (MRAM) used as image buffer memory for storing image data processed by the logic region.