Transistor In U- Or V-shaped Trench In Substrate (epo) Patents (Class 257/E21.655)
  • Patent number: 10074654
    Abstract: Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.
    Type: Grant
    Filed: March 31, 2018
    Date of Patent: September 11, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Kazutaka Manabe, Noriaki Ikeda, Wei-Che Chang
  • Patent number: 9893168
    Abstract: A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a gate oxide layer and an adjacent dielectric layer. The boundary of the gate oxide layer and the dielectric layer is curved to avoid a sharp corner where the gate oxide layer meets the sidewalls of the trench.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: February 13, 2018
    Assignee: VISHAY-SILICONIX
    Inventors: Yang Gao, Kuo-In Chen, Kyle Terrill, Sharon Shi
  • Patent number: 9799660
    Abstract: Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: October 24, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert C. Wong, Lei Zhuang, Ananthan Raghunathan
  • Patent number: 9715316
    Abstract: A touch panel includes a dummy electrode capable of protecting a circuit included in the touch panel for shielding against static electricity.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: July 25, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Jae Joon Jang
  • Patent number: 9385224
    Abstract: An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterostructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: July 5, 2016
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Karen M. Renaldo, Eric J. Stewart, Robert S. Howell, Howell George Henry, Harlan Carl Cramer, Justin Andrew Parke, Matthew Russell King
  • Patent number: 9362421
    Abstract: In a semiconductor device, a support wall is formed between storage nodes to more effectively prevent leaning of a capacitor, and the storage nodes are formed using a damascene process, which may increase a contact area between each storage node and a storage node contact.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: June 7, 2016
    Assignee: SK HYNIX INC.
    Inventors: Cheol Hwan Park, Dong Sauk Kim
  • Patent number: 9041085
    Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove; a first fin structure underneath the first gate groove; a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove; and a second diffusion region in the semiconductor substrate. The second diffusion region covers a second side of the first gate groove. The second diffusion region has a bottom which is deeper than a top of the first fin structure.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: May 26, 2015
    Assignee: PS4 LUXCO S.A.R.L.
    Inventors: Kiyonori Oyu, Koji Taniguchi, Koji Hamada, Hiroaki Taketani
  • Patent number: 9006053
    Abstract: Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: April 14, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Ji Pan, Daniel Ng, Sung-Shan Tai, Anup Bhalla
  • Patent number: 9006063
    Abstract: A method for forming a trench MOSFET includes doping a body region of the trench MOSFET in multiple ion implantation steps each having different ion implantation energy. The method further comprises etching the trench to a depth of about 1.7 ?m.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 14, 2015
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Yean Ching Yong, Stefania Fortuna
  • Patent number: 8946026
    Abstract: A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: February 3, 2015
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Sukhun Choi, Boun Yoon, Jae-Jik Baek, Byung-Kwon Cho
  • Patent number: 8928071
    Abstract: A semiconductor device has a semiconductor substrate with a plurality of transistor cell regions. Each transistor cell region includes a plurality of trenches disposed in the semiconductor substrate, a well region between the plurality of trenches, and a source region of a MOSFET in the well region. A source electrode of the MOSFET is in contact with a top surface of the source region in each of the plurality of transistor cell regions. The source electrode is in contact with a part of a main surface of the semiconductor substrate so as to form a Schottky junction in a Schottky cell region disposed between the plurality of transistor cell regions. The Schottky junction is lower than a portion of the main surface between the Schottky junction and one of the transistor cell regions.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: January 6, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Patent number: 8900968
    Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate having a device isolation groove defining first to fourth device formation portions. The second device formation portion is separated from the first device formation portion. The third device formation portion extends from the first device formation portion. The third device formation portion is separated from the second device formation portion. The fourth device formation portion extends from the second device formation portion. The fourth device formation portion is separated from the first and third device formation portions. The third and fourth device formation portions are positioned between the first and second device formation portions.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: December 2, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Takeshi Kishida
  • Patent number: 8846538
    Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: September 30, 2014
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Bomy Chen, Long Ching Wang, Sychi Fang
  • Patent number: 8846515
    Abstract: Some embodiments include methods of forming contacts. A row of projections may be formed over a semiconductor substrate. The projections may include a plurality of repeating components of an array, and a terminal projection. The terminal projection may have a sacrificial material spaced from semiconductor material of the substrate by a dielectric structure. An electrically conductive line may be formed along the row. The line may wrap around an end of the terminal projection and bifurcate into two branches that are along opposing sides of the repeating components. The individual branches may have regions spaced from the sacrificial material by segments of gate dielectric. The sacrificial material may be removed, together with the segments of gate dielectric, to form a contact opening. An electrically conductive contact may be formed within the contact opening and directly against the regions of the branches.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Marcello Mariani, Micaela Gabriella Tomasini
  • Patent number: 8835254
    Abstract: A method of forming a device in each of vertical trench gate MOSFET region and control lateral planar gate MOSFET region of a semiconductor substrate is disclosed. A trench is formed in the substrate in the vertical trench gate MOSFET region, a first gate oxide film is formed along the internal wall of the trench, and the trench is filled with a polysilicon film. A LOCOS oxide film is formed in a region isolating the devices. A second gate oxide film is formed on the substrate in the lateral planar gate MOSFET region. Advantages are that number of steps is suppressed, the gate threshold voltage of an output stage MOSFET is higher than the gate threshold voltage of a control MOSFET, the thickness of the LOCOS oxide film does not decrease, and no foreign object residue remains inside the trench.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: September 16, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yoshiaki Toyoda, Takatoshi Ooe
  • Patent number: 8796126
    Abstract: A method of manufacturing a semiconductor device includes forming an insulating isolation portion in a groove of a substrate, forming a projection portion in which an upper portion of the insulating isolation portion projects from a principal surface of the substrate, forming a sidewall spacer covering a side surface of the projection portion and part of the principal surface of the substrate along the side surface of the projection portion, and forming a first trench in the substrate by etching the substrate using the sidewall spacer as a mask.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 5, 2014
    Assignee: PS4 Luxco, S.a.r.l.
    Inventor: Koji Taniguchi
  • Patent number: 8785280
    Abstract: A body layer is formed in an epitaxial layer and a gate electrode formed in a trench in the body and epitaxial layer. A gate insulator is disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the epitaxial layer. A cap insulator is disposed on top of the gate electrode. A doped spacer is disposed along a sidewall of the source and a sidewall of the gate insulator. The body layer next to the polysilicon spacer is etched back below the bottom of the polysilicon spacer. Dopants are diffused from the spacer to form the source region.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: July 22, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: François Hébert
  • Patent number: 8778757
    Abstract: In methods of manufacturing a DRAM device, a buried-type gate is formed in a substrate. A capping insulating layer pattern is formed on the buried-type gate. A conductive layer pattern filling up a gap between portions of the capping insulating layer pattern, and an insulating interlayer covering the conductive layer pattern and the capping insulating layer pattern are formed. The insulating interlayer, the conductive layer pattern, the capping insulating layer pattern and an upper portion of the substrate are etched to form an opening, and a first pad electrode making contact with a first pad region. A spacer is formed on a sidewall of the opening corresponding to a second pad region. A second pad electrode is formed in the opening. A bit line electrically connected with the second pad electrode and a capacitor electrically connected with the first pad electrode are formed.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Chul Park, Sang-sup Jeong
  • Patent number: 8766317
    Abstract: Provided is a semiconductor device in which on-resistance is largely reduced based on a new principle of operation. In the semiconductor device, if an embedded electrode is at negative potential, a depletion layer is formed from a trench to a neighboring trench so that a channel is turned off. If the embedded electrode is at a positive potential, the depletion layer is not formed in every region between the neighboring trenches so that the channel is turned on.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: July 1, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 8748268
    Abstract: Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: June 10, 2014
    Assignee: Alpha to Omega Semiconductor, Inc.
    Inventors: Ji Pan, Daniel Ng, Sung-Shan Tai, Anup Bhalla
  • Patent number: 8748267
    Abstract: The present invention belongs to the technical field of semiconductor device manufacturing and specifically relates to a method for manufacturing a tunneling field effect transistor with a U-shaped channel. The U-shaped channel can effectively extend the transistor channel length, restrain the generation of leakage current in the transistor, and decrease the chip power consumption. The method for manufacturing a tunneling field effect transistor with a U-shaped channel put forward in the present invention is capable of realizing an extremely narrow U-shaped channel, overcoming the alignment deviation introduced by photoetching, and improving the chip integration degree.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: June 10, 2014
    Assignee: FUDAN University
    Inventors: Pengfei Wang, Xi Lin, Wei Liu, Qingqing Sun, Wei Zhang
  • Patent number: 8748261
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer, a base region of a second-conductivity-type formed in an upper portion of the first-conductivity-type semiconductor layer, first though third trenches penetrating through the base region and reaching to the first-conductivity-type semiconductor layer, the first through third trenches being linked to one another, a source interconnect layer buried in the first through third trenches, the source interconnect layer including a protruding portion, a gate electrode buried in the first trench and the third trench, and formed over the source interconnect layer, a source metal contacting the protruding portion of the source interconnect layer, and a gate metal contacting the gate electrode in the third trench. A contact face between the source metal and the protruding portion at the second trench is formed higher than a contact face between the gate metal and the gate electrode at the third trench.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Kei Takehara
  • Patent number: 8680610
    Abstract: A trench MOSFET comprising source regions having a doping profile of a Gaussian-distribution along the top surface of epitaxial layer and floating dummy cells formed between edge trench and active area is disclosed. A SBR of n region existing at cell corners renders the parasitic bipolar transistor difficult to turn on, and the floating dummy cells having no parasitic bipolar transistor act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: March 25, 2014
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8658498
    Abstract: A method for fabricating vertical surround gate structures in semiconductor device arrays. The method includes forming pillars separated by vertical and horizontal trenches on a substrate. Forming a gate layer over the pillars and trenches such that the gate layer forms gate trenches in the horizontal trenches. The method includes forming fillers within the gate trenches, and planarizing the gate layer and fillers. The method also includes successively etching a first portion of the gate layer, removing the fillers, and etching a second portion of the gate layer.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chung H. Lam, Jing Li
  • Patent number: 8652901
    Abstract: A method for fabricating vertical surround gate structures in semiconductor device arrays. The method includes forming pillars separated by vertical and horizontal trenches on a substrate. Forming a gate layer over the pillars and trenches such that the gate layer forms gate trenches in the horizontal trenches. The method includes forming fillers within the gate trenches, and planarizing the gate layer and fillers. The method also includes successively etching a first portion of the gate layer, removing the fillers, and etching a second portion of the gate layer.
    Type: Grant
    Filed: March 3, 2013
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chung H. Lam, Jing Li
  • Patent number: 8633073
    Abstract: A method of forming a semiconductor device includes the following processes. A first groove is formed in a semiconductor substrate. A first conductive film is formed in the first groove and over the semiconductor substrate. The first conductive film is planarized over the semiconductor substrate. The planarized first conductive film is selectively etched to have the planarized first conductive film remain in a lower portion of the first groove.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: January 21, 2014
    Inventor: Keisuke Otsuka
  • Patent number: 8610205
    Abstract: In one general aspect, an apparatus can include a shield dielectric disposed within a trench aligned along an axis within an epitaxial layer of a semiconductor, and a shield electrode disposed within the shield dielectric and aligned along the axis. The apparatus can include a first inter-poly dielectric having a portion intersecting a plane orthogonal to the axis where the plane intersects the shield electrode, and a second inter-poly dielectric having a portion intersecting the plane and disposed between the first inter-poly dielectric and the shield electrode. The apparatus can also include a gate dielectric having a portion disposed on the first inter-poly dielectric.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: December 17, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Dean E. Probst
  • Patent number: 8581346
    Abstract: A semiconductor memory device includes a first conductive line, a second conductive line crossing over the first conductive line, a resistance variation part disposed at a position in which the second conductive line intersects with the first conductive line and electrically connected to the first conductive line and the second conductive line and a mechanical switch disposed between the resistance variation part and the second conductive line. The mechanical switch includes a nanotube.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: HongSik Yoon, Jinshi Zhao, Ingyu Baek, Hyunjun Sim, Minyoung Park
  • Patent number: 8569134
    Abstract: A closed cell trench MOSFET structure having a drain region of a first conductivity type, a body of a second conductivity type, a trenched gate, and a plurality of source regions of the first conductivity type is provided. The body is located on the drain region. The trenched gate is located in the body and has at least two stripe portions and a cross portion. A bottom of the stripe portions is located in the drain region and a bottom of the cross portion is in the body. The source regions are located in the body and at least adjacent to the stripe region of the trenched gate.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: October 29, 2013
    Assignee: Great Power Semiconductor Corp.
    Inventor: Hsiu Wen Hsu
  • Patent number: 8552535
    Abstract: A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: October 8, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Peter A. Burke, Brian Pratt, Prasad Venkatraman
  • Patent number: 8541826
    Abstract: A memory array structure and a method for forming the same are provided. The memory array structure comprises: a substrate; a plurality of memory cells, each memory cell including a vertical transistor, of which a gate structure is formed in a first trench extending in a first direction; a plurality of word lines in the first direction, each word line formed in the first trench; a plurality of bit lines in a second direction, each bit line formed in lower sides of a semiconductor pillars; a plurality of body lines in the first direction, each body line having a first portion formed on the gate electrodes and a second portion covering a part of a top surface of semiconductor pillar for providing a substrate contact to vertical channel regions; and a plurality of data storage device contacts.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: September 24, 2013
    Assignee: Tsinghua University
    Inventors: Liyang Pan, Haozhi Ma
  • Patent number: 8524559
    Abstract: The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: September 3, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Main-Gwo Chen, Chia-Hao Chang, Chia-Wei Chen
  • Patent number: 8518812
    Abstract: Some embodiments include methods of forming contacts. A row of projections may be formed over a semiconductor substrate. The projections may include a plurality of repeating components of an array, and a terminal projection. The terminal projection may have a sacrificial material spaced from semiconductor material of the substrate by a dielectric structure. An electrically conductive line may be formed along the row. The line may wrap around an end of the terminal projection and bifurcate into two branches that are along opposing sides of the repeating components. The individual branches may have regions spaced from the sacrificial material by segments of gate dielectric. The sacrificial material may be removed, together with the segments of gate dielectric, to form a contact opening. An electrically conductive contact may be formed within the contact opening and directly against the regions of the branches.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Marcello Mariani, Micaela Gabriella Tomasini
  • Patent number: 8497551
    Abstract: The process methods and structures mentioned above for creating a trench MOSFET enables self-aligned contacts to be formed to allow decreasing pitch size for trench MOSFET. The self-aligned contacts are formed by etching exposed silicon areas without using lithographical mask and alignment. As a result, the allowance for alignment can be saved and the pitch size can be decreased.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: July 30, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Alex Kalnitsky, Hsiao-Chin Tuan, Kuo-Ming Wu, Wei Tsung Huang
  • Patent number: 8497173
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: July 30, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Woo Young Chung
  • Patent number: 8476701
    Abstract: A semiconductor device includes a transistor that has a trench formed in an element forming region of a substrate, a gate insulating film formed on side faces and a bottom face of the trench, a gate electrode formed on the gate insulating film so as to bury the trench, a source region formed on one side in the gate longitude direction, which is formed on the surface of the substrate, and a drain region formed on the other side in the gate longitude direction. Here, the gate electrode is formed so as to be exposed also on the substrate outside the trench, and the gate electrode is disposed so as to cover upper portions of both ends of the trench and so as to form at least one concave portion having a depth reaching the substrate in a center portion.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: July 2, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takehiro Ueda, Hiroshi Kawaguchi
  • Patent number: 8431457
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: April 30, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hong Chang, Yi Su, Wenjun Li, Limin Weng, Gary Chen, Jongoh Kim, John Chen
  • Patent number: 8426910
    Abstract: A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: April 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Patent number: 8405089
    Abstract: To provide an active region having first and second diffusion layers positioned at both sides of a gate trench and a third diffusion layer formed on a bottom surface of the gate trench, first and second memory elements connected to the first and second diffusion layers, respectively, a bit line connected to the third diffusion layer, a first gate electrode that covers a first side surface of the gate trench via a gate dielectric film and forms a channel between the first diffusion layer and the third diffusion layer, and a second gate electrode that covers a second side surface of the gate trench via a gate dielectric film and forms a channel between the second diffusion layer and the third diffusion layer. According to the present invention, because separate transistors are formed on both side surfaces of a gate trench, two times of conventional integration can be achieved.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: March 26, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroyuki Uchiyama
  • Patent number: 8372710
    Abstract: A semiconductor structure having U-shaped transistors includes source/drain regions at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. Methods of forming semiconductor structures are also disclosed.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: February 12, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8314471
    Abstract: In one embodiment, the present invention includes a semiconductor power device. The semiconductor power device comprises a trenched gate and a trenched field region. The trenched gate is disposed vertically within a trench in a semiconductor substrate. The trenched field region is disposed vertically within the trench and below the trenched gate. A lower portion of the trenched field region tapers to disperse an electric field.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: November 20, 2012
    Assignee: Diodes Incorporated
    Inventors: Chiao-Shun Chuang, Tony Huang
  • Patent number: 8298892
    Abstract: A fabricating method of an insulator for replacing a gate structure in a substrate by the insulator. The fabricating method includes the step of providing a substrate including a first buried gate structure. The first buried structure includes a first trench embedded in the substrate and a first gate filling in the first trench. The first trench has a first depth. Then, the first gate of the first buried structure is removed. Later, the substrate under the first trench is etched to elongate the depth of the first trench from the first depth to a third depth. Finally, an insulating material fills in the first trench with the third depth to form an insulator of the present invention.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 30, 2012
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung-Han Lee, Chung-Lin Huang, Ron Fu Chu
  • Patent number: 8283714
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: October 9, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Patent number: 8258065
    Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: September 4, 2012
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Bomy Chen, Long Ching Wang, Sychyi Fang
  • Patent number: 8193578
    Abstract: A power supply circuit includes first and second switching MOSFETS. A semiconductor device, including the second switching MOSFET, has a plurality of transistor cell regions disposed in a semiconductor substrate. A source electrode of the second MOSFET is disposed over a main surface of the semiconductor substrate and is in contact with a top surface of a source region in each of the plurality of transistor cell regions. A drain electrode of the second MOSFET is disposed over a back surface of the semiconductor substrate and is electrically connected to the semiconductor substrate. A Schottky cell region is disposed between the plurality of transistor cell regions in the semiconductor substrate. The source electrode is in contact with a part of the main surface of the semiconductor so as to form a Schottky junction in the Schottky cell region.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: June 5, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Patent number: 8153489
    Abstract: A method for fabricating a semiconductor device, including forming a trench by etching a semiconductor substrate, forming a gate insulation layer over a surface of the trench, forming a gate conductive layer over the gate insulation layer, performing a first recess process by etching the gate conductive layer, forming a protection pattern over the gate insulation layer, and performing a second recess process by etching the gate conductive layer.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: April 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Pil-Geun Song
  • Patent number: 8148796
    Abstract: Disclosed are a solar cell and a manufacturing method thereof. The solar cell in accordance with an embodiment of the present invention includes: a substrate having a plurality of holes formed on one surface thereof; a metal layer formed on an inner wall of the hole and on one surface of the substrate; a p-type semiconductor coated on the metal layer; an n-type semiconductor formed inside the hole and on one surface of the substrate; a transparent conductive oxide formed on the n-type semiconductor; and an electrode terminal formed on the p-type semiconductor and on the transparent conductive oxide.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: April 3, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ro-Woon Lee, Jae-Woo Joung, Shang-Hoon Seo, Tae-Gu Kim
  • Patent number: 8143125
    Abstract: A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric is formed extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches. A gate electrode is formed in each trench isolated from the semiconductor region by the gate dielectric. Well regions of a second conductivity type are formed in the semiconductor region. Source regions of the first conductivity type are formed in upper portions of the well regions. After forming the source regions, a salicide layer is formed over the gate electrode in each trench abutting portions of the gate dielectric. The gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: March 27, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Robert J. Purtell, James J. Murphy
  • Patent number: 8143670
    Abstract: Provided is a self aligned filed effect transistor structure. The self aligned field effect transistor structure includes: an active region on a substrate; a U-shaped gate insulation pattern on the active region; and a gate electrode self-aligned by the gate insulation pattern and disposed in an inner space of the gate insulation pattern.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: March 27, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Lee-Mi Do, Kyu-Ha Baek
  • Patent number: 8143124
    Abstract: A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom includes forming a drift region, a well region extending above the drift region, an active trench extending through the well region and into the drift region, a charge control trench extending deeper into the drift region than the active trench, an oxide film that fills the active trench, the charge control trench and covers a top surface of the substrate, an electrode in the active trench, and source regions. The method also includes etching the oxide film off the top surface of the substrate and inside the active trench to leave a substantially flat layer of thick oxide having a target thickness at the bottom of the active trench.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: March 27, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ashok Challa, Alan Elbanhawy, Dean E. Probst, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Becky Losee, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher B. Kocon, Debra S. Woolsey