Making Bit Line Contact (epo) Patents (Class 257/E21.658)
-
Patent number: 10461170Abstract: A method includes providing a semiconductor structure that includes an epitaxial layer and a cap layer above the epitaxial layer, filling a trench above the cap layer with a sacrificial layer, and removing the sacrificial layer. As such, the cap layer is protected by the sacrificial layer during an etching process and the epitaxial layer is protected by the cap layer during another etching process.Type: GrantFiled: May 4, 2016Date of Patent: October 29, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ching-Feng Fu, Yu-Chan Yen, Chih-Hsin Ko, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
-
Patent number: 8969936Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate including first and second junction regions, a word line buried in the substrate, a bit line provided over the word line to cross the word line, a first contact provided between the substrate and the bit line and electrically connected to the first junction region, and a second contact provided between the bit lines and electrically connected to the second junction region. An overlapping area of a lower portion of the second contact may be greater than an overlapping area of an upper portion of the second contact with respect to the second junction region.Type: GrantFiled: December 31, 2012Date of Patent: March 3, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Wonchul Lee, Eun A Kim, Ja Young Lee
-
Patent number: 8957467Abstract: A semiconductor device includes: a transistor including source and drain diffusion-layers, a gate insulating film and a gate electrode; first and second plugs formed in a first interlayer-insulating film and connected to the source and drain diffusion-layers, respectively; a third plug extending through a second interlayer-insulating film and connected to the first plug; a first interconnection-wire formed on the second interlayer-insulating film and connected to the third plug; a second interconnection-wire formed on a third interlayer-insulating film and intersecting the first interconnection-wire; a fourth interlayer-insulating film; a hole extending through the fourth, third and second interlayer-insulating films, the hole being formed such that a side surface of the second interconnection-wire is exposed; and a fourth plug filling the hole via an intervening dielectric film and connected to the second plug, wherein a capacitor is formed using the fourth plug, the second interconnection-wire and the dieleType: GrantFiled: August 3, 2011Date of Patent: February 17, 2015Assignee: PS4 Luxco S.A.R.L.Inventor: Hiroyuki Uchiyama
-
Patent number: 8921906Abstract: Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.Type: GrantFiled: October 27, 2011Date of Patent: December 30, 2014Assignee: Micron Technology, Inc.Inventors: Byron Neville Burgess, John K. Zahurak
-
Patent number: 8865588Abstract: A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.Type: GrantFiled: December 24, 2013Date of Patent: October 21, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Takeshi Kagawa
-
Patent number: 8815735Abstract: A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer.Type: GrantFiled: May 3, 2012Date of Patent: August 26, 2014Assignee: Nanya Technology CorporationInventors: Yi Jung Chen, Kuo Hui Su, Chiang Hung Lin
-
Patent number: 8778763Abstract: A method for forming a memory cell transistor is disclosed which includes providing a substrate, forming a trench structure in the substrate, depositing a conductive substance on the surface of the substrate to form a conductive member inside the trench structure, forming one or more dielectric layers on the surface of the substrate, forming one or more first conductive layers on top of the dielectric layers, and etching the first conductive layers and the dielectric layers to form a hole structure extending through the first conductive and the dielectric layers, reaching to the substrate surface. One or more second conductive layers may be formed on top of the first conductive layers, with the second conductive layer material filling the hole structure.Type: GrantFiled: December 8, 2011Date of Patent: July 15, 2014Assignee: Hermes Microvision, Inc.Inventor: Hong Xiao
-
Patent number: 8778757Abstract: In methods of manufacturing a DRAM device, a buried-type gate is formed in a substrate. A capping insulating layer pattern is formed on the buried-type gate. A conductive layer pattern filling up a gap between portions of the capping insulating layer pattern, and an insulating interlayer covering the conductive layer pattern and the capping insulating layer pattern are formed. The insulating interlayer, the conductive layer pattern, the capping insulating layer pattern and an upper portion of the substrate are etched to form an opening, and a first pad electrode making contact with a first pad region. A spacer is formed on a sidewall of the opening corresponding to a second pad region. A second pad electrode is formed in the opening. A bit line electrically connected with the second pad electrode and a capacitor electrically connected with the first pad electrode are formed.Type: GrantFiled: July 3, 2012Date of Patent: July 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Chul Park, Sang-sup Jeong
-
Patent number: 8742548Abstract: A method for fabricating a semiconductor device includes forming a plurality of first trenches by etching a substrate, forming first spacers covering both sidewalls of each of the first trenches, forming a plurality of second trenches by etching a bottom of each of the first trenches, forming second spacers covering both sidewalls of each of the second trenches, forming a plurality of third trenches by etching a bottom of each of the second trenches, forming an insulation layer covering exposed surfaces of the plurality of the substrate, and forming a contact which exposes one sidewall of each of the second trenches by selectively removing the second spacers.Type: GrantFiled: December 29, 2010Date of Patent: June 3, 2014Assignee: Hynix Semiconductor Inc.Inventor: You-Song Kim
-
Patent number: 8728927Abstract: Embodiments of the invention include methods of forming borderless contacts for semiconductor transistors. Embodiments may include providing a transistor structure including a gate, a spacer on a sidewall of the gate, a hard cap above the gate, a source/drain region adjacent to the spacer, and an interlevel dielectric layer around the gate, forming a contact hole above the source/drain region, forming a protective layer on portions of the hard cap and of the spacer exposed by the contact hole; deepening the contact hole by etching the interlevel dielectric layer while the spacer and the hard cap are protected by the protective layer, so that at least a portion of the source/drain region is exposed by the deepening of the contact hole; removing the protective layer; and forming a metal contact in the contact hole.Type: GrantFiled: December 10, 2012Date of Patent: May 20, 2014Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan, Charan V. Surisetty, Thomas N. Adam
-
Patent number: 8704284Abstract: Provided is a semiconductor device having bit line expanding islands, which are formed underneath bit lines to reliably expand and connect the bit lines.Type: GrantFiled: February 25, 2010Date of Patent: April 22, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Kye-hee Yeom
-
Patent number: 8691656Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.Type: GrantFiled: September 7, 2011Date of Patent: April 8, 2014Assignee: Micron Technology, Inc.Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
-
Patent number: 8642464Abstract: A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.Type: GrantFiled: July 31, 2012Date of Patent: February 4, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Takeshi Kagawa
-
Patent number: 8546220Abstract: A method for fabricating buried bit lines comprises steps of: defining a plurality of parallel masked regions and a plurality of first etched regions each forming between any two neighboring masked regions on a surface of a substrate, and wherein the masked region is wider than the first etched region; etching the first etched regions to form a plurality of first trenches and a plurality of first pillars; forming two bit lines respectively on two sidewalls of each first trench; etching the first pillars to form a plurality of second pillars corresponding to the bit lines. The present invention uses a two-stage etching process to prevent pillars from bending or collapsing due to high aspect ratio. Moreover, the present invention has a simple process and is able to reduce cost and decrease cell size.Type: GrantFiled: July 18, 2012Date of Patent: October 1, 2013Assignee: Rexchip Electronics CorporationInventors: Isao Tanaka, Chien-hua Tsai
-
Patent number: 8518788Abstract: A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, and a second material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials. Openings are anisotropically etched to extend through the outer insulative retaining material and the second material. After the anisotropic etching, remaining of the second material is isotropically etched through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials.Type: GrantFiled: August 11, 2010Date of Patent: August 27, 2013Assignee: Micron Technology, Inc.Inventor: Che-Chi Lee
-
Patent number: 8507344Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The method for forming the semiconductor device includes forming one or more buried gates in a semiconductor substrate, forming a landing plug between the buried gates, forming a bit line region exposing the landing plug over the semiconductor substrate, forming a glue layer in the bit line region, forming a bit line material in the bit line region, and removing the glue layer formed at inner sidewalls of the bit line region, and burying an insulation material in a part where the glue layer is removed. A titanium nitride (TiN) film formed at sidewalls of the damascene bit line is removed, so that resistance of the bit line is maintained and parasitic capacitance of the bit line is reduced, resulting in the improvement of device characteristics.Type: GrantFiled: December 27, 2010Date of Patent: August 13, 2013Assignee: Hynix Semiconductor Inc.Inventor: Chan Woo Kim
-
Patent number: 8507971Abstract: The present invention provides an apparatus and method for a non-volatile memory comprising at least one array of memory cells with shallow trench isolation (STI) regions between bit lines for increased process margins. Specifically, in one embodiment, each of the memory cells in the array of memory cells includes a source, a control gate, and a drain, and is capable of storing at least one bit. The array of memory cells further includes word lines that are coupled to control gates of memory cells. The word lines are arranged in rows in the array. In addition, the array comprises bit lines coupled to source and drains of memory cells. The bit lines are arranged in columns in the array. Also, the array comprises at least one row of bit line contacts for providing electrical conductivity to the bit lines. Further, the array comprises shallow trench isolation (STI) regions separating each of the bit lines along the row of bit line contacts.Type: GrantFiled: August 6, 2008Date of Patent: August 13, 2013Assignee: Spansion LLCInventor: Satoshi Torii
-
Patent number: 8507375Abstract: An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.Type: GrantFiled: February 2, 2012Date of Patent: August 13, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: André P. Labonté, Richard S. Wise
-
Patent number: 8476154Abstract: The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability.Type: GrantFiled: January 4, 2011Date of Patent: July 2, 2013Assignee: Fudan UniversityInventors: Dongping Wu, Shi-Li Zhang
-
Patent number: 8435876Abstract: A method of manufacturing a semiconductor device includes forming a lower film including a cell region and a peripheral circuit region, forming a first sacrificial film on the lower film, the first sacrificial film having trenches in the cell region, forming a second sacrificial pattern on the first sacrificial film, the second sacrificial pattern having line-shaped patterns spaced apart from each other and crossing the trenches in the cell region, and the second sacrificial pattern covering a top surface of the first sacrificial film in the peripheral circuit region, and patterning the first sacrificial film to form upper holes in portions of the trenches exposed by the second sacrificial pattern.Type: GrantFiled: November 2, 2011Date of Patent: May 7, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jongchul Park, Jong-Kyu Kim, Ki-jin Park, Sangsup Jeong
-
Patent number: 8394680Abstract: In a layout for a semiconductor device, each active region comprises a first active region, a right active region on the right side of the first active region, a left active region on the left side of the first active region, an upper active region on the upper side of the first active region and a lower active region on the lower side of the first active region, wherein the first active region, the right active region, the left active region, the upper active region and the lower active region each have an inclined portion having a bit-line contact region; and first and second portions having a storage node contact region, first and second ends formed on left and right ends of the inclined portion at a predetermined tilt angle with respect to the inclined portion, the active region being intersected by two word lines and one bit line.Type: GrantFiled: December 30, 2009Date of Patent: March 12, 2013Assignee: Hynix Semiconductor IncInventor: Ho Hyuk Lee
-
Patent number: 8349664Abstract: In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy, HfxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.Type: GrantFiled: August 12, 2010Date of Patent: January 8, 2013Assignee: SanDisk 3D LLCInventors: Scott Brad Herner, Christopher J. Petti, Tanmay Kumar
-
Patent number: 8319264Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line contact hole obtained by etching the semiconductor substrate; a bit line contact plug having a smaller width than that of the bit line contact hole; and a bit line connected to the upper portion of the bit line contact plug, thereby preventing a short of the bit line contact plug and the storage node contact plug to improve characteristics of the semiconductor device.Type: GrantFiled: December 28, 2010Date of Patent: November 27, 2012Assignee: SK Hynix Inc.Inventor: Seung Bum Kim
-
Patent number: 8216897Abstract: A method for manufacturing a semiconductor device is disclosed. A method for manufacturing a semiconductor device includes forming a device isolation structure for defining an active region, forming a buried word line traversing the active region, forming one or more insulation film patterns over the buried word line, forming a line pattern including a first conductive material at a position between the insulation film patterns, and forming a plurality of storage node contacts (SNCs) by isolating the line pattern. As a result, when forming a bit line contact and a storage node contact, a fabrication margin is increased.Type: GrantFiled: December 29, 2010Date of Patent: July 10, 2012Assignee: Hynix Semiconductor Inc.Inventor: Do Hyung Kim
-
Patent number: 8198661Abstract: A semiconductor device include a semiconductor substrate comprising a substrate body, a base over the substrate body and a pillar over a first region of the base; a buried line adjacent to a side surface of the base; a first diffusion layer over a second region of the base; a second diffusion layer over the pillar, the second diffusion layer being higher in level than the first diffusion layer; and a third diffusion layer disposed between the buried line and the semiconductor substrate. The third diffusion layer is different in level from the first diffusion layer. The top level of the third diffusion layer is lower than the top level of the first diffusion layer.Type: GrantFiled: December 14, 2009Date of Patent: June 12, 2012Assignee: Elpida Memory, Inc.Inventor: Hiroyuki Fujimoto
-
Patent number: 8148260Abstract: Provided may be a semiconductor memory device and a method of forming the semiconductor memory device. The memory device of example embodiments may include a bit line structure including a bit line on a semiconductor substrate, and a buried contact plug structure including a buried contact pad and a buried contact plug that extends in a lower portion of the bit line from one side of the bit line and connected to the buried contact pad. A width of the buried contact plug near a top surface of the buried contact pad may be greater than a width of the buried contact plug adjacent to the bit line.Type: GrantFiled: September 26, 2008Date of Patent: April 3, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Kyoung-Sub Shin
-
Patent number: 8138538Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.Type: GrantFiled: October 10, 2008Date of Patent: March 20, 2012Assignee: Qimonda AGInventors: Hans-Peter Moll, Gouri Sankar Kar, Martin Popp, Lars Heineck, Peter Lahnor, Arnd Scholz, Stefan Jakschik, Wolfgang Roesner, Gerhard Enders, Werner Graf, Peter Baars, Klaus Muemmler, Bernd Hintze, Andrei Josiek
-
Patent number: 8119512Abstract: A method for fabricating a semiconductor device includes forming an interlayer dielectric layer over a substrate; forming a dual storage node contact plug to be buried in the interlayer dielectric layer, forming a first damascene pattern to isolate the dual storage node contact plug, forming a protective layer pattern inside the first damascene pattern, etching the interlayer dielectric layer to form a second damascene pattern to be coupled to the first damascene pattern, and forming bit lines inside the first and second damascene patterns.Type: GrantFiled: December 29, 2010Date of Patent: February 21, 2012Assignee: Hynix Semiconductor Inc.Inventor: Chang-Goo Lee
-
Patent number: 8093662Abstract: Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi+1, . . . , AAn, which extend on a memory cell array along the column length; a plurality of word line patterns WL1, WL2, . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG1, SG2, . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.Type: GrantFiled: August 16, 2010Date of Patent: January 10, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kikuko Sugimae, Satoshi Tanaka, Koji Hashimoto, Masayuki Ichige
-
Patent number: 8084801Abstract: In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.Type: GrantFiled: December 15, 2009Date of Patent: December 27, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-Yun Baek, Yong-Sun Ko, Hak Kim, Yong-Kug Bae
-
Patent number: 8053360Abstract: To prevent two contacts that have different heights, share at least one interlayer insulating film and are disposed close to each other from being short-circuited to each other due to misalignment thereof, a semiconductor device according to the invention has a recess in an interlayer insulating film in which a first contact hiving a lower height, the recess being formed by the upper surface of the first contact, and a silicon nitride sidewall is formed in the recess to extend from the upper surface of the first contact and along the side surface of the recess.Type: GrantFiled: January 21, 2009Date of Patent: November 8, 2011Assignee: Elpida Memory, Inc.Inventor: Kazuo Yamazaki
-
Patent number: 8035152Abstract: A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.Type: GrantFiled: June 22, 2009Date of Patent: October 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-hoon Jang, Young-bae Yoon, Hee-soo Kang, Young-seop Rah, Jeong-dong Choe
-
Patent number: 8034684Abstract: Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.Type: GrantFiled: April 29, 2010Date of Patent: October 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Joon-Soo Park
-
Patent number: 8030168Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.Type: GrantFiled: April 6, 2009Date of Patent: October 4, 2011Assignee: Micron Technology, Inc.Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
-
Patent number: 8030158Abstract: Disclosed is a method for fabricating a contact in a semiconductor device, including: obtaining a pattern layout including bit lines arranged across a cell matrix region of a semiconductor substrate, cell storage node contacts arranged to pass through a portion of a first interlayer insulation layer between the bit lines, and dummy storage node contacts additionally arranged in an end of the arrangement of the cell storage node contacts; and forming the cell storage node contacts and the dummy storage node contacts using the pattern layout.Type: GrantFiled: November 23, 2009Date of Patent: October 4, 2011Assignee: Hynix SemiconductorInventors: Chun Soo Kang, Jin Hyuck Jeon
-
Patent number: 8013385Abstract: A semiconductor device of the present invention has a first contact and a second contact which are located over a device isolation film so as to be opposed with each other, and have a length in the horizontal direction larger than the height; a first electro-conductive pattern located on the first contact and is formed in at least a single interconnect layer; a second electro-conductive pattern located on the second contact so as to be opposed with the first electro-conductive pattern; and an interconnect formed in an upper interconnect layer which is located above the first electro-conductive pattern and the second electro-conductive pattern, so as to be located in a region above the first electro-conductive pattern and the second electro-conductive pattern.Type: GrantFiled: December 7, 2009Date of Patent: September 6, 2011Assignee: Renesas Electronics CorporationInventors: Masayuki Furumiya, Yasutaka Nakashiba
-
Patent number: 8012810Abstract: A method of manufacturing low parasitic capacitance bit line for stack DRAM, comprising the following steps: offering a semi-conductor base, which semi-conductor having already included an oxide, plural word line stacks, plural bit line stacks and plural polysilicons; applying a multi layer resist coat; removing the multi layer resist coat and further removing parts of the oxide located on the polysilicon to form contact holes exposing the plural polysilicons; depositing an oxide layer; etching the oxide layer to form the oxide layer spacer; depositing a polysilicon layer; performing lithography and etching on the polysilicon layer thereby allowing the rest of the polysilicon layer that is column-shaped to form capacitor contacts; and using another oxide to fill into the space among the word line stacks and the capacitor contacts.Type: GrantFiled: February 11, 2010Date of Patent: September 6, 2011Assignee: Inotera Memories, Inc.Inventors: Hsiao-Lei Wang, Chih-Hung Liao
-
Patent number: 7989335Abstract: In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A preliminary hard mask pattern having first openings is formed by patterning the hard mask layer. A hard mask pattern having the first openings and second openings is formed by patterning the preliminary hard mask pattern. Width control spacers are formed on sidewalls of the first and the second openings. An etching mask pattern is formed by etching the organic layer using the hard mask pattern as an etching mask. The insulation layer pattern having third openings is formed by etching the insulation layer using the etching mask pattern as an etching mask.Type: GrantFiled: March 25, 2010Date of Patent: August 2, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-Woo Lee, Hong-Jae Shin
-
Patent number: 7951675Abstract: Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and second spacers between the bitlines, the memory device can improve the electrical isolation between the bitlines, thereby preventing and/or mitigating bitline-to-bitline current leakage and increasing BVdss.Type: GrantFiled: December 17, 2007Date of Patent: May 31, 2011Assignee: Spansion LLCInventors: Lei Xue, Aimin Xing, Chih-Yuh Yang, Angela Hui, Chungho Lee
-
Patent number: 7939411Abstract: A method for fabricating a semiconductor device includes forming buried bit lines in a first substrate; forming a trench that separate the buried bit lines from each other; forming an interlayer insulation layer to gap-fill the trench; forming a second substrate over the first substrate gap-filled with the interlayer insulation layer; forming a protective pattern over the second substrate; forming a plurality of active pillars by etching the second substrate using the protective pattern as an etch barrier; and forming vertical gates surrounding sidewalls of the active pillars.Type: GrantFiled: June 27, 2009Date of Patent: May 10, 2011Assignee: Hynix Semiconductor Inc.Inventor: Young-Kyun Jung
-
Patent number: 7932168Abstract: A method of a fabricating a bitline in a semiconductor device, comprising: forming an interlayer insulation layer that defines a bitline contact hole on a semiconductor substrate; forming a contact layer to fill the bitline contact hole; forming a bitline contact by planarizing the contact layer; forming a bitline stack aligned with the bitline contact; forming a high aspect ratio process (HARP) layer that extends along the bitline stack and the interlayer insulation layer while covering a seam exposed in a side portion of the bitline stack by excessive planarization during formation of the bitline contact; and forming an interlayer gap-filling insulation layer on the HARP layer that gap-fills the entire bitline stack.Type: GrantFiled: December 16, 2009Date of Patent: April 26, 2011Assignee: Hynix Semiconductor Inc.Inventor: Byung Soo Eun
-
Patent number: 7927945Abstract: Provided is a method for manufacturing a semiconductor device having a 4F2 transistor. In the method, a gate stack is formed on a semiconductor substrate. A first interlayer dielectric including a contact hole which includes a first region and second regions Spacer layers are formed on both sides of the gate stack and a portion of the second region. Landing plugs are formed on the contact hole, a portion of the semiconductor substrate exposed by a thickness of the spacer layer, and a lateral side of the trench. A second interlayer dielectric is formed to separate the landing plug. The bit line contact plug is connected to a first portion of the landing plug that extends to the lateral side of the trench. The bit line stack is connected to the bit line contact plug. The storage node contact plug is connected to the first portion and a second portion of the landing plug located at a corresponding position in a diagonal direction.Type: GrantFiled: May 8, 2008Date of Patent: April 19, 2011Assignee: Hynix Semiconductor Inc.Inventor: Jin Yul Lee
-
Patent number: 7923371Abstract: A semiconductor device has a semiconductor substrate in which a plurality of device regions and a plurality of device isolation regions are alternately formed to extend in a first direction; and a plurality of contact plugs formed on the semiconductor substrate, connected to the device regions and arranged on the semiconductor substrate in a zigzag pattern in a second direction perpendicular to the first direction, wherein the contact plugs have a rectangular cross section.Type: GrantFiled: March 17, 2009Date of Patent: April 12, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Masahito Shinohe
-
Patent number: 7867842Abstract: A method for forming alloy deposits at selected areas on a receiving substrate includes the steps of: providing an alloy carrier including at least a first decal including a first plurality of openings and a second decal including a second plurality of openings, the first and second decals being arranged such that each of the first plurality of openings is in alignment with a corresponding one of the second plurality of openings; filling the first and second plurality of openings with molten alloy; cooling the molten alloy to thereby form at least first and second plugs, the first plug having a first surface and a second surface substantially parallel to one another, the second plug having a third surface and a fourth surface substantially parallel to one another; removing at least one of the first and second decals to at least partially expose the first and second plugs; aligning the alloy carrier with the receiving substrate so that the first and second plugs correspond to the selected areas on the receivinType: GrantFiled: July 29, 2008Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Peter Alfred Gruber, Paul Alfred Lauro, Jae-Woong Nah
-
Patent number: 7858477Abstract: A method for manufacturing a semiconductor device includes forming a bulb-type trench separated from a surrounding gate and forming a buried bit line in the bulb-type trench, thereby preventing electric short of a word line and the buried bit line. A semiconductor device includes a vertical pillar formed over a semiconductor substrate, a surrounding gate formed outside the vertical pillar, and a buried bit line separated from the surrounding gate.Type: GrantFiled: May 8, 2008Date of Patent: December 28, 2010Assignee: Hynix Semiconductor Inc.Inventor: Han Nae Kim
-
Patent number: 7812399Abstract: The present invention provides a semiconductor device which includes a gate electrode shaped in the form of an approximately quadrangular prism, including a laminated body of a gate oxide layer, a gate polysilicon layer and a gate silicon nitride layer provided in a first conduction type substrate, a second conduction type implantation region provided in a region outside the gate electrode, a sidewall that exposes a top face of the gate electrode and is formed by laminating a sidewall mask oxide layer covering side surfaces, an electron storage nitride layer and a sidewall silicon oxide layer, and a source/drain diffusion layer provided in the first conduction type substrate exposed from the gate electrode and the sidewall.Type: GrantFiled: March 29, 2007Date of Patent: October 12, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Takashi Yuda
-
Patent number: 7807513Abstract: Methods for manufacturing a semiconductor device are provided that reduces the thickness of an oxide layer formed on a polysilicon layer for bit line contacts. A reduced thickness oxide layer can prevent short circuits between adjoining bit lines. A reduced thickness oxide layer can also eliminate the need for overetching in a subsequent etching process, thereby preventing loss of an isolation layer in a peripheral region.Type: GrantFiled: December 28, 2009Date of Patent: October 5, 2010Assignee: Hynix Semiconductor Inc.Inventors: Hyung Kyun Kim, Yong Soo Joung
-
Patent number: 7776659Abstract: A method of manufacturing a semiconductor device having a first memory cell array region and a second memory cell array region, the method includes forming an active region on a surface layer of a semiconductor substrate, forming a first word line extending in a first direction on the gate insulating film in the first memory cell array region, and forming a second word line extending in a second direction crossing the first direction on the gate insulating film in the second memory cell array region, wherein the ion implantation into the active region is performed from a direction that is inclined from a direction vertical to the surface of the semiconductor substrate and is oblique with respect to both the first direction and the second direction.Type: GrantFiled: November 30, 2009Date of Patent: August 17, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Hiroyuki Ogawa, Hideyuki Kojima
-
Patent number: 7763542Abstract: A semiconductor memory device includes a semiconductor substrate. An inter-layer dielectric is disposed on the semiconductor substrate. A bit line is disposed on the inter-layer dielectric. A bit line spacer is fabricated of a nitride layer containing boron and/or carbon and covers sidewalls of the bit line. A method of fabricating the semiconductor memory device is also provided.Type: GrantFiled: August 16, 2006Date of Patent: July 27, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Gyun Kim, Ki-Sun Kim, Jae-Young Ahn
-
Patent number: 7749834Abstract: A method includes forming a lower dielectric layer on a semiconductor substrate, forming a bit line landing pad and a storage landing pad that penetrate the lower dielectric layer, covering the lower dielectric layer, the bit line landing pad, and the storage landing pad with an intermediate dielectric layer, forming an upper dielectric layer on the intermediate dielectric layer, partially removing the upper dielectric layer and the intermediate dielectric layer to form a contact opening that exposes the storage landing pad and a portion of the lower dielectric layer, forming a contact spacer on an inner wall of the contact opening, and filling the contact opening with a contact plug, a top surface of the contact plug larger than a surface of the contact plug that is in contact with the storage landing pad, the top surface of the contact plug eccentric in relation to the storage landing pad.Type: GrantFiled: February 27, 2006Date of Patent: July 6, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Je-Min Park, Yoo-Sang Hwang, Seok-Soon Song