Static Random Access Memory Structures (sram) (epo) Patents (Class 257/E21.661)
  • Patent number: 7880239
    Abstract: By providing a body controlled double channel transistor, increased functionality in combination with enhanced stability may be accomplished. For instance, flip flop circuits usable for static RAM cells may be formed on the basis of the body controlled double channel transistor, thereby reducing the number of transistors required per cell, which may result in increased information density.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: February 1, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Frank Wirbeleit
  • Publication number: 20110012202
    Abstract: A memory cell has N?6 transistors, in which two are access transistors, at least one pair [say (N?2)/2] are pull-up transistors, and at least another pair [say (N?2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.
    Type: Application
    Filed: July 20, 2009
    Publication date: January 20, 2011
    Inventors: Josephine B. Chang, Leland Chang, Steven J. Koester, Jeffrey W. Sleight
  • Patent number: 7872290
    Abstract: A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: January 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Young Kim, Jin-Jun Park
  • Publication number: 20110006379
    Abstract: A semiconductor device includes a silicon substrate in which active regions of a memory cell are defined, a gate electrode formed on a device isolation insulating film to extend in a first direction, a first insulating film formed on the silicon substrate and the gate electrode, a first plug formed to penetrate the first insulating film, to overlap with the gate electrode and the first active region, and to extend in a second direction perpendicular to the first direction, a second plug penetrating the first insulating film above the second active region, a second insulating film formed on the first insulating film, and an interconnection buried in the second insulating film, and formed to recede from a side surface of the first plug in the second direction and to cover only part of an upper surface of the first plug.
    Type: Application
    Filed: June 28, 2010
    Publication date: January 13, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Yoshihiro Takao
  • Publication number: 20100327372
    Abstract: A semiconductor substrate according to one embodiment includes: a first transistor having a first gate insulating film formed on a semiconductor substrate, a first gate electrode formed on the first gate insulating film and a first sidewall formed on a side face of the first gate electrode, the first gate insulating film comprising a high-dielectric constant material as a base material, a part of the first sidewall contacting with the first gate insulating film and containing Si and N; and a second transistor having a second gate insulating film formed on the semiconductor substrate, a second gate electrode formed on the second gate insulating film and a second sidewall formed on a side face of the second gate electrode so as to contact with the second gate insulating film, the second gate insulating film comprising a high-dielectric constant material as a base material, a part of the second sidewall contacting with the second gate insulating film and containing Si and N, wherein at least one of an abundance
    Type: Application
    Filed: March 15, 2010
    Publication date: December 30, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masakazu Goto
  • Publication number: 20100320541
    Abstract: A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block.
    Type: Application
    Filed: December 28, 2007
    Publication date: December 23, 2010
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Maud Vinet, Olivier Thomas, Olivier Rozeau, Thierry Poiroux
  • Patent number: 7855403
    Abstract: Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: December 21, 2010
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Mitchell Meinhold, Steven L. Konsek, Thomas Rueckes, Frank Guo
  • Publication number: 20100314692
    Abstract: A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to adjust the channel mobility, a stress memorization technique may be used, a wide spacer may be used, germanium may be implanted on tensile stress silicon nitride, a compressive liner may be used or silicon germanium may be embedded in one or more of the devices in the cell. In another configuration, the gate capacitance of each device within the SRAM bit cell may be adjusted to achieve high SRAM yield. For instance, a thick gate oxide may be used, phosphorous pre-doping may be used or fluorine pre-doping may be used in one or more of the devices within the cell.
    Type: Application
    Filed: August 23, 2010
    Publication date: December 16, 2010
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Katsura Miyashita
  • Publication number: 20100308419
    Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.
    Type: Application
    Filed: June 5, 2009
    Publication date: December 9, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Theodore W. Houston, Thomas J. Aton, Scott W. Jessen
  • Publication number: 20100295025
    Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.
    Type: Application
    Filed: August 4, 2010
    Publication date: November 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joerg Appenzeller, AJ Kleinosowski, Edward J. Nowak, Richard Q. Williams
  • Publication number: 20100297815
    Abstract: A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate (362) overlies the first channel. A second transistor (222) is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path (502) oriented parallel to the first current path. A second control gate (360) overlies the second channel.
    Type: Application
    Filed: August 5, 2010
    Publication date: November 25, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ashesh Parikh, Anand Seshadri
  • Patent number: 7838407
    Abstract: A gate of a transistor in an integrated circuit is protected against the production of an interconnection terminal for a source/drain region. The transistor includes a substrate, at least one active zone formed in the substrate, at least one insulating zone formed in the substrate and a gate, the gate being formed above an active zone. A dielectric layer is formed on the transistor, the dielectric layer covering the gate. The dielectric layer is then etched while leaving it remaining at least on the gate so that the gate is electrically insulated from other elements formed above the dielectric layer. This etching is preferably carried out using a mask which was used for fabricating the gate and a mask which was used for fabricating the insulating zone.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: November 23, 2010
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Paul Ferreira
  • Patent number: 7830703
    Abstract: A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: November 9, 2010
    Assignee: NEC Corporation
    Inventors: Koichi Takeda, Masahiro Nomura, Kiyoshi Takeuchi, Hitoshi Wakabayashi, Shigeharu Yamagami, Risho Koh, Koichi Terashima, Katsuhiko Tanaka, Masayasu Tanaka
  • Patent number: 7829942
    Abstract: A first transfer transistor includes a first diffusion layer connected to a first bit line, and a second diffusion layer connected to a first storage node, the first diffusion layer is provided in a substrate, the second diffusion layer is provided in a bottom part of a recess provided in the substrate, a channel region of the first transfer transistor is offset with respect to the second diffusion layer toward the first storage node, and the offset part functions as a resistor.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: November 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Kawasumi, Tetsu Morooka
  • Patent number: 7820512
    Abstract: In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: October 26, 2010
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Suman Datta, Jack Kavalieros, Brian S. Doyle, Uday Shah
  • Publication number: 20100264496
    Abstract: A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k?1) parallel in a direction forming a non-zero angle with the main plane of the substrate, and one or more second transistor(s), respectively including a number m of channels, such that m>k, parallel in a direction forming a non-zero angle, or an orthogonal direction, with the main plane of the substrate.
    Type: Application
    Filed: November 7, 2008
    Publication date: October 21, 2010
    Applicant: COMM. A L'ENERGIE ATOM. ET AUX ENERGIES ALTERNA
    Inventors: Olivier Thomas, Thomas Ernst
  • Patent number: 7812391
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate having a plurality of active regions separately formed by a plurality of trenches formed in a surface of the substrate at predetermined intervals, a first gate insulating film formed on an upper surface of the substrate corresponding to each active region, a gate electrode of a memory cell transistor formed by depositing an electrical charge storage layer formed on an upper surface of the gate insulating film, a second gate insulating film and a control gate insulating film sequentially, an element isolation insulating film buried in each trench and formed from a coating type oxide film, and an insulating film formed inside each trench on a boundary between the semiconductor substrate and the element isolation insulating film, the insulating film containing nontransition metal atoms and having a film thickness not more than 5 ?.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: October 12, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Matsuo, Masayuki Tanaka, Atsuhiro Suzuki
  • Patent number: 7807546
    Abstract: A semiconductor device comprises a substrate. In addition, the semiconductor device comprises an active region and an isolation region. The active region is in the substrate and comprises a semiconductor material. The isolation region is also in the substrate, adjacent the active region and comprises an insulating material. The active region and isolation region form a surface having a step therein. The semiconductor further comprises a dielectric material formed over the step. The dielectric material has a dielectric constant greater than about 8.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: October 5, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chin Lee, Yee-Chia Yeo
  • Publication number: 20100230762
    Abstract: An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).
    Type: Application
    Filed: May 24, 2010
    Publication date: September 16, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: James D. Burnett, Leo Mathew, Byoung W. Min
  • Patent number: 7795116
    Abstract: A wafer-cutting process includes first cutting a semiconductive wafer along a first path at a given first cutting intensity including cutting across an intersection. The process also includes second cutting the semiconductive wafer along a second path at a given second cutting intensity. The second cutting intensity is diminished during crossing the intersection and resumed to the given cutting intensity after crossing the intersection.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: September 14, 2010
    Assignee: Intel Corporation
    Inventors: Mark Dydyk, Erasenthiran Poonjolai
  • Patent number: 7791109
    Abstract: A local interconnect is formed with a gate conductor line that has an exposed sidewall on an active area of a semiconductor substrate. The exposes sidewall comprises a silicon containing material that may form a silicide alloy upon silicidation. During a silicidation process, a gate conductor sidewall silicide alloy forms on the exposed sidewall of the gate conductor line and an active area silicide is formed on the active area. The two silicides are joined to provide an electrical connection between the active area and the gate conductor line. Multiple sidewalls may be exposed on the gate conductor line to make multiple connections to different active area silicides.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Clement H. Wann, Haining S. Yang
  • Patent number: 7777263
    Abstract: To provide a semiconductor integrated circuit device capable of increasing a capacitor capacitance. A semiconductor integrated circuit device according to an embodiment of the present invention includes: a circuit element formed on a semiconductor substrate; and capacitors formed on the semiconductor substrate and including: a lower capacitance electrode formed of a lower wiring line connected to the circuit element; a capacitance insulating film covering an upper surface and a side surface of the lower wiring line; and an upper capacitance electrode formed on the capacitance insulating film, the lower capacitance electrode including at least one of a power supply line and a ground line formed of the lower wiring line.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: August 17, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hirofumi Nikaido, Seiji Hirabayashi
  • Publication number: 20100200918
    Abstract: A CMOS memory element comprising silicon-on-insulator MOSFET transistors is disclosed wherein at least one of the MOSFET transistors is configured such that the body of the transistor is not connected to a voltage source and is instead permitted to electrically float. Implementations of the disclosed memory element with increased immunity to errors caused by heavy ion radiation are also disclosed.
    Type: Application
    Filed: February 10, 2009
    Publication date: August 12, 2010
    Applicant: Honeywell International Inc.
    Inventors: Bradley J. Larsen, Todd A. Randazzo, Cheisan Yue
  • Patent number: 7759235
    Abstract: Methods for manufacturing semiconductor devices are disclosed. In a preferred embodiment, a method of processing a semiconductor device includes providing a workpiece, the workpiece comprising a material layer to be patterned disposed thereon. A hard mask is formed over the material layer. A first pattern is formed in the hard mask and an upper portion of the material layer using a first etch process. A second pattern is formed in the hard mask and the upper portion of the material layer using a second etch process, the second pattern being different than the first pattern. The first pattern and the second pattern are formed in a lower portion of the material layer using a third etch process and using the hard mask as a mask.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: July 20, 2010
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Haoren Zhuang, Helen Wang, Len Yuan Tsou, Scott D. Halle
  • Patent number: 7754560
    Abstract: An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: July 13, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James D. Burnett, Leo Mathew, Byoung W. Min
  • Patent number: 7750416
    Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: July 6, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yi Lee, Harry Chuang, Ping-Wei Wang, Kong-Beng Thei
  • Patent number: 7738282
    Abstract: An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: June 15, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 7732257
    Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device can include a first chip having transistors of only the NMOS type, a second chip having transistors of only the PMOS type, and an interconnection electrically connecting the first and second chips to each other. By forming NMOS and PMOS transistors on separate chips, the total number of implant photo processes can be decreased, thereby reducing the fabrication cost.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: June 8, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Jin Ha Park
  • Patent number: 7718482
    Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: May 18, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Shashank Ekbote, Borna Obradovic, Greg C. Baldwin
  • Patent number: 7714395
    Abstract: A static random access memory at least includes: pluralities of transistors disposed on a substrate, each transistor at least includes a gate, a gate dielectric layer, a source doped region and a drain doped region, in which some of the source doped regions are used for connecting with a Vss voltage or a Vdd voltage, and a salicide layer disposed on the gates, the source doped regions except those source doped regions used for connecting a Vss voltage and a Vdd voltage and the drain doped regions.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: May 11, 2010
    Assignee: United Microelectronics Corp.
    Inventor: Chung-Li Hsiao
  • Patent number: 7709340
    Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-hyon Ahn, Jae-cheol Yoo, Ki-seog Youn, Kwan-jong Roh, Su-gon Bae, Ki-young Kim
  • Patent number: 7700999
    Abstract: An integrated circuit device has a base area defining a longitudinal axis. Four in-line transistors, which are NMOS transistors in exemplary embodiments, are each centered on the longitudinal axis. Two off-set transistors, which are PMOS transistors in exemplary embodiments, are off-set to first and second sides of the longitudinal axis, respectively.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: April 20, 2010
    Assignee: Infineon Technologies AG
    Inventor: Thomas Schulz
  • Patent number: 7682890
    Abstract: A method of fabricating a semiconductor device is provided. A substrate is first provided, and then several IO devices and several core devices are formed on the substrate, wherein those IO devices include IO PMOS and IO NMOS, and those core devices include core PMOS and core NMOS. Thereafter, a buffer layer is formed on the substrate, and then the buffer layer except a surface of the IO PMOS is removed in order to reduce the negative bias temperature instability (NBTI) of the IO PMOS. Afterwards, a tensile contact etching stop layer (CESL) is formed on the IO NMOS and the core NMOS, and a compressive CESL is formed the core PMOS.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: March 23, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Han Hung, Cheng-Tung Huang, Li-Shian Jeng, Kun-Hsien Lee, Shyh-Fann Ting, Tzyy-Ming Cheng, Chia-Wen Liang
  • Patent number: 7674674
    Abstract: A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: March 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark Charles Hakey, David Vaclav Horak, Charles William Koburger, III, Mark Eliot Masters, Peter H. Mitchell
  • Publication number: 20100038684
    Abstract: A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate (362) overlies the first channel. A second transistor (222) is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path (502) oriented parallel to the first current path. A second control gate (360) overlies the second channel.
    Type: Application
    Filed: August 11, 2009
    Publication date: February 18, 2010
    Inventors: Ashesh Parikh, Anand Seshadri
  • Publication number: 20100038752
    Abstract: An intra-metal capacitor unit cell comprises a first electrode and a second electrode formed in the same device layer. A dielectric layer separates the electrodes. The first electrode is substantially surrounded by the second electrode. Misalignment between the first and second electrodes does not substantively alter the capacitance of the unit cell.
    Type: Application
    Filed: August 15, 2008
    Publication date: February 18, 2010
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Chit Hwei NG, Chaw Sing HO, Kerwin KHU, Sanford CHU
  • Patent number: 7663172
    Abstract: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: February 16, 2010
    Assignee: Intel Corporation
    Inventors: Jun-Fei Zheng, Pranav Kalavade
  • Patent number: 7638390
    Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: December 29, 2009
    Assignee: United Microelectric Corp.
    Inventors: Tzung-Han Lee, Kuang-Pi Lee, Wen-Jeng Lin, Rern-Hurng Larn
  • Publication number: 20090294820
    Abstract: Semiconductor devices, capacitors, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a capacitor includes forming a first material over a workpiece, and patterning the first material, forming a first capacitor plate in a first region of the workpiece and forming a first element in a second region of the workpiece. A second material is formed over the workpiece and over the patterned first material. The second material is patterned, forming a capacitor dielectric and a second capacitor plate in the first region of the workpiece over the first capacitor plate and forming a second element in a third region of the workpiece.
    Type: Application
    Filed: May 27, 2008
    Publication date: December 3, 2009
    Inventors: Martin Ostermayr, Richard Lindsay
  • Publication number: 20090269899
    Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
    Type: Application
    Filed: June 25, 2009
    Publication date: October 29, 2009
    Inventors: Kenichi OSADA, Koichiro ISHIBASHI, Yoshikazu SAITOH, Akio NISHIDA, Masaru NAKAMICHI, Naoki KITAI
  • Patent number: 7605447
    Abstract: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: October 20, 2009
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Gregory Costrini, Oleg Gluschenkov, Meikei Ieong, Nakgeuon Seong
  • Publication number: 20090258471
    Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
    Type: Application
    Filed: June 22, 2009
    Publication date: October 15, 2009
  • Patent number: 7598542
    Abstract: SRAM devices and methods of fabricating the same are disclosed, by which a process margin and a degree of device integration are enhanced by reducing the number of contact holes of an SRAM device unit cell using local interconnections. A disclosed example device includes first and second load elements; first and second drive transistors; a common gate electrode connected in one body to a gate electrode of the first load element and a gate electrode of the first drive transistor to apply a sync signal to the gate electrodes; the common gate electrode overlapping with a junction layer of the second load element and a junction layer region of the second drive transistor; the common gate electrode being electrically connected to an upper line via a plug in one contact hole.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: October 6, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Ahn Heui Gyun
  • Patent number: 7598141
    Abstract: A method of fabricating a static random access memory device includes selectively removing an insulating film and growing a single crystalline silicon layer using selective epitaxy growth, the single crystalline silicon layer being grown in a portion from which the insulating film is removed; recessing the insulating film; and depositing an amorphous silicon layer on the single crystalline silicon layer and the insulating film, such that the amorphous silicon layer partially surrounds a top surface and side surfaces of the single crystalline silicon layer.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: October 6, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Hoon Lee, Sang-Jin Park, Won-Seok Yoo, Kong-Soo Lee
  • Patent number: 7598544
    Abstract: Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: October 6, 2009
    Assignee: Nanotero, Inc.
    Inventors: Claude L. Bertin, Mitchell Meinhold, Steven L. Konsek, Thomas Rueckes, Frank Guo
  • Patent number: 7598134
    Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: October 6, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Publication number: 20090244954
    Abstract: A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).
    Type: Application
    Filed: March 26, 2008
    Publication date: October 1, 2009
    Inventors: Ethan H. Cannon, Toshiharu Furukawa, David Horak, Charles W. Koburger, III, Jack A. Mandelman
  • Patent number: 7592268
    Abstract: A method for fabricating a semiconductor device is provided. The method includes: forming a plurality of gate lines on a substrate by performing an etching process; forming an oxide layer on the gate lines and the substrate by employing an atomic layer deposition (ALD) method; and sequentially forming a buffer oxide layer and a nitride layer on the oxide layer.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: September 22, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki-Won Nam, Kyung-Won Lee
  • Publication number: 20090218631
    Abstract: Conductive stripes laterally abutting the dielectric lines are formed over a thin semiconductor layer on a gate dielectric. Angled halo ion implantation is performed to implant p-type dopants on the side of the drains of pull-down transistors and a first source/drain region of each pass gate transistor. The dielectric lines are removed and the pattern of the conductive stripes is transferred into the semiconductor layer to form gate electrodes. The resulting pass gate transistors are asymmetric transistors have a halo implantation on the side of the first source/drain regions, while the side of a second source/drain regions does not have such a halo implantation. As such, the pass gate transistors provide enhanced readability, writability, and stability.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 3, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huilong Zhu, Qingqing Liang
  • Patent number: RE41670
    Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: September 14, 2010
    Assignee: STMicroelectronics, Inc.
    Inventors: Loi Nguyen, Ravishankar Sundaresan