Abstract: A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

Abstract: The invention provides wiring, which can form or disconnect freely the adjacent exposure regions by employing the same optical mask under a condition that a plurality of array substrates are produced on one mother glass substrate; and an optical mask, which can be inspected by utilizing the same probe device for inspecting even though under a condition that the same mother glass substrate is used to produce the array substrates with different sizes; array substrates; and the manufacture method of the same.

Abstract: An exemplary TFT array substrate includes: an insulating substrate (201), a gate line (23) and a repair structure (272) arranged on the insulating substrate, a gate insulating layer (204) covering the gate line and the repair structure; a data line (27) arranged on the gate insulating layer corresponding to the repair structure, which is insulated from the gate line and intersects with the gate line. The repair structure has a gap (274). The gap of the repair structure is located at where the repair structure overlapping to the gate line.

Abstract: An organic light emitting device includes a substrate, first and second signal lines formed on the substrate, a switching thin film transistor (“TFT”) connected to the first and second signal lines and including a first semiconductor, a driving TFT including a second semiconductor, an etch stopper formed on the second semiconductor, driving input and driving output electrodes overlapping the etch stopper and the second semiconductor and opposite to each other with respect to the etch stopper, and a driving control electrode connected to the switching TFT and overlapping the second semiconductor, a first electrode connected to the driving output electrode, a second electrode opposite to the first electrode, and an organic light emitting member, wherein at least one of the etch stopper, the driving input electrode, and the driving output electrode is symmetrical with respect to one straight line.

Abstract: Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.

Abstract: A display device comprises: an insulating substrate; a first electrode formed over the insulating substrate and physically contacting the insulating substrate; an organic layer which is formed over the first electrode and includes an organic light emitting layer; and a second electrode which is formed over the organic layer.

Abstract: A display device includes; an insulating substrate, a thin film transistor disposed on the insulating substrate and which comprises a drain electrode, a wall disposed on the thin film transistor and which includes an opening and a contact hole which exposes the drain electrode, a pixel electrode connected to the drain electrode through the contact hole and which comprises a first part in direct contact with the insulating substrate and a second part connected to the first part, an organic layer disposed on the pixel electrode and which comprises an organic emission layer, and a common electrode disposed on the organic layer

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to integrated circuit device including SOI logic transistors and SOI memory transistors, and method for fabricating such a device. In one embodiment, integrated circuit device includes memory portion having, for example, PD or FD SOI memory cells, and logic portion having, for example, high performance transistors, such as Fin-FET, multiple gate transistors, and/or non-high performance transistors (such as single gate transistors that do not possess the performance characteristics of the high performance transistors). In another aspect, the present invention is directed to a method of manufacture of such integrated circuit device.

Abstract: A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor.

Abstract: Provided are an NMOS device, a PMOS device and a SiGe HBT device which are implemented on an SOI substrate and a method of fabricating the same. In manufacturing a Si-based high speed device, a SiGe HBT and a CMOS are mounted on a single SOI substrate. In particular, a source and a drain of the CMOS are formed of SiGe and metal, and thus leakage current is prevented and low power consumption is achieved. Also, heat generation in a chip is suppressed, and a wide operation range may be obtained even at a low voltage.

Abstract: A thin film transistor substrate and a method of manufacturing the same are disclosed. The method of manufacturing a thin film transistor substrate includes forming a first conductive pattern group including a gate line, a gate electrode, and a lower gate pad electrode on a substrate, forming a gate insulating layer on the substrate on which the first conductive pattern group is formed, forming an oxide semiconductor pattern overlapping the gate electrode on the gate insulating layer, and forming first and second conductive layers on the substrate on which the oxide semiconductor pattern is formed and patterning the first and second conductive layers to form a second conductive pattern group including a data line, a source electrode, a drain electrode, and a data pad.

Abstract: Provided is a method of manufacturing a thin film transistor, the method comprising: forming an amorphous silicon layer on a substrate; forming a polysilicon layer by crystallizing the amorphous silicon layer; forming a mask structure that masks a portion of the polysilicon; forming a source and a drain region and a channel region interposed between the source and the drain regions in the polysilicon layer; injecting impurities having a first concentration using an ion beam implantation into one end and the other end of the polysilicon layer which are not covered by the mask structure. The ends of the polysilicon layer with the mask thereon is then subjected to ion bombardment to increase the level of impurities in the source and drain regions while at the same time shrinking the size of the masked regions.

Abstract: A display substrate includes a substrate including a pixel area, a plurality of gate lines formed on the substrate, a plurality of data lines intersecting the plurality of gate lines, a storage capacitor formed adjacent the plurality of gate lines and the plurality of data lines to surround the pixel area, and a pixel electrode formed in the pixel area, the pixel electrode connected to the storage capacitor.

Abstract: When a semi-conductor film is irradiated with conventional pulsed laser light, unevenness, which is called as ridge, is caused on the surface of the semiconductor film. In the case of a top-gate type TFT, element characteristics are changed depending on the ridge. In particular, there is a problem in that variation in the plural thin film transistors electrically connected in parallel with one another. According to the present invention, in manufacturing a circuit including plural thin film transistors, the width LP of a region (not including a microcrystal region) that is melted by irradiating a semiconductor film with light of a continuous wave laser is enlarged, and active layers of a plurality of thin film transistors (that are electrically connected in parallel with one another) are arranged in one region.

Abstract: The present invention provides a display comprising a panel having a display region for displaying an image and a peripheral region defined therein, a plurality of thin film transistors (TFTs) formed in the display region, p-type and n-type TFTs formed in the peripheral region, and at least one photo diode formed in a horizontal structure in the display or peripheral region; and a method of manufacturing the display. According to the present invention, n-type and p-type TFTs and a photo diode can be together formed without an additional process when forming the TFTs using a polycrystalline silicon thin film, and various peripheral circuits can be configured using such elements.

Abstract: An object of the present invention is to provide a semiconductor device formed by laser crystallization by which formation of grain boundaries in the TFT channel formation region can be avoided, and a method of manufacturing the same. Still another object of the present invention is to provide a method of designating the semiconductor device.

Abstract: A thin film transistor (“TFT”) substrate in which the size of a pixel TFT formed in a display area is reduced using a single slit mask, and the length of the channel area of a protection TFT constituting an electrostatic discharge protection circuit formed in a non-display area is formed larger than that of the pixel TFT using the same mask pattern. The TFT substrate includes a signal line and a discharge line formed on a substrate, a signal supply pad formed on one end of the signal line to supply a signal to the signal line, and an electrostatic discharge protection circuit including at least one protection TFT including a plurality of channels formed between the signal supply pad and the discharge line and/or between the signal line and the discharge line.

Abstract: A thin film transistor (TFT) having improved characteristics, a method for fabricating the same, and an organic light emitting display device (OLED) including the same. The TFT is constructed with a substrate, a semiconductor layer disposed on the substrate and including a channel region, source and drain regions, a gate insulating layer disposed on the semiconductor layer, a gate electrode disposed on the gate insulating layer and corresponding to the channel region, an interlayer insulating layer disposed on the gate electrode, and source and drain electrodes electrically connected to the source and drain regions of the semiconductor layer. The channel region is made from polycrystalline silicon (poly-Si), and the source and drain regions are made from amorphous silicon (a-Si). The polycrystalline silicon of the channel region is formed by crystallizing amorphous silicon using Joule's heat generated by the gate electrode.

Abstract: Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device and the vertically formed gate electrode; and a first solid source material layer, a solid source material interlayer insulating layer, and a second solid source material layer sequentially formed between the lower silicon layer and the upper silicon layer. Therefore, the FinFET can be provided which enhances the density of integration of a circuit, suppresses thin film damages due to ion implantation using solid phase material layers, and has a stabilized characteristic by a simple and low-cost process.

Abstract: It is an object of the present invention to provide a device suitable for new usage by making use of a semiconductor device such as an RFID tag in terms of the capability to transmit and receive data without being contacted therewith, to decrease a burden on a user, and to improve convenience. A semiconductor device is provided to have an arithmetic processing circuit including a transistor, a conductive layer serving as an antenna, a detecting unit having a means for detecting physical quantity or chemical quantity, and a storage unit for storing data detected by the detecting unit, and to cover the arithmetic processing circuit, the conductive layer, the detecting unit, and the storage unit with a protective layer. In addition, diverse information can be monitored and controlled by providing such a semiconductor device for human beings, animals and plants, or the like without being contacted therewith.

Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.

Abstract: A semiconductor device includes: a semiconductor substrate; and a plurality of crystalline insulation films which are formed on the semiconductor substrate and have at least two crystalline insulation films. Crystal orientations of the at least two crystalline insulation films are different from each other.

Abstract: A wafer-level manufacturing method produces stress compensated x-y gimbaled comb-driven MEMS mirror arrays using two SOI wafers and a single carrier wafer. MEMS structures such as comb drives, springs, and optical surfaces are formed by processing front substrate layer surfaces of the SOI wafers, bonding together the processed surfaces, and removing the unprocessed SOI layers to expose second surfaces of the front substrate layers for further wafer-level processing. The bonded SOI wafers are mounted to a surface of the carrier wafer that has been separately processed. Processing wafer surfaces may include formation of a stress compensation layer to counteract physical effects of MEMS mirrors to be formed in a subsequent step. The method may form multi-layered conductive spring structures for the mirrors, each spring having a first conducting layer for energizing a comb drive, a second conducting layer imparting a restoring force, and an insulating layer between the first and second conducting layers.

Abstract: Provided is a method of fabricating a semiconductive oxide thin-film transistor (TFT) substrate. The method includes forming gate wiring on an insulation substrate; and forming a structure in which a semiconductive oxide film pattern and data wiring are stacked on the gate wiring, wherein the semiconductive oxide film pattern is selectively patterned to have channel regions of first thickness and source/drain regions of greater second thickness and where image data is coupled to the source regions by data wiring formed on the source regions. According to a 4-mask embodiment, the data wiring and semiconductive oxide film pattern are defined by a shared etch mask.

Abstract: An image display system has a multi-gate thin film transistor (TFT) disposed on a transparent substrate. The multi-gate TFT includes a silicon film layer, a first electrode and a reflecting layer. The silicon film layer is formed on the transparent substrate and has a first crystallization zone and a second crystallization zone, which are not adjacent to each other. A grain size of the first crystallization zone is smaller than a grain size of the second crystallization zone. The first electrode corresponding to the first crystallization zone is disposed on the silicon film layer. The reflecting layer corresponding to the second crystallization zone is disposed on the transparent substrate. The silicon film layer is disposed on the transparent substrate and the reflecting layer.

Abstract: In a method for manufacturing a flexible memory device and semiconductor device, a stack including an element layer and an insulating layer which seals the element layer is formed over a substrate having a separation layer, and the stack is separated from the separation layer. The element layer includes a memory element having a layer containing an organic compound between a pair of electrodes, a first electrode layer and a second electrode layer, and at least one of the pair of electrode layers is formed using an alloy layer containing tin. The flexible memory device and semiconductor device include a memory element having a layer containing an organic compound between a pair of electrodes, a first electrode layer and a second electrode layer, in which at least one of the pair of electrode layers is formed using an alloy layer containing tin.

Abstract: A method for manufacturing TFTs is provided. It can be applied to both inverted staggered and co-planar TFT structures. The manufacturing method for the staggered TFT includes the formation of a gate electrode, a gate insulator, an active channel layer, a drain electrode, and a source electrode on a substrate. It emphasizes the use of metal oxides or II-VI compound semiconductors and low-temperature CBD process to form the active channel layer. In a CBD process, the active channel layers are selectively deposited on the substrates immersed in the solution through controlling solution temperature and PH value. The invention offers the advantages of low deposition temperature, selective deposition, no practical limit of panel size, and low fabrication cost. Its low deposition temperature allows the use of flexible substrates, such as plastic substrates.

Abstract: Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the semiconductor layer to the insulator. A layer of polycrystalline silicon is deposited overlying the STI and the semiconductor layer and is patterned to form a polycrystalline silicon mask comprising at least a first mask region and a second mask region. First and second openings are etched through the STI and the insulator using the mask as an etch mask. N— and P-type ions are implanted into the diode region through the openings to form the anode and cathode of the diode. The anode and cathode are closely spaced and precisely aligned to each other by the polycrystalline silicon mask. Electrical contacts are made to the anode and cathode.

Abstract: Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 ?m, a DeltaWarp of less than 30 ?m, a bow of less than 10 ?m and a DeltaBow of less than 10 ?m. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.

Abstract: A thin film transistor (TFT) array panel structure and a fabrication method thereof are provided. The method includes the following steps. An insulating substrate is provided, on which a first metal layer is deposited to form a plurality of gate electrodes, a plurality of lower electrodes of storage capacitors, a plurality of scan lines, and a plurality of scan line pads with a first mask process. A TFT island region is formed with a second mask process. Drain electrodes and source electrodes of the TFT, upper electrodes of storage capacitors, pixel electrodes, data lines and data line pads are formed, and a plurality of pixel display regions is defined with a third mask process. The pattern of a passivation layer is defined with a fourth mask. A second metal layer in the pixel display region is removed by selective etching.

Abstract: A display apparatus, such as an organic light emitting diode (“OLED”) display, is driven by thin film transistors (“TFTs”), including a driving TFT and a switching TFT, and a pixel electrode. The display apparatus includes an amorphous silicon layer for the switching TFT and a microcrystalline silicon or polycrystalline silicon layer for the driving TFT. The amorphous silicon layer and the microcrystalline silicon layer are separated by an insulating layer. The apparatus provides product reliability and high image quality. A method of manufacturing the apparatus is characterized by reducing processing steps, and using a special mask which is a half tone mask or a slit mask adapted to forming a source electrode and a drain electrode of the switching TFT or the driving TFT and a semiconductor layer during a photolithographic process.

Abstract: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.

Abstract: It is an object of the present invention to provide a high reliable EL display device and a manufacturing method thereof by shielding intruding moisture or oxygen which is a factor of deteriorating the property of an EL element without enlarging the EL display device. In the invention, application is used as a method for forming a high thermostability planarizing film 16, typically, an interlayer insulating film (a film which serves as a base film of a light emitting element later) of a TFT in which a skeletal structure is configured by the combination of silicon (Si) and oxygen (O). After the formation, an edge portion or an opening portion is formed to have a tapered shape. Afterwards, distortion is given by adding an inert element with a comparatively large atomic radius to modify or highly densify a surface (including a side surface) for preventing the intrusion of moisture or oxygen.

Abstract: A semiconductor device includes a thin-film transistor including a polycrystalline silicon layer, disposed above a substrates serving as an active layer. The thin-film transistor includes a first thin-film transistor section including a first channel region disposed in a drain-side portion of the polycrystalline silicon layer and also includes a second thin-film transistor section including a second channel region that is adjacent to the first channel region with an impurity-implanted region disposed therebetween. The first and second thin-film transistor sections are of the same conductivity type. The gate electrode of the first thin-film transistor section is electrically connected to the gate electrode of the second thin-film transistor section. The first thin-film transistor section has a channel length of less than 2 ?m.

Abstract: A transistor and related method are disclosed. The transistor may include a gate, a sidewall spacer formed along the gate, and a source/drain region positioned only under the sidewall spacer except for a portion at which a contact is positioned. The transistor may be ultra-low power and sub-threshold voltage or near sub-threshold voltage. The transistor may exhibit at least two times reduction in outer fringe capacitance (Cof).

Abstract: Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.

Abstract: Aspects of the present disclosure are directed to reducing strain in at least a portion of a bulk silicon region formed in a silicon-on-insulator (SOI) wafer using a hybrid orientation technology (HOT) process. A trench is formed having a sidewall liner. The liner is recessed prior to oxidation of the bulk silicon region upper surface as part of the HOT process. Recessing the trench liner provides room for the silicon to laterally expand during this oxidation. The trench liner may be recessed by various amounts, such as to approximately the bottom of a hard mask layer, or approximately halfway to the bottom of the hard mask layer, or anywhere in between. The trench liner may even be recessed more deeply than the bottom of the hard mask layer, such as down to or below the upper surface of the upper silicon layer of the surrounding SOI wafer.

Abstract: Provided are a driving device for a unit pixel of an organic light emitting display having an improved structure and a method of manufacturing the same.

Abstract: An exemplary TFT array substrate (20) includes: an insulating substrate (201); a common electrode (220), a common line (224), a gate line (23), and a gate electrode (281) arranged on the insulating substrate; a gate insulating layer (204) covering the common electrode, the common line, the gate line, and the gate electrode; a semiconductor layer (207) arranged on the gate insulating layer; a source and a drain electrodes (281, 282) arranged on two ends the semiconductor layer; a passivation material layer (25) covering the gate insulating layer; a pixel electrode arranged on the passivation material layer, the pixel electrode (290) being electrically connected to the drain electrode via a through hole (284); and at least one through channel (225) arranged crossing the gate insulating layer. The at least one through channel are arranged between the common electrode and the gate line, and between the gate line and the common line.

Abstract: The present invention provides an image display unit and a method for manufacturing the same, in which the number of photolithographic processes can be reduced in the manufacture of an active substrate, and the manufacturing cost can be decreased. In a bottom gate type TFT substrate, a transparent conductive film 16 in the same layer as a pixel electrode 3 is used as a bottom layer, said pixel electrode 3 having said gate electrode 4 on main surface of an insulating substrate 1, and a laminated electrode film with a metal film 26 superimposed on a top layer thereof, and said pixel electrode 3 is used as the transparent conductive film 16.

Abstract: A semiconductor device is provided comprising an oxide layer over a first silicon layer and a second silicon layer over the oxide layer, wherein the oxide layer is between the first silicon layer and the second silicon layer. The first silicon layer and the second silicon layer comprise the same crystalline orientation. The device further includes a graded germanium layer on the first silicon layer, wherein the graded germanium layer contacts a spacer and the first silicon layer and does not contact the oxide layer. A lower portion of the graded germanium layer comprises a higher concentration of germanium than an upper portion of the graded germanium layer, wherein a top surface of the graded germanium layer lacks germanium.

Abstract: A liquid crystal display panel includes a first substrate, a second substrate facing the first substrate, and a liquid crystal layer interposed therebetween. The second substrate includes gate lines, data lines crossing the gate lines to define sub-pixel regions, a thin film transistor connected to a gate line and a data line, an organic passivation layer, a pixel electrode connected to the thin film transistor, a repair portion where the pixel electrode overlaps with a previous gate line, and a repair hole formed in the repair portion to penetrate the organic passivation layer. The pixel electrode is arranged in the repair hole. A method for repairing a defective pixel includes connecting a gate extending portion of the previous gate line to the pixel electrode in the repair portion using a laser, and cutting the defective pixel's drain electrode connected to the pixel electrode.

Abstract: A semiconductor device comprises: a) a multiple layered substrate including a semiconductor substrate, an insulation film formed on the semiconductor substrate, and a semiconductor film, b) a first inverter having a first n-channel type MISFET and a first p-channel type MISFET connected in series each other, being formed on a first region in the multiple layered substrate; c) a second inverter having a second n-channel type MISFET and a second p-channel type MISFET connected in series each other, being formed on a second region; d) a first wiring connecting the output of the first inverter to the input of the second inverter ; e) a second wiring connecting the output of the second inverter to the input of the first inverter ; f) a first back gate region formed on the first region in the semiconductor substrate; g) a second back gate region formed on the second region in the semiconductor substrate; (h) a first connecting portion between the first wiring and the second back gate region; and (i) a second connec

Abstract: A transistor structure comprising a single-crystal gate conductor disposed on a single-phase high-K dielectric gate dielectric is disclosed. The transistor structure is particularly suitable for fully-depleted silicon-on-insulator electronics.

Abstract: An organic light emitting diode display device (OLED display device) having uniform electrical characteristics and a method of manufacturing the same.

Abstract: A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.

Abstract: An apparatus for providing a driving signal to an organic light emitting diode in an image display device includes gate lines for transferring previous and current gate signals, respectively, in a sequential process for providing the driving signal to the organic light emitting diode, a data line for transferring a data signal for displaying images on the image display device, a first switching transistor including a conduction path for transferring the data signal from the data line in response to the current gate signal; a second switching transistor including a conduction path for transferring a reference signal externally supplied in response to the previous gate signal, a third switching transistor including a conduction path for transferring the data signal provided from the first switching transistor in response to a state of the second switching transistor, and a fourth switching transistor including a conduction path for receiving a bias voltage and generating the driving signal to the organic light

Abstract: An array substrate for an LCD device includes a gate line crossing a data line to define a pixel region. A thin film transistor (TFT) includes a gate electrode connected to the gate line, insulating and active layers on the gate electrode, a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode. An auxiliary common electrode includes a horizontal portion disposed in the pixel region. A metal layer overlaps the insulating layer and contacts the horizontal portion of the auxiliary common electrode through a contact hole defined through the insulating layer. A passivation layer is disposed on the TFT and the metal layer. A pixel electrode has a horizontal portion overlapping the metal layer with the passivation layer therebetween to form a storage capacitor, the pixel electrode connected to the drain electrode through a second contact hole defined through the passivation layer.

Abstract: The present invention provides a two-dimensional image detecting apparatus including a mold structure which apparatus can be applied to mammography, and a manufacturing method thereof. The manufacturing method includes: a conversion layer formation step of forming a conversion layer (3) on an active matrix substrate (2); a counter substrate formation step of disposing a spacer material (5) and disposing the counter substrate (6) so as to be opposite to the active matrix substrate (2) via the spacer material (5); a mold resin layer formation step of forming a mold structure layer (8) in a space surrounded by the conversion layer (3), the spacer material (5), and the counter substrate (6); and a cutting step of cutting at least the active matrix substrate (2) so that cut surfaces of the constituent members are flush with each other; and a sealing step of securing a sealing material (7) to the cut surface.

Abstract: A method for making a thin film transistor (TFT) is provided. A mask is first formed on the backside of a substrate, and is used to fabricate a gate, source, and drain of the transistor by backside exposure, such that the source and drain can be self-aligned with the gate pattern. In this way, an alignment shift due to expansion or contraction after performing a high temperature process on an insulating layer can be avoided. Further, since the backside mask previously formed on the substrate can be shifted with the expansion or contraction of the substrate, the process is simplified. Moreover, the source/drain can be accurately aligned with the gate, so that parasitic capacitance can be reduced and flickering of the panel can be avoided.