Abstract: The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated on the silicon substrate. And the present invention is provided with the FIN type transistor with which the gate electrode coiled around the body region formed in the SOI layer, and the planar type transistor which was separated using partial isolation and full isolation together to element isolation, and was formed in the SOI layer.

Abstract: A thin film transistor array panel includes interconnection members interposed between the underlying gate pads made of an Al-containing metal and the overlying contact assistants made of a transparent conductor such as ITO thereon to prevent corrosion of Al due to ITO, or gate-layer signal transmission lines. Gate-layer signal transmission lines are directly connected to the data-layer signal transmission line to prevent corrosion of Al due to ITO in the thin film transistor array panel according to an embodiment of the present invention. The color filters are formed on the thin film transistor array panel to prevent misalignment between the two display panels so as to increase the aperture ratio.

Abstract: Lift-off method and half-tone photolithography are used to fabricate LCD TFT array plate. Only two photo masks are used to respectively define a first and a second metal layers to accomplish the LCD TFT array plate.

Abstract: A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

Abstract: A mask that is capable of forming a thin-film transistor (TFT) with improved electrical characteristics is presented. The mask includes a drain mask pattern, a source mask pattern and a light-adjusting pattern. The drain mask pattern blocks light for forming a drain electrode. The source mask pattern blocks light for forming a source electrode and faces the drain mask pattern. A distance between the drain and source mask patterns is no more than the resolution of an exposing device. The light-adjusting pattern is formed between end portions of the source mask pattern and the drain mask pattern to block at least some light from entering a space between the source and drain mask patterns.

Abstract: The invention provides a display device having a thin film transistor and a storage capacitor storing a display signal applied to a pixel electrode through this thin film transistor on a substrate, where dielectric strength between electrodes forming the storage capacitor is enhanced for increasing the yield. In the storage capacitor, a lower storage capacitor electrode, a thin lower storage capacitor film, a polysilicon layer, an upper storage capacitor film and an upper storage capacitor electrode are layered. The polysilicon layer is formed by crystallization by laser annealing. The polysilicon layer of the storage capacitor is microcrystalline and thus the flatness of its surface is enhanced. The pattern of the polysilicon layer (storage capacitor electrode) is formed larger than the bottom portion of an opening, and the edge of its peripheral portion is located on a buffer film on the slant portion of the opening or on the buffer film on the outside of the opening.

Abstract: Provided are a method of manufacturing a laterally crystallized semiconductor layer and a method of manufacturing a thin film transistor (TFT) using the method. The method of manufacturing the laterally crystallized semiconductor layer comprises: forming a semiconductor layer on a substrate; irradiating laser beams on the semiconductor layer; splitting the laser beams using a prism sheet comprising an array of a plurality of prisms, advancing the laser beams toward the semiconductor layer to alternately form first and second areas in the semiconductor layer so as to fully melt the first areas, wherein the laser beams are irradiated onto the first areas, and the laser beams are not irradiated onto the second areas; and inducing the first areas to be laterally crystallized using the second areas as seeds.

Abstract: In a display device manufacturing method including a step of forming a semiconductor film above a substrate and a step of implanting an impurity to each of a first semiconductor film in a first region of the substrate, a second semiconductor film in a second region outside the first region, and a third semiconductor film in a third region outside the first and second regions, the implanting step includes: a first step of forming a first resist above the substrate so as to be thicker in the first region than in the second region, the first resist covering the first and second regions and having an opening in the third region; a second step of implanting an impurity to only the third semiconductor in the third region using the first resist as a mask; a third step of thinning the first resist so as to form a second resist that covers the first region and has an opening in each of second and third regions; a fourth step of implanting an impurity to the second and third semiconductor films in the second and third

Abstract: A method for forming an opto-electronic device through low temperature processes is provided. An active layer is bonded to a substrate by a common adhesive to maintain or increase the luminous efficiency of the opto-electronic because the electric conductive elements of the opto-electronic are formed on the active layer by a solid phase regrowth process through a low temperature processe.

Abstract: A method for forming a semiconductor device of the present invention solves problems in a process for forming a fin type gate including a recess region, such as, a complicated process, low production margin, and difficulty in forming an accurate fin shape. In a process for forming an isolation dielectric film defining an active region, a nitride film pattern is formed in such a manner that the size of the nitride film is adjusted according to line width of a fin portion in a fin type active region formed in a subsequent process step, and an isolation dielectric film is formed in every region except for the nitride film pattern of a semiconductor substrate. Then, a recess is etched, and the isolation dielectric film is removed from a region where the line width of the nitride film pattern was reduced to a certain degree.

Abstract: A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.

Abstract: A method of fabricating a Complementary Metal-Oxide Semiconductor (CMOS) Thin Film Transistor (TFT) using a reduced number of masks includes: forming a buffer layer on the entire surface of a substrate; forming polysilicon and photoresist layers on the entire surface of the substrate having the buffer layer; exposing and developing the photoresist layer to form a first photoresist pattern having a first thickness in a region where a semiconductor layer of a first TFT is to be formed, a second thickness in a region where a channel and a Lightly Doped Drain (LDD) region of a second TFT are to be formed, and a third thickness in a region where source and drain regions of the second TFT are to be formed; etching the polysilicon layer using the first photoresist pattern as a mask to pattern the semiconductor layers of the first and second TFTs; performing a first ashing process on the first photoresist pattern to form a second photoresist pattern where the region having the third thickness has been removed from th

Abstract: In a thin-film transistor (TFT) substrate, a gate insulating layer is disposed on a gate electrode electrically connected to a gate line. A semiconductor layer is disposed on the gate insulating layer. A source electrode is electrically connected to a data line that intersects the gate line. A drain electrode faces the source electrode and defines a channel area of a semiconductor layer. An organic layer is disposed on the data line and has a first opening exposing the channel area. An inorganic insulating layer is disposed on the organic layer. A pixel electrode is disposed on the inorganic insulating layer and electrically connected to the drain electrode. The inorganic insulating layer covers the first opening, and thickness of the inorganic insulating layer is substantially uniform.

Abstract: A method of fabricating a TFT array substrate that prevents mobile ions from moving from a photoresist to channels of the TFT by the gate electrode of the TFT by performing photolithography processes for ion injection after forming gate electrode of TFT and, in addition, a method of fabricating a TFT array substrate that omits a photolithography process for forming a lower electrode of a storage capacitor by forming the lower electrode of the storage capacitor by a channel doping process for a PMOS TFT.

Abstract: A thin-film device includes a first electrical insulator, an oxide-semiconductor film formed on the first electrical insulator, and a second electrical insulator formed on the oxide-semiconductor film, the oxide-semiconductor film defining an active layer. The oxide-semiconductor film is comprised of a first interface layer located at an interface with the first electrical insulating insulator, a second interface layer located at an interface with the second electrical insulator, and a bulk layer other than the first and second interface layers. A density of oxygen holes in at least one of the first and second interlayer layers is smaller than a density of oxygen holes in the bulk layer.

Abstract: A display device according to an embodiment of the present invention includes: a crystalline silicon layer formed on a substrate and including a source region, a drain region, and a channel region; a wiring layer including a signal line and formed to cover at least a predetermined portion on the source region and the drain region; a gate insulating layer formed on the crystalline silicon layer and the wiring layer; a gate electrode layer formed above the gate insulating layer and including a scanning line, a gate electrode corresponding to the channel region, and a capacitor electrode corresponding to a predetermined portion of the wiring layer; an interlayer insulating film formed on the gate electrode layer; and a pixel electrode layer formed on the interlayer insulating film, and including a pixel electrode connected to the drain region or the source region through a contact hole formed in the gate insulating layer and the interlayer insulating film.

Abstract: A bipolar device is integrated in an active layer, wherein delimitation trenches surround respective active areas housing bipolar transistors of complementary types. Each active area accommodates a buried layer; a well region extending on top of the buried layer; a top sinker region extending between the surface of the device and the well region; a buried collector region extending on top of the well region and laterally with respect to the top sinker region; a base region, extending on top of the buried collector region laterally with respect to the top sinker region; and an emitter region extending inside the base region. The homologous regions of the complementary transistors have a similar doping level, being obtained by ion-implantation of epitaxial layers wherein the concentration of dopant added during the growth is very low, possibly zero.

Abstract: It is an object of the present invention to provide a technology to manufacture a semiconductor sheet or a semiconductor chip with a high yield using a circuit having a thin film transistor. A manufacturing method for a semiconductor device comprises: attaching a flexible base material to an element layer x times (x is an integer number of 4 or more), wherein a thickness of a base material which is attached to the element layer (y+1)th (y is an integer number of 1 or more and less than x) time is the same or smaller than that of a base material which is attached to the element layer y-th (y is an integer number of 1 or more and less than x) time.

Abstract: A component built-in module includes an insulating layer, wirings integrated with both surfaces of the insulating layer, a via connecting the wirings, and one or more components selected from an electronic component and a semiconductor, which is embedded inside of the insulating layer. In this module, at least one of the wirings is formed on a surface of a wiring board, and the components embedded inside of the insulating layer are mounted on and integrated with the wiring board before embedding. This configuration allows the components such as a semiconductor to undergo a mounting inspection and a property inspection before embedding. As a result, the yields of the module can be improved. In addition, since the components are integrated with the wiring board and embedded, the strength thereof can be enhanced.

Abstract: A semiconductor device may include a substrate, an insulating layer formed on the substrate and a conductive fin formed on the insulating layer. The conductive fin may include a number of side surfaces and a top surface. The semiconductor device may also include a source region formed on the insulating layer adjacent a first end of the conductive fin and a drain region formed on the insulating layer adjacent a second end of the conductive fin. The semiconductor device may further include a metal gate formed on the insulating layer adjacent the conductive fin in a channel region of the semiconductor device.

Abstract: Plastic casings are simultaneously molded onto several PCBAs attached to a carrier in a closely-spaced arrangement. All edges of each PCBA have integral connecting segments that extend through grooves formed in the associated mold assembly, and are pinched when the molds assembly is closed to precisely and reliably position the PCBA inside of an associated cavity during the molding process. In one embodiment, the PCB substrate is positioned in a bent arrangement to accommodate the use of inexpensive memory devices. Write-protect switches are provided.

Abstract: A semiconductor device includes at least one semiconductor structure having a plurality of external connection portions on an upper surface, and an insulating member which is made of a resin containing reinforcing materials and arranged on a side of the semiconductor structure. An insulating film is formed on the upper surface of the semiconductor structure, except the external connection portions, and on an upper surface of the insulating member. A plurality of upper wirings each of which has a connection pad portion are located on an upper side of the insulating film and electrically connected to a corresponding one of the external connection portions of the semiconductor structure. The connection pad portion of at least one of the upper wirings is arranged above an upper surface of the insulating member.

Abstract: The invention includes methods for forming integrated circuits within substrates, and embedded circuits. In one aspect, the invention includes a method of forming an integrated circuit within a substrate comprising: a) providing a recess in a substrate; b) printing an antenna within the recess; and c) providing an integrated circuit chip and a battery in electrical connection with the antenna.