Consisting Of Lead-in Layers Inseparably Applied To Semiconductor Body (epo) Patents (Class 257/E23.012)

E Subclasses

Bridge structure with air gap (epo) (Class 257/E23.013)
Beam leads (epo) (Class 257/E23.014)
Pads with extended contours, e.g., grid structure, branch structure, finger structure (epo) (Class 257/E23.015)
For devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g., silicon on sapphire devices, i.e., sos (epo) (Class 257/E23.016)
Materials (epo) (Class 257/E23.017)
Consisting of layered constructions comprising conductive layers and insulating layers, e.g., planar contacts (epo) (Class 257/E23.019)
  • Bumping process
    Patent number: 7112523
    Abstract: A method of forming a plurality of bumps over a wafer mainly comprises the steps of providing a wafer having a plurality of bonding pads, forming an adhesive layer on the surface of the wafer to cover the bonding pads, patterning the adhesive layer to expose the bonding pads to form a patterned adhesive layer, forming a barrier layer and a wetting layer on the patterned adhesive layer and the surface of the wafer, removing the barrier layer and the wetting layer not covering the patterned adhesive layer, forming a plurality of bumps on the patterned wetting layer, and reflowing the bumps.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: September 26, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Ching-Fu Horng