Abstract: A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller footprint than that of the die. A method is disclosed which includes operatively coupling an interposer to a die comprising an integrated circuit, the interposer having a smaller footprint than that of the die, and filling a space between the interposer and the die with an underfill material.

Abstract: A method of assembly of a semiconductor package includes treating the electrical contacts thereof by the application on the electrical contacts of a chemical composition comprising at least one ionic polar surfactant. A semiconductor package has a coating on the electrical contacts thereof, the coating comprising at least one ionic polar surfactant. A device includes a semiconductor package with electrical contacts on a circuit board, the electrical contacts having a coating that includes an ionic surfactant.

Abstract: In an example embodiment, there is a method for packaging an integrated circuit device (IC) having a circuit pattern (305) in a wafer-level chip-scale (WLCS) package (300). The method includes depositing a metal layer (5, 10, 15) on a first dielectric layer (315) and filling (20) in bond pad openings (310) and bump pad openings (330); the metal layer (360) has atop (340) and bottom (360) layer. In the metal layer (360), bond pad connections (310) and bump pad connections (330) are defined (25, 30) by removing the top layer of metal in areas other than at bond pad openings (310) and bump pad openings (330), and leaving the bottom layer (360) of metal in areas without bond pad or bump pad connections. In the bottom metal layer, connection traces between the bond pad and bump pad are defined (35, 40). A second organic dielectric layer (325) is deposited (45) on the silicon substrate (305), enveloping the circuit pattern.

Abstract: The problem of the present invention is to provide a chip-on-chip type semiconductor electronic component and a semiconductor device which can meet the requirements for further density increase of semiconductor integrated circuits. The present invention provides: a chip-on-chip type semiconductor electronic component in which a circuit surface of a first semiconductor chip and a circuit surface of a second semiconductor chip are opposed to each other, wherein the distance X between the first semiconductor chip and the second semiconductor chip is 50 ?m or less, and the shortest distance Y between the side surface of the second semiconductor chip and the first external electrode is 1 mm or less; and a semiconductor device comprising the same.

Abstract: A semiconductor device includes: a substrate having first and second surfaces, the first surface comprising first and second regions; a first semiconductor chip covering the first region; a first seal covering the second region and the first semiconductor chip; and a second seal covering the second surface.

Abstract: Provided is a semiconductor package, a semiconductor module and a method for fabricating the semiconductor package. The method provides a substrate including a bonding pad. The method forms a dielectric layer for exposing the bonding pad on the substrate. The method forms a redistribution line which is electrically connected to the bonding pad, on the dielectric layer. The method forms an external terminal which is electrically connected to the bonding pad without using a solder mask which limits a position of the external terminal, on the redistribution line.

Abstract: A semiconductor device, includes: an organic multilayer wiring substrate having an inner conductive layer; a semiconductor element mounted and connected on one surface of the wiring substrate; and a plurality of solder balls disposed on the other surface in a grid array. A defect portion is formed at an area corresponding to a corner solder ball disposed at an outer peripheral corner, or at an area corresponding to the corner solder ball and peripheral solder balls at the inner conductive layer. Temperature rises of the solder balls disposed in a vicinity of the corner are suppressed, and therefore, the semiconductor device of which fatigue life is prolonged and superior in reliability can be obtained.

Abstract: A semiconductor device according to an aspect of the present invention comprises a package board having first and second surfaces, first external terminals on the first surface which are arranged in matrix, and second external terminals on the first surface which are arranged apart from the first external terminals. Each of the second external terminals includes first and second through holes which extend from the first surface to the second surface, and a metal layer on the first surface which is provided between the first and second through holes. The metal layer passes through the first and second through holes to the second surface.

Abstract: Substrates including conductive pads for coupling the substrates to a microelectronic device and/or package are described herein. Embodiments of the present invention provide substrates comprising one or more conductive pads including a base portion and a pillar portion, the pillar portion being configured to couple with a microelectronic device. According to various embodiments of the present invention, the substrate may be a printed circuit board and/or may be a carrier substrate incorporated into an electronic package. The pillar portion may facilitate interconnection between the substrate and a microelectronic device or package by effectively raising the height of the conductive pad. Other embodiments may be described and claimed.

Abstract: Disclosed is a semiconductor package having a bump ball as an external connection terminal, the bump ball including a core layer containing copper, a copper alloy, aluminum, an aluminum alloy or a combination thereof and a shell layer surrounding the core layer and containing tin, a tin alloy or a combination thereof.

Abstract: In some embodiments, an apparatus and a system are provided. The apparatus and the system may comprise a first integrated circuit die comprising a plurality of silicon vias and a first surface activated bonding site coupled to the plurality of silicon vias, and a second integrated circuit die comprising a second surface activated bonding site coupled to the first surface activated bonding site. The first surface activated bonding site may comprise a first clean metal and the second surface activated bonding site may comprise a second clean metal. If the first surface activated bonding site is coupled to the second surface activated bonding site respective metal atoms of the first activated surface activated bonding site are diffused into the second surface activated bonding site and respective metal atoms of the second activated surface activated bonding site are diffused into the first surface activated bonding site.

Abstract: A connecting terminal provided on a substrate and a connector provided on an electronic device are connected via a bump formed of a first member, which is formed of an anisotropic conductive paste including particles of a conductive material, and a second member which is different in conductivity from the first member. According to such a structure, since the anisotropic conductive paste which is softer as compared to a solder bump is used, stress applied to an interface between the bump and the connecting terminal is relaxed. Accordingly, reliability of connection can be assured even when using a substrate with large surface irregularities and/or bending, in which stress occurs relatively easily in a connection part of the bump and the connecting terminal.

Abstract: An insulative substrate includes a plurality of flexible retaining clips and a plurality of alignment and retaining pins. A metal leadframe includes a plurality of leads. Each lead terminates in a spring contact beam portion. The leadframe is attached to the substrate (for example, by fitting a hole in each lead over a corresponding alignment and retaining pin and then thermally deforming the pin to hold the lead in place). An integrated circuit is press-fit down through the retaining clips such that pads on the face side of the integrated circuit contact and compress the spring contact beams of the leads. After the press-fit step, the retaining clips hold the integrated circuit in place. The resulting assembly is encapsulated. In a cutting and bending step, the leads are singulated and formed to have a desired shape. The resulting low-cost package involves no wire-bonding and no flip-chip bond bump forming steps.

Abstract: An IC device includes a die and a first package interposer stacked over a second package interposer. The IC device includes a first conductive connection from a first bond pad of the die directly to a bond pad of the first interposer and a second conductive connection from a second bond pad of the die directly to a bond pad of the second interposer. Another IC device includes a second die stacked over a separate first die and a first package interposer stacked over a separate second package interposer. The first die is stacked over the first interposer. A first conductive connection exists from a bond pad of the first die directly to a bond pad of the first interposer and a second conductive connection exists from a bond pad of the second die directly to a bond pad of the second interposer.

Abstract: A semiconductor package system includes: providing a semiconductor die with bonding pad on the semiconductor die; attaching the semiconductor die to an intermediate layer; attaching one end of a bonding wire to the bonding pad; forming a bonding ball at the other end of the bonding wire, the bonding ball being fully or partially embedded in the intermediate layer; encapsulating the semiconductor die, the bonding pad, the bonding wire, and a portion of the bonding ball with a mold compound; removing the intermediate layer, resulting in the bonding ball protruding from the exposed mold compound bottom surface; and conditioning the bonding ball

Abstract: Electrically and thermally enhanced die-up ball grid array (BGA) packages are described. A BGA package includes a stiffener, substrate, a silicon die, and solder balls. The die is mounted to the top of the stiffener. The stiffener is mounted to the top of the substrate. A plurality of solder balls are attached to the bottom surface of the substrate. A top surface of the stiffener may be patterned. A second stiffener may be attached to the first stiffener. The substrate may include one, two, four, or other number of metal layers. Conductive vias through a dielectric layer of the substrate may couple the stiffener to solder balls. An opening may be formed through the substrate, exposing a portion of the stiffener. The stiffener may have a down-set portion. A heat slug may be attached to the exposed portion of the stiffener. A locking mechanism may be used to enhance attachment of the heat slug to the stiffener. The heat slug may be directly attached to the die through an opening in the stiffener.

Abstract: A plurality of wiring lines are provided on a first protective film, a second protective film having an opening in a part corresponding to a connection pad portion of a wring line is provided on the first protective film including the wiring line, a columnar electrode is provided on the upper surface of the connection pad portion of the wring line exposed via the opening in the second protective film and on the second protective film around the connection pad portion.

Abstract: An inventive semiconductor device includes: a semiconductor chip; an internal pad provided on a surface of the semiconductor chip for electrical connection; a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed; a stress relief layer provided on the surface protective film and having an opening portion through which the internal pad exposed from the pad opening is exposed; a connection pad including an anchor buried in the pad opening and the opening portion and connected to the internal pad, and a projection provided integrally with the anchor as projecting on the stress relief layer, the projection having a width greater than an opening width of the opening portion; and a metal ball provided for external electrical connection as covering the projection of the connection pad.

Abstract: A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed over the substrate. In one case, the UBM layer is disposed above the passivation layer. Alternatively, the passivation layer is disposed above the UBM layer. A portion of the passivation layer is removed to create a passivation island. The passivation island is centered with respect to the contact pad with its top surface devoid of the UBM layer. A solder bump is formed over the passivation island in electrical contact with the UBM layer. The passivation island forms a void in the solder bump for stress relief. The UBM layer may include a redistribution layer such that the passivation island is offset from the contact pad.

Abstract: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the center portion of the base substrate and the land hole disposed at the edge portion of the base substrate may have different sizes. For example, the sizes of the land holes may increase from the center portion of the base substrate to the edge portion thereof, and alternatively, the sizes of the land holes may decrease from the center portion of the base substrate to the edge portion thereof.

Abstract: Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.

Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.

Abstract: A package circuit board having a reduced package size. The package circuit board may include a semiconductor substrate in place of a printed circuit board. The package circuit board may further include a microelectronic chip mounted on the semiconductor substrate, the microelectronic chip having at least one of active and passive elements formed on the semiconductor substrate semiconductor substrate.

Abstract: A method and device for enhanced reliability for semiconductor devices using dielectric encasement is disclosed. The method and device are directed to improving the reliability of the solder joint that connects the integrated circuit (IC) chip to the substrate. The method comprises applying a layer of a photoimageable permanent dielectric material to a top surface of the semiconductor device, and patterning the layer of the photoimageable permanent dielectric material to have an opening over each feature. The method further comprises dispensing or stencil printing fluxing material into the permanent dielectric material openings, and applying solder, which contains no flux, to a top surface of the fluxing material. In one or more embodiments, the method further comprises heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to sidewalls of the permanent dielectric material openings to form a protective seal.

Abstract: A chip package structure including a first substrate, a chip, a second substrate, a plurality of conductive wires, a plurality of solder balls and a molding compound is provided. The chip is disposed on the first substrate. The second substrate disposed on the chip has an upper surface and a lower surface, in which a distance of the lower surface relative to the chip is smaller than that of the upper surface relative to the chip. The upper surface has a ball mounting surface and a wire bonding surface. A distance between the wire bonding surface and the first substrate is smaller than that between the ball mounting surface and the first substrate. The conductive wires connect the wire bonding surface to the first substrate. The solder balls are disposed on the ball mounting surface. The molding compound is disposed on the first substrate.

Abstract: Conductive structures for electrically conductive pads of a circuit board and fabrication method thereof are proposed. The fabrication method includes: providing a circuit board with a plurality of first, second and third electrically conductive pads; forming first and second conductive layers on the circuit board; forming first and second resist layers respectively on the first and second conductive layers, the resist layers having a plurality of openings for exposing the conductive layers on the pads; forming a metal layer in the openings of the first and second resist layers; and forming a first connecting layer on the metal layer; forming third and fourth resist layers on the first and second resist layers respectively, the third resist layer having a plurality of openings for exposing the first connecting layer on the metal layer on the second electrically.

Abstract: An electronic component such as a semiconductor device is provided which is capable of preventing wiring breakage in a stress concentration region of surface layer wiring lines. In a semiconductor device provided with a support ball (5), no ordinary wiring line is formed in a region (7(A)) in the vicinity of the support ball (5) and a region (7(B)) at the end of the semiconductor chip facing the support ball (5), which are the stress concentration regions of the package substrate (2). Instead, a wiring line (6(C)) is formed away from these regions or a wide wiring line is formed in these regions.

Abstract: A semiconductor package and a method for constructing the package are disclosed. The package includes a substrate and a die attached thereto. A first contact region is disposed on the substrate and a second contact region is disposed on the die. The first contact region, for example, comprises copper coated with an OSP material. A copper wire bond electrically couples the first and second contact regions. Wire bonding includes forming a ball bump on the first contact region having a flat top surface. Providing the flat top surface is achieved with a smoothing process. A ball bond is formed on the second contact region, followed by stitching the wire onto the flat top surface of the ball bump on the first contact region.

Abstract: A semiconductor device 1 is a semiconductor device of the BGA type, and includes a semiconductor chip 10, a resin layer 20, an insulating layer 30, and an external electrode pad 40. The resin layer 20 is constituted by a sealing resin 22 and an underfill resin 24, and covers the semiconductor chip 10. The insulating layer 30 is formed on the resin layer 20. The external electrode pad 40 is formed in the insulating layer 30. This external electrode pad 40 extends through the insulating layer 30. One surface S1 of the external electrode pad 40 is exposed in the surface of the insulating layer 30, and the other surface S2 is located in the resin layer 20. A concave portion 45 is formed in the surface S2 of the external electrode pad 40. The resin composing the resin layer 20 enters into the concave portion 45.

Abstract: A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings.

Abstract: Output pads on an integrated circuit (IC) chip are arranged along a first longer side and are arranged along a second longer side with input pads. The output pads are connected to respective output patterns formed on top and bottom surfaces of a base film. All the output patterns may pass over the first longer side. Alternatively, the output patterns connected to the output pads at the second longer side may pass over a shorter side. These pattern structures establish an effective pad arrangement without increasing the size of a TAB package, yet allowing reduced the chip size.

Abstract: A semiconductor package structure for flip chip package includes at least a patterned circuit layer and an insulating layer alternately stacking up each other. The patterned layer includes a plurality of bump pads, and the insulating layer includes a plurality of etching holes. The etching holes and the bump pads are aligned, such that the bump pads are exposed through the etching holes. A plurality of bumps is disposed on the active surface of the chip, which can be obtained by stud bumping. The etching holes are filled with solder paste, and the bumps of the chips penetrate into the solder filled etching holes. Vibration obtained by mechanical equipment, or ultrasonic equipment can be applied to assist the alignment of the bumps to the corresponding bump pads. A reflow process is applied to collapse the solder paste that fills the etching holes to form electrical connection between the bumps and bump pads.

Abstract: A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package include a substrate including a plurality of pads and a plurality of bumps evenly disposed on an entire region of the substrate regardless of an arrangement of the plurality of pads. According to the present invention, a simplification of a process can be accomplished, a cost of a process can be reduced, reliability can be improved and an under-filling can become easy.

Abstract: Embodiments provide a semiconductor device package and a method for fabricating thereof. The package includes a silicon substrate having a semiconductor device and a metal layer thereon; an insulator ring formed in the silicon substrate and surrounding a portion of a silicon material below the metal layer; and a conductive layer disposed below a backside of the silicon substrate and extended to contact the portion of the silicon material surrounded by the insulator ring below the metal layer.

Abstract: A package of a micro-electro-mechanical systems (MEMS) device includes a cap wafer, a plurality of bonding bumps formed over the cap wafer, a plurality of array pads arrayed on an outer side of the bonding bumps, and an MEMS device wafer bonded to an upper portion of the cap wafer in a manner to expose the array pads.

Abstract: A semiconductor package includes: a semiconductor chip having a first surface, and a second surface that is opposite to the first surface and allows a semiconductor device to be formed thereon; bonding pads disposed on the second surface of the semiconductor chip; and a metal ion barrier layer disposed on the first surface of the semiconductor chip, and preventing metal ions from penetrating into the semiconductor chip through the first surface of the semiconductor chip. Accordingly, the semiconductor package can obtain a superior semiconductor device by minimizing moisture absorption and effectively blocking the penetration of metal ions.

Abstract: A BGA package has an LSI package, a plurality of terminal pads arranged in a grid pattern on the rear surface of the LSI package, and solder balls for soldering the LSI package to a printed wiring board via the terminal pads. A plurality of the terminals pads located at each of the four corners of the outermost periphery of the LSI package form a group of first terminal pads, and each group of terminal pads is formed integrally as a reinforcing pad having a greater size than that of the other terminal pads.

Abstract: The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, forming a stiffening mold on a backside of the coreless substrate strip adjacent to sites where solder balls are to be attached, and attaching solder balls to the backside of the coreless substrate strip amongst the stiffening mold. Other embodiments are also disclosed and claimed.

Abstract: A die rearrangement package structure is provided, which includes an active surface of die with the pads; a first polymer material is covered on the active surface of die and the pads is to be exposed; the conductive posts is disposed among the first polymer material and is electrically connected to the pads; an encapsulated structure is covered the die and the first polymer material and the conductive posts is to be exposed; a second polymer material is covered on the first polymer material and the encapsulated structure to expose the conductive posts; the fan-out patterned metal traces are disposed on the second polymer material and one ends of each fan-out patterned metal traces is electrically connected to the conductive posts; and the conductive elements is electrically connected to another ends of the patterned metal traces.

Abstract: Methods for making solder balls, which can be used to bump semiconductor wafers are disclosed. Methods for bumping semiconductor wafers with the solder balls are also disclosed. The solder balls can be made using an injection molded soldering (IMS) process.

Abstract: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as it modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established be considering the reflective density in opposing conductive build-up layers above and below the core region.

Abstract: A laminated substrate and the semiconductor package utilizing the substrate are revealed. The laminated substrate primarily comprises a core layer, a first metal layer and a first solder mask disposed on the bottom surface of the core layer, and a second metal layer and a second solder mask disposed on the top surface of the core layer. The two solder masks have different CTEs to compensate potential substrate warpage caused by thermal stresses. Therefore, the manufacturing cost of the substrate can be reduced without adding extra stiffeners nor changing thicknesses of semiconductor packages to suppress substrate warpage during packaging processes. Especially, a die-attaching layer partially covers the second solder mask by printing and is planar after pre-curing for zero-gap die-attaching.

Abstract: The mounting height of a semiconductor device is reduced. A wiring substrate has an upper surface with multiple bonding leads formed therein and a lower surface with multiple lands formed therein. This wiring substrate is a multilayer wiring substrate and multiple wiring layers and multiple insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material of the wiring substrate. The bonding leads are formed of part of the uppermost wiring layer and the lands are formed of part of the lowermost wiring layer. The insulating layers include second insulating layers containing fiber and resin and third insulating layers smaller in fiber content than the second insulating layers. The second insulating layers are formed on the upper surface side and on the lower surface side of the core material. The third insulating layers are formed on the upper surface side and on the lower surface side of the core material with the second insulating layers in-between.

Abstract: A high-frequency BGA device (500) with the chip (501) assembled by metal bumps (503) on an insulating substrate (502) with conductive vias (505) and metal traces (504). Chip bumps which serve the high frequency signal terminals are attached directly to the lands (510) on the vias in order to minimize parasitic electrical parameters such as inductance, resistance, and IR drops, thus achieving the required 0.1 nH inductance for each chip terminal. Chip bumps which serve the remaining chip terminals are attached to pads on certain substrate traces. In both cases, the bumps can be attached reliably because the lands on the vias and the pads on the traces are plated with additional metal layers (511, 512), which provide extra thickness as well as a metallurgically suitable surface.

Abstract: The present invention relates to a semiconductor package having an antenna. The semiconductor package includes a substrate, a chip, a molding compound and an antenna. The substrate has a first surface and a second surface. The chip is disposed on the first surface of the substrate, and electrically connected to the substrate. The molding compound encapsulates the whole or a part of the chip. The antenna is disposed on the molding compound, and electrically connected to the chip. The antenna is disposed on the molding compound that has a relatively large area, so that the antenna will not occupy the space for the substrate.

Abstract: A semiconductor package with enhanced mobility of ball terminals is revealed. A chip is attached to the substrate by a die-attaching material where the substrate has at least a stepwise depression on the covered surface to make the substrate thickness be stepwise decreased from a central line of the die-attaching area toward two opposing sides of the substrate. The die-attaching material is filled in the stepwise depression. Therefore, the thickness of the die-attaching material under cross-sectional corner(s) of the chip becomes thicker so that a row of the ball terminals away from the central line of the die-attaching area can have greater mobility without changing the appearance, dimensions, thicknesses of the semiconductor package, nor the placing plane of the ball terminals. Accordingly, the row of ball terminals located adjacent the edges or corners of the semiconductor package can withstand larger stresses without ball cracks nor ball drop.

Abstract: A printed circuit board and method thereof and a solder ball land and method thereof. The example printed circuit board (PCB) may include a first solder ball land having a first surface treatment portion configured for a first type of resistance and a second solder ball land having a second surface treatment portion configured for a second type of resistance. The example solder ball land may include a first surface treatment portion configured for a first type of resistance and a second surface treatment portion configured for a second type of resistance. A first example method may include first treating a first surface of a first solder ball land to increase a first type of resistance and second treating a second surface of a second solder ball land to increase a second type of resistance other than the first type of resistance.

Abstract: A semiconductor package has contacts on both sides of the dice on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice expose the metal plate without extending through the metal plate. A metal layer may be formed on the front side of the dice, covering the exposed portions of the metal plate and extending to side edges of the dice. The metal layer may cover connection pads on the front side of the dice. A second set of scribe lines are made coincident with the first set. Therefore, the metal layer remains on the side edges of the dice coupling the front and the back. As a result, the package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice.