Abstract: An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first packaged microelectronic device adjacent to a support member having support member circuitry, with the first packaged microelectronic device having a first microelectronic die at least partially encased in a first encapsulant to define a first package configuration. The method can further include electrically connecting the first packaged microelectronic device to a first portion of the support member circuitry and positioning at least proximate to the first packaged microelectronic device a second packaged microelectronic device having a second microelectronic die at least partially encased in a second encapsulant to define a second package configuration different than the first package configuration. The first packaged microelectronic device can be positioned between the support member and the second packaged microelectronic device.

Abstract: An interconnection mechanism between plated through holes is disclosed, a first embodiment includes a first substrate having a first plated through hole; a second substrate having a second plated through hole; a metal core is configured in between the two plated through holes; the metal ball has a diameter larger than a diameter of the plated through holes; and melted solder binds the first plated through hole, metal core, and the second plated through hole. A second embodiment includes stacked substrate having a gold plated only on ring pads of the plated through holes; melted solder binds the two gold ring pads.

Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

Abstract: A standing chip scale package is disclosed. The standing chip scale package provides electrical connection to bumped device contacts on both sides of the chip. The package is coupleable to a printed circuit board in a standing configuration such that front and back sides of the bumped chip are substantially perpendicular to a mounting surface. A process of fabricating the standing chip scale package is also disclosed.

Abstract: Semiconductor dice comprise at least one bond pad on an active surface of the semiconductor die. At least one blind hole extends from a back surface of the semiconductor die opposing the active surface, through a thickness of the semiconductor die, to an underside of the at least one bond pad. At least one quantity of passivation material covers at least a sidewall surface of the at least one blind hole. At least one conductive material is disposed in the at least one blind hole adjacent and in electrical communication with the at least one bond pad and adjacent the at least one quantity of passivation material.

Abstract: An integrated circuit packaging system includes: a carrier, having a carrier top side and a carrier bottom side, without an active device attached to the carrier bottom side; an interconnect over the carrier; and a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation, and with the carrier top side partially exposed with the cavity.

Abstract: A silicon contactor of which a side contacts test terminals of a semiconductor testing device and of which an other side contacts ball leads of a semiconductor device so as to be used in the semiconductor testing device, including: conductive silicon parts which are formed opposite to the ball leads and/or the test terminals and include silicon rubber and conductive powders; and an insulating silicon part which is formed by filling silicon rubber among areas of the conductive silicon parts, which do not contact the ball leads, and supports the conductive silicon parts, wherein the conductive powders of the conductive silicon parts include plate type powders. Therefore, the plate type powders are used as the conductive powders of the conductive silicon parts to improve contact characteristics between the conductive silicon parts and the semiconductor device.

Abstract: A substrate including therein a plurality of conductor layers laminated via insulating layers, the substrate mounting at least one semiconductor integrated circuit, wherein the substrate includes a first electrode terminal connected to the semiconductor integrated circuit, a second electrode terminal connected to a terminal on an upper substrate arranged in a layer over the substrate, and on at least part of the perimeter of the first and second electrode terminals, a third electrode terminal located outside the outer edge of the upper substrate.

Abstract: A standing chip scale package is disclosed. The standing chip scale package provides electrical connection to bumped device contacts on both sides of the chip. The package is coupleable to a printed circuit board in a standing configuration such that front and back sides of the bumped chip are substantially perpendicular to a mounting surface. A process of fabricating the standing chip scale package is also disclosed.

Abstract: An integrated-circuit attachment structure comprises an integrated circuit and a package assembly. The package assembly includes a package containing the integrated circuit. The package has pins at its corners and a grid at least primarily of solder halls on its bottom face.

Abstract: A structure includes a solder element for electrically coupling a substrate of an integrated circuit (IC) chip package and a printed circuit board (PCB); and a first electrical property altering, substantially planar member positioned between the solder element and at least one of a landing pad of the substrate and a landing pad of the PCB. In another embodiment, the electrical property altering, planar member can be applied to the solder element(s) between the IC chip and the package substrate.

Abstract: A semiconductor device, includes: an organic multilayer wiring substrate having an inner conductive layer; a semiconductor element mounted and connected on one surface of the wiring substrate; and a plurality of solder balls disposed on the other surface in a grid array. A defect portion is formed at an area corresponding to a corner solder ball disposed at an outer peripheral corner, or at an area corresponding to the corner solder ball and peripheral solder balls at the inner conductive layer. Temperature rises of the solder balls disposed in a vicinity of the corner are suppressed, and therefore, the semiconductor device of which fatigue life is prolonged and superior in reliability can be obtained.

Abstract: A method of making a wafer level chip scale package includes providing a temporary substrate, and forming a wafer level interconnect structure over the temporary substrate using wafer level processes. The wafer level processes include forming a first insulating layer in contact with an upper surface of the temporary substrate, and forming a first conductive layer in contact with an upper surface of the first passivation layer. A first semiconductor die is mounted over the wafer level interconnect structure such that an active surface of the first semiconductor die is in electrical contact with the first conductive layer, and a first encapsulant is deposited over the first semiconductor die. A second encapsulant is deposited over the first encapsulant, and the first and second encapsulants are cured simultaneously. The temporary substrate is removed to expose the first passivation layer.

Abstract: An electrical interconnect within a semiconductor device consists of a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, first barrier layer, adhesion layer, and seed layer are formed over the substrate. An inner core pillar including a hollow interior is centered over and formed within a footprint of the contact pad. A second barrier layer and a wetting layer are formed over the single cylindrical inner core pillar and hollow interior. A spherical bump is formed around the second barrier layer, wetting layer, and single cylindrical inner core pillar. A footprint of the spherical bump encompasses the footprint of the contact pad. The spherical bump is electrically connected to the contact pad.

Abstract: A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve and an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to the protruding TSV tips is on a portion of the sidewalls of the protruding TSV tips. The passivation layers is absent from a distal portion of the protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends including a first metal layer including a first metal other than solder and a second metal layer including a second metal other than solder that covers the exposed tip portion. The bulbous distal tip ends cover a portion of the TSV sidewalls and are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is ?25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.

Abstract: Wafer-level chip-scale package semiconductor devices are described that have bump assemblies configured to mitigate solder bump failures due to stresses, particularly stresses caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having two or more arrays of bump assemblies for mounting the device to a printed circuit board. At least one of the arrays includes bump assemblies that are configured to withstand higher levels of stress than the bump assemblies of the remaining arrays.

Abstract: An integrated circuit including solder balls containing an elastic or resilient material core, a hard or rigid shell substantially enclosing the core, and an electrical contact layer substantially enclosing the shell. The elastic or resilient core serves as a stress buffer layer in a wafer level package (WLP) integrated circuit. The elastic or resilient material core may include an organic plastic material, such as a Divinilbenzene cross-linked co-polymer of relatively high resistance. This material has a relatively good elongation property so that it can effectively absorb forces exerted upon the integrated circuit by, for example, the flexing of a printed circuit board (PCB) or other structure to which the integrated circuit is attached. The hard or rigid shell serves to contain the elastic or resilient core and may include copper. The electrical contact layer serve to provide a good adhesive electrical contact to an under bump metallization (UBM) layer, may include a lead free, Tin-Gold (SnAg) material.

Abstract: A semiconductor device includes an electrode pad provided on a semiconductor chip, in which the electrode pad includes aluminum (Al) as a major constituent and further including copper (Cu), a coupling ball primarily including Cu, the coupling ball is coupled to the electrode pad such that a plurality of layers of Cu and Al alloys are formed at a junction between the electrode pad and the coupling ball, and an encapsulating resin including a halogen of less than or equal to 1000 ppm, the encapsulating resin covering at least the electrode pad and the junction between the electrode pad and the coupling ball. A dimensional area of the plurality of layers of Cu and Al alloys is equal to or larger than 50% of a dimensional area of the junction between the electrode pad and the coupling ball. The plurality of layers of Cu and Al alloys includes a CuAl2 layer, a CuAl layer formed on the CuAl2 layer, and a layer including one of Cu9Al4 and Cu3Al2 formed on the CuAl layer.

Abstract: Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a die having an active surface, a conductive pillar formed on the active surface of the die, the conductive pillar having a side surface, and a molding material encasing the die and the conductive pillar, including covering the active surface of the die and the side surface of the conductive pillar. Methods for making the same also are described.

Abstract: A semiconductor device has a substrate with a contact pad. A first insulation layer is formed over the substrate and contact pad. A first under bump metallization (UBM) is formed over the first insulating layer and is electrically connected to the contact pad. A second insulation layer is formed over the first UBM. A second UBM is formed over the second insulation layer after the second insulation layer is cured. The second UBM is electrically connected to the first UBM. The second insulation layer is between and separates portions of the first and second UBMs. A photoresist layer with an opening over the contact pad is formed over the second UBM. A conductive bump material is deposited within the opening in the photoresist layer. The photoresist layer is removed and the conductive bump material is reflowed to form a spherical bump.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: The semiconductor device manufacturing method includes the steps of attaching two or more solder particles on at least one electrode among a plurality of electrodes of an electronic component, arranging the electrode of the electronic component and an electrode of a circuit board so as to oppose each other, abutting the solder particles attached on a surface of the electrode of the electronic component to the electrode of the circuit board and heating the solder particles, and connecting electrically the electrode of the electronic component and the electrode of the circuit board via two or more solder joint bodies made by melting the solder particles.

Abstract: A printed circuit board providing high reliability using a packaging of high capacity semiconductor chip, a semiconductor package, and a card and a system using the semiconductor package.

Abstract: A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.

Abstract: Embodiments of the present disclosure provide a substrate having (i) a first laminate layer, (ii) a second laminate layer, and (iii) a core material that is disposed between the first laminate layer and the second laminate layer; and a die attached to the first laminate layer, the die having an interposer bonded to a surface of an active side of the die, the surface comprising (i) a dielectric material and (ii) a bond pad to route electrical signals of the die, the interposer having a via formed therein, the via being electrically coupled to the bond pad to further route the electrical signals of the die, wherein the die and the interposer are embedded in the core material of the substrate. Other embodiments may be described and/or claimed.

Abstract: A process for fabricating an electronic component includes a liquid injection molding method for overmolding a semiconductor device. The liquid injection molding method includes: i) placing the semiconductor device in an open mold, ii) closing the mold to form a mold cavity, iii) heating the mold cavity, iv) injection molding a curable liquid into the mold cavity to overmold the semiconductor device, v) opening the mold and removing the product of step iv), and optionally vi) post-curing the product of step v). The semiconductor device may have an integrated circuit attached to a substrate through a die attach adhesive.

Abstract: A semiconductor device has a first conductive layer formed over a top surface of a substrate. A first insulating layer is formed over the substrate. A first dielectric layer is formed over the first insulating layer. A second conductive layer is formed over the first conductive layer and first dielectric layer. A second dielectric layer is formed over the second conductive layer. A polymer material is deposited over the second dielectric layer and second conductive layer. A third conductive layer is formed over the polymer material and second conductive layer. The third conductive layer is electrically connected to the second conductive layer. A first solder bump is formed over the third conductive layer. A conductive via is formed through a back surface of the substrate. The conductive via is electrically connected to the first conductive layer. The polymer material has a low coefficient of thermal expansion.

Abstract: Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane.

Abstract: An integrated circuit bridge interconnect device includes a first die and a second die provided in a side-by-side configuration and electrically interconnected to each other by a bridge die. The bridge die includes through silicon vias (TSVs) to connect conductive interconnect lines on the bridge die to the first die and the second die. Active circuitry, other than interconnect lines, may be provided on the bridge die. At least one or more additional die may be stacked on the bridge die and interconnected to the bridge die.

Abstract: An IC die includes active circuitry and I/O nodes tied together in first net and at least a second net. A first die pad and a second die pad adjacent thereto are coupled to the first and second net, respectively. A redirect layer (RDL) coupled to the die pads over a first dielectric vias includes a first RDL trace lateral coupling the first die pad and first RDL pad and a second RDL trace coupling the second die pad and second RDL pad. The first RDL pad includes an RDL notch facing the second RDL trace. Under bump metallization (UBM) pads on a second dielectric include a first UBM pad coupled to the first RDL pad over a second dielectric via. A first metal bonding connector is on the first UBM pad. The first UBM pad or first metal bonding connector overhangs the first RDL pad over the notch.

Abstract: A package device and a fabrication method thereof comprises providing a plurality of package units each having a plurality of penetrated holes; stacking the plurality of package units in a manner such that the penetrated holes of the plurality of package units are aligned; filling a conductive material into the plurality of penetrated holes substantially, so as to electrically connect the plurality of package units through the conductive material; and disposing a plurality of solder balls on the bottom of the conductive material filling the plurality of penetrated holes, and connecting the plurality of solder balls with the conductive material electrically.

Abstract: A semiconductor package includes a carrier strip having a die cavity and bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip. In one embodiment, the semiconductor die is mounted using a die attach adhesive. In one embodiment, a top surface of the first semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. A metal layer is disposed over the carrier strip to form a package bump and a plated interconnect between the package bump and a contact pad of the first semiconductor die. An underfill material is disposed in the die cavity between the first semiconductor die and a surface of the die cavity. A passivation layer is disposed over the first semiconductor die and exposes a contact pad of the first semiconductor die. An encapsulant is disposed over the carrier strip.

Abstract: A device includes a semiconductor chip having contact pads arranged on a first main face of the semiconductor chip. A first material has an elongation to break of greater than 35% covering the first main face of the semiconductor chip. An encapsulation body covers the semiconductor chip. A metal layer is electrically coupled to the contact pads of the semiconductor chip and extends over the encapsulation body.

Abstract: A semiconductor device structure has a semiconductor die that has a bond pad with a passivation layer surrounding a portion of the bond pad. A nickel layer, which is deposited, is on the inner portion. A space is between a sidewall of the nickel layer and the passivation layer and extends to the bond pad. A palladium layer is over the nickel layer and fills the space. The space is initially quite small but is widened by an isotropic etch so that when the palladium layer is deposited, the space is sufficiently large so that the deposition of palladium is able to fill the space. Filling the space results in a structure in which the palladium contacts the nickel layer, the passivation layer and the bond pad.

Abstract: An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and a pad within the pad ring on the semiconductor die. In an embodiment, a first dielectric layer is formed such that it terminates on each die within the die's pad ring. Tracks are then formed in a conductive layer which contact one of the pads and run over the edge of an opening onto the surface of the first dielectric layer. These tracks may be used to form an electrical connection between the pad and a solder ball.

Abstract: A transition layer 38 is provided on a die pad 22 of an IC chip 20 and integrated into a multilayer printed circuit board 10. Due to this, it is possible to electrically connect the IC chip 20 to the multilayer printed circuit board 10 without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on an aluminum pad 24, it is possible to prevent a resin residue on the pad 24 and to improve connection characteristics between the die pad 24 and a via hole 60 and reliability.

Abstract: A substrate for an integrated circuit package is disclosed. The substrate comprises a core comprising a first dielectric layer having a first thickness; conductive traces formed on the first dielectric layer for routing signals within the integrated circuit package, wherein the conductive traces have a second thickness; and a substrate support structure comprising conductive traces formed on the first dielectric layer, where the conductive traces of the substrate support structure have a third thickness which is greater than the second thickness. A method of forming an integrated circuit package is also disclosed.

Abstract: A single-layer board on chip package substrate and a method of manufacturing the same are disclosed. The single-layer board on chip package substrate in accordance with an embodiment of the present invention includes an insulator, which has a window perforated therethrough, a wiring pattern, a wire bonding pad and a solder ball pad, which are embedded in one surface of the insulator, and a solder resist layer, which is formed on the one surface of the insulator such that the solder resist layer covers the wiring pattern but at least portions of the wire bonding pad and the solder ball pad are exposed.

Abstract: An integrated circuit package system includes: interconnection pads; a first device mounted below the interconnection pads; a bond wire, or a solder ball connecting the first device to the interconnection pads; a lead connected to the interconnection pad or to the first device; an encapsulation having a top surface encapsulating the first device; and a recess in the top surface of the encapsulation with the interconnection pads exposed therefrom.

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method further includes forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands.

Abstract: The invention relates to an integrated circuit module (3) comprising a carrier substrate (4) with terminals for electrically contacting the carrier substrate (4) and a motherboard (2) and comprising at least one semiconductor chip (9) that is electrically contacted to the carrier substrate (4) and integrated into the substrate (4). The carrier substrate (4) comprises at least one cavity (8) that adjoins a mounting surface (10) for the motherboard (2) and holds at least one semiconductor chip (9). The cavity (8) is equipped with connection contacts (11a, 11b) for assigned connections of the semiconductor chip or chips (9), said contacts electrically contacting the semiconductor chip (9) and the carrier substrate (4). The carrier substrate (4) is multi-layered and comprises conductor tracks that extend transversally through several layers and the cavity (8) is hermetically sealed by a thermally conductive cover (12).

Abstract: Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed.

Abstract: A wafer level chip size package (WLCSP) and a method of manufacturing the same are disclosed. Lands are formed at the ends of redistribution layers. The redistribution layers excluding the lands and a first dielectric layer are covered with a second dielectric layer. After forming a first under bump metallurgy (UBM) layer on the land, a solder ball is reflowed to the first UBM layer. A second UBM layer is widely formed on the entire second dielectric layer that is the outer circumference of the first UBM layer and is connected to the redistribution layer through a via-hole. Therefore, the second UBM layer having a large area can be used as a ground plane or a power plane. In addition, the second UBM layer can electrically connect the redistribution layers physically separated from each other. Therefore, the plurality of redistribution layers can cross each other without being electrically shorted with each other.

Abstract: Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices re disclosed herein. One aspect of the invention is directed toward a microelectronic workpiece comprising a substrate having a device side and a backside. In one embodiment, the microelectronic workpiece further includes a plurality of dies formed on the device side of the substrate, a dielectric layer over the dies, and a plurality of bond-pads on the dielectric layer. The dies have integrated circuitry and a plurality of bond-pads electrically coupled to the integrated circuitry. The ball-pads are arranged in ball-pad arrays over corresponding dies on the substrate. The microelectronic workpiece of this embodiment further includes a protective layer over the backside of the substrate. The protective layer is formed on the backside of the substrate from a material that is in a flowable state and is then cured to a non-flowable state.

Abstract: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics.

Abstract: Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes of circuit contact pitch. Also disclosed are methods for the construction of the devices and applications therefore.

Abstract: A flip-chip fan-out wafer level package for package-on-package applications includes a semiconductor die with solder bumps on an upper surface in a flip chip configuration. The die is inverted, with an upper surface facing an upper side of a redistribution layer, with the solder bumps in electrical contact with respective chip contact pads of the redistribution layer. The redistribution layer includes conductive traces that place each of the solder bumps in electrical contact with one or both of one of a plurality of upper redistribution contact pads and one of a plurality of lower redistribution contact pads. Each of the plurality of upper redistribution contact pads has an upper solder ball in electrical contact therewith. The die and the upper solder balls are at least partially encapsulated in a layer of mold compound positioned on the upper surface of the redistribution layer, and whose lateral dimensions are defined by the lateral dimensions of the redistribution layer.

Abstract: A dished micro-bump structure with self-aligning functions is provided. The micro-bump structure takes advantage of the central concavity for achieving the accurate alignment with the corresponding micro-bumps.

Abstract: A semiconductor device with improved moisture resistance and its manufacturing method as well as a manufacturing method of a semiconductor device which simplifies a manufacturing process and improves productivity are offered. This invention offers a CSP type semiconductor device and its manufacturing method that can prevent moisture and the like from infiltrating into it to attain high reliability by covering a side surface of a semiconductor chip with a thick protection layer. This invention also offers a highly productive manufacturing method of semiconductor devices by which a supporter bonded to semiconductor dice is etched from a back surface-side of the supporter so that the semiconductor devices can be separated without dicing.

Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.