Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a semiconductor chip, and a plurality of conductive balls, e.g., solder balls formed on a joint surface of the semiconductor chip. A dummy board includes openings aligned with the solder balls and is bonded to the joint surface of the semiconductor chip. An adhesive material is interposed between the semiconductor chip and the dummy board to adhere the dummy board to the semiconductor chip. The adhesive material is applied on an adhesion surface of the dummy board adhered to a joint surface of the semiconductor chip. The dummy board is adhered to the joint surface of the semiconductor chip such that the solder balls are aligned with the openings. Cheap underfill materials can be selectively used, and a process time for reflow and curing of the adhesive material can be greatly reduced.

Abstract: An integrated circuit includes a first surface configured for mounting to a carrier, an active area of the integrated circuit spaced from the first surface, a bond pad disposed over and in electrical communication with the active area, and a ceramic inorganic stress-buffering layer disposed between the active area and the bond pad.

Abstract: A composite semiconductor package is disclosed. The package includes a lead frame having first and second die bonding pads, the first and second die bonding pads having a large lateral separation therebetween, a first device bonded to the first die bonding pad, a second device bonded to the second die bonding pad, a plurality of first leads coupled to the first die bonding pad, a plurality of second leads coupled to the second die bonding pad, and an encapsulant covering the lead frame, the first and second devices and at least a portion of the first and second pluralities of leads. The package may be a TSSOP-8 composite package having a common drain MOSFET pair and an IC.

Abstract: A semiconductor device (20) in which a semiconductor element (2) is mounted on one of a front side and a back side of a wiring board (3), and a plurality of lands (9) (23) for external connection are provided on the other side of the wiring board, the land (9) (23) including a land terminal (10) (24) formed on the wiring board and a spherical solder ball (11) (25) formed on the land terminal, wherein a first land (23) immediately below an outer end corner (B) of the semiconductor element (2) is larger in size than the other lands (9).

Abstract: A method of manufacturing a semiconductor device includes: applying a paste containing acid to an electrical connection section which is electrically connected with a semiconductor substrate; removing the paste from the electrical connection section by washing the electrical connection section; and providing a conductive material to the electrical connection section.

Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Abstract: A semiconductor device includes: a semiconductor substrate having an integrated circuit formed thereon and an electrode electrically coupled to the integrated circuit; a passivation film formed on a surface of the semiconductor substrate, the surface having the electrode formed thereon; a first metal layer formed so as to come into contact with the passivation film; a resin layer formed on the first metal layer; a wiring formed so as to be electrically coupled to the electrode and reach an upper surface of the resin layer; and a second metal layer formed so as to be in contact with the first metal layer and reach the upper surface of the resin layer.

Abstract: A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that includes a plurality of address pads and respective supply pins. The method includes: realizing at least one configuration terminal having a first and a second portion structurally independent and connected to at least one contact terminal; providing the contact of such first and second portions with respective terminals; and configuring the device by a short-circuiting of the contact terminal with at least one of said terminals.

Abstract: An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the openings therethrough. A second UBM layer of chromium/copper alloy is deposited on the first UBM layer. A third UBM layer of copper is deposited on the second UBM layer. UBM pads of at least two different sizes are formed from the UBM layers. Solder paste is printed over at least some of the UBM pads. The solder paste is reflowed to form at least smaller solder bumps on at least some of the UBM pads. Bigger solder bumps are formed on at least some of the UBM pads.

Abstract: A semiconductor device is made by providing a semiconductor die having a contact pad, forming a circular solder bump on the contact pad, providing a substrate having a trace line, disposing a non-circular solder resist opening over the trace line, placing the solder bump in proximity to the trace line, and reflowing the circular solder bump to metallurgically connect the circular solder bump to the trace line. The circular solder bump contacts less than an entire perimeter of the non-circular solder resist opening which creates one or more vents in areas where the circular solder bump is discontinuous with the non-circular solder resist opening. The non-circular solder resist opening can be a rectangle, triangle, ellipse, oval, star, and tear-drop. An underfill material is deposited under the first substrate. The underfill material penetrates through the vents to fill an area under the solder bump.

Abstract: A device package, such as a BGA, to be mounted on a printed wiring board (PWB) is disclosed. The bottom electrodes of the device package are arranged in an array such that intervals between the edges of the bottom electrodes become different from place to place. The intervals may be set wider at the peripheral positions of the bottom electrodes. The PWB includes pads that are located at positions corresponding to the bottom electrodes.

Abstract: A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR?2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.

Abstract: A thermal-enhanced multi-hole semiconductor package is revealed, primarily comprising a substrate with a plurality of alignment holes, a chip disposed on the substrate, an internal heat sink attached to the chip, and an encapsulant. The internal hear sink has a plurality of alignment bars and a heat dissipation surface. The alignment bars are inserted into the alignment holes, but not fully occupying the alignment holes to provide a plurality of flowing channels therein. The encapsulant completely encapsulates the alignment bars through filling the flowing channels. Therefore, the internal heat sink can be aligned to the substrate and is integrally connected with the chip and the substrate utilizing a small amount of adhesive or without any adhesive to form a composite having high rigidity and strong adhesion.

Abstract: An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is connected between the first and second metal ground layers. The second metal ground layer is connected to the casing. A chip is electrically connected to the printed circuit board and includes a die and a heat-conducting portion connected to the die and soldered with the first metal ground layer. Heat generated by the chip is conducted to the casing through the heat-conducting portion, first metal ground layer, metal connecting portion, and second metal ground layer.

Abstract: The invention provides thermally conductive material so that less heat traveling from one side of a layer will reach connection material on another side of a layer. Rather, some of the heat will be conducted away by the thermally conductive material and dissipated.

Abstract: Methods for creating redistribution layers for only selected dice, such as known good dice, to form relatively thin semiconductor component assemblies and packages, and the assemblies and packages created by the methods, are disclosed. A sacrificial layer is deposited on a support substrate. An etch stop layer having a lower etch is deposited on the sacrificial layer. Redistribution lines in a dielectric material are formed on the support substrate on the etch stop layer. Semiconductor dice, either singulated or at the wafer level, are connected to the redistribution lines. The assembly may be scribed to allow the sacrificial layer to be etched to enable removal of the semiconductor dice and associated redistribution layer from the support substrate. The etch stop layer is removed to allow access to the redistribution lines for conductive bumping.

Abstract: A ball grid array semiconductor device has a wiring substrate (2), a semiconductor chip (6) disposed on one surface side of the wiring substrate, and a bump arrangement (5) as external terminals disposed on a surface side, opposite to the one surface side, of the wiring substrate. The semiconductor chip is mounted so that the center of the semiconductor chip is shifted from the center of the semiconductor device by one pitch or more of the bump arrangement, and the bump arrangement has a reinforcing structure (5-2) for a bump array located at a position farthest from the center of the semiconductor device in a shift direction of the semiconductor chip.

Abstract: A chip package includes a coreless package substrate and a chip. The coreless package substrate includes an interconnection structure and a ceramic stiffener. The interconnection structure has a first inner circuit, a carrying surface and a corresponding contact surface. The first inner circuit has multiple contact pads disposed on the contact surface. The ceramic stiffener is disposed on the carrying surface and has a first opening. In addition, the chip is disposed on the carrying surface and within the first opening and electrically connected to at least one of the contact pads.

Abstract: A ball grid array includes: a semiconductor chip having multiple pads; and an interposer for mounting the semiconductor chip on a first surface. The interposer includes multiple wirings on the first surface and multiple ball terminals on a second surface opposite to the first surface. Each wiring is connected to a corresponding pad of the semiconductor chip, and is electrically connected to a corresponding ball terminal. At least one of ball terminals providing a power supply terminal or a ground terminal provides a common ball terminal for connecting to at least two of the pads of the semiconductor chip through two wirings.

Abstract: An electronic package is provided. The electronic package includes a first substrate, an electronic component, a first sealant, a second substrate, a plurality of bonding wires and a second sealant, wherein the first substrate has opposing upper and lower surfaces and a plurality of bonding pads is disposed on the upper surface of the first substrate. The electronic component is positioned on the upper surface of the first substrate and electrically connected to the bonding pads. The first sealant is formed on the upper surface of the first substrate to encapsulate the electronic component. The lower surface of the second substrate is attached to the first sealant. The upper surface of the second substrate includes a central protrusion and a rim portion which surrounds and is lower than the central protrusion. A plurality of bonding wires is used to electrically connect the rim portion to the first substrate.

Abstract: A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads.

Abstract: Semiconductor chip packages have die asymmetrically arranged on the respective substrates. Two such packages having complementary arrangements can be stacked, one inverted with respect to the other, such that the two die are situated side-by-side in the space between the two substrates. Also, multipackage modules include stacked packages, each having the die asymmetrically arranged on the substrate. Adjacent stacked packages have complementary asymmetrical arrangements of the die, and one package is inverted with respect to the other in the stack, such that the two die are situated side-by-side in the space between the two substrates. Also, methods are disclosed for making the packages and for making the stacked package modules.

Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.

Abstract: A wiring board according to the present invention includes: an insulating base 22; a plurality of first conductor wirings 23a aligned in an inner region on the insulating base; bumps 24 formed on the respective first conductor wirings; and a protective film 25a that is formed on the insulating base so as to cover the first conductor wirings and has an opening region through which the bumps are exposed. The height of at least part of a surface of the protective film from a surface of the insulating base is greater than the height of the bumps from the surface of the insulating base. With this configuration, it is possible to decrease the thickness in the state where a protective tape is placed on the wiring board to protect bumps, thereby increasing the length of the wiring board that can be held by a reel for supplying the wiring board.

Abstract: Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while the appearance cracks and the warpage defects can be prevented.

Abstract: An integrated circuit package system comprising: providing a package die; and connecting a connector lead having a first connector end with a protruded connection surface and a lowered structure over the package die.

Abstract: A ball grid array is mounted on a wiring board in a rectangular shape provided with screw insertion holes and fixed with screws to a mounting member at four points. Solder banks are formed around the screw insertion holes and pressed contact with a ground connecting face on the mounting member. The screw insertion holes are located in corners of an imaginary rectangular outline imagined on a board surface of the wiring board. Two of the holes diagonally positioned on the outline are located in one of corners and at an inward position of the wiring board, while the remaining two are located at intermediate parts of two sides embracing the corner. The wiring board is divided into a rectangular first zone surrounded by the four points and an L-shape second zone. The ball grid array is mounted on an intersecting area between vertical and transverse areas defining the L-shape.

Abstract: A method for forming a bump includes the steps of forming a resist layer so that a through-hole formed therein is located on a pad; and forming a metal layer to be electrically connected to the pad conforming to the shape of the through-hole. The metal layer is formed so as to have a shape in which is formed a region for receiving a soldering or brazing material.

Abstract: An interconnection mechanism between plated through holes is disclosed, a first embodiment includes a first substrate having a first plated through hole; a second substrate having a second plated through hole; a metal core is configured in between the two plated through holes; the metal ball has a diameter larger than a diameter of the plated through holes; and melted solder binds the first plated through hole, metal core, and the second plated through hole. A second embodiment includes stacked substrate having a gold plated only on ring pads of the plated through holes; melted solder binds the two gold ring pads.

Abstract: A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.

Abstract: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.

Abstract: Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices. One aspect of the invention is directed toward a microelectronic workpiece comprising a substrate having a device side and a backside. In one embodiment, the microelectronic workpiece further includes a plurality of dies formed on the device side of the substrate, a dielectric layer over the dies, and a plurality of bond-pads on the dielectric layer. The dies have integrated circuitry and a plurality of bond-pads electrically coupled to the integrated circuitry. The ball-pads are arranged in ball-pad arrays over corresponding dies on the substrate. The ball-pads of one array, for example, are electrically coupled to the bond-pads of the corresponding die. The microelectronic workpiece of this embodiment further includes a protective film over the dielectric layer.

Abstract: Some embodiments of the present invention relate to an electronic assembly that includes a substrate and a die. The electronic assembly further includes an alignment bump on one of the die and the substrate and a group of mating bumps on the other of the die and the substrate. The group of mating bumps is positioned such that if the alignment bump engages each of the mating bumps, the die is appropriately positioned relative to the substrate at that location where the alignment bump engages the group of mating bumps. In some embodiments, the alignment bump extends from the substrate while in other embodiments the alignment bump extends from the die. The alignment bump on the substrate (or die) may be part of a plurality of alignment bumps such that each alignment bump engages a different group of mating bumps on the die (or substrate).

Abstract: To miniaturize a semiconductor device, a package substrate is provided having terminals formed on the main surface, lands formed on the back surface, through holes formed by laser beam machining and arranged at the upper part of each of the lands, and plating films arranged in the through hole to connect the lands with the terminals electrically. A semiconductor chip is mounted on the main surface of the substrate, a conductive wire connects the pad of the chip and the substrate, and solder bumps are formed in the lands. Since the through holes are formed by laser beam machining, the openings of the through holes are small. Further, the through holes have a larger opening on the main surface of the package substrate than the opening on the back surface of the package substrate. Therefore, it becomes possible to arrange a solder bump directly under each of the through holes, and miniaturization can be realized.

Abstract: Disclosed is a semiconductor package and method for package a semiconductor that has high reliability. A semiconductor package according to the present invention comprises a first substrate on which a circuit pattern and an electrode pad are formed; a second substrate which is adhered to the first substrate and on which a hole is formed; and a solder ball adhered to the electrode pad through the hole formed on the second substrate. Then, the second substrate is used as a solder resist. Accordingly, since the first substrate and the second substrate are formed of same material, the BGA package can be prevented from being cracked and being nonuniform when fired.

Abstract: A method for manufacturing bonded substrates includes: forming the first terminals on the first substrate, the first terminals each having a metal core projecting from a surface of the first substrate, each metal core coated with a solder layer lower in a melting point than the metal core; forming the conductive second terminals on the second substrate; and electrically bonding the first terminals to the second terminals by heating the first and second substrates while applying pressure to the first substrate and the second substrate. In the forming of the first terminals, a ratio of a height of the metal core from the surface of the first substrate in a thickness direction of the first substrate to a thickness of the solder layer in the thickness direction of the first substrate is in a range of from 1:1 to 2:1.

Abstract: The present invention provides a semiconductor device exhibiting an improved reliability of a bump coupling section. A semiconductor device is provided, which comprises: an interconnect layer; a stress-relaxing layer, covering the interconnect layer and provided with an opening exposing at least a portion of the interconnect layer; a post, covering the opening and provided so as to overlap with the stress-relaxing layer disposed around the opening; and a resin layer, provided around the post to cover the stress-relaxing layer, wherein a value of 2A/C is within a range of from 0.1 to 0.5, wherein C is a diameter of the post and 2A is a width of an overlapping region of the stress-relaxing layer with the post.

Abstract: Provided is a semiconductor device including a wafer having an electrode pad; an insulation layer that is formed on the wafer and has an exposure hole exposing the electrode pad; a redistribution layer that is formed on the insulation layer and the exposure hole of the insulation layer and has one end connected to the electrode pad; a conductive post that is formed at the other end of the redistribution layer; an encapsulation layer that is formed on the redistribution layer and the insulation layer such that the upper end portion of the conductive post is exposed; and a solder bump that is formed on the exposed upper portion of the conducive post.

Abstract: A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.

Abstract: A microelectronic assembly includes a microelectronic package having a microelectronic element with faces and contacts, a flexible substrate spaced from and overlying a first face of the microelectronic element, and a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, at least some of the conductive posts being electrically interconnected with the microelectronic element. The package includes a plurality of support elements disposed between the microelectronic element and the substrate and supporting the flexible substrate over the microelectronic element. At least some of the conductive posts are offset from the support elements. The assembly includes a circuitized substrate having conductive pads confronting the conductive posts of the microelectronic package, whereby the conductive posts are electrically interconnected with the conductive pads.

Abstract: In some embodiments, flexible joint methodology to attach a die on an organic substrate is presented. In this regard, an integrated circuit chip package substrate is introduced having an organic substrate, an interposer coupled with a surface of the organic substrate, the interposer having cavities to accept bumps of a die, and a flexible tape layer coupled with a surface of the interposer, the flexible tape layer to couple with bumps of the die. Other embodiments are also disclosed and claimed.

Abstract: Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while the appearance cracks and the warpage defects can be prevented.

Abstract: A semiconductor assembly (300) comprising a semiconductor device (301), which has a plurality of metallic contact pads (302) and an outline by sides (303). A metallic bump (304) made of reflowable metal is attached to each of these contact pads. An electrically insulating substrate (305) has a surface with a plurality of metallic terminal pads (306) in locations matching the locations of the device contact pads, and further a plurality of grooves (310) and humps (311) distributed between the terminal pad locations, complementing the distribution of the terminal pads. Each bump is further attached to its matching terminal pad, respectively; the device is thus interconnected with the substrate and spaced apart by a gap (320). Adherent polymeric material (330) containing inorganic fillers fills the gap substantially without voids.

Abstract: The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first line parts are formed on the first surface and are connected to the connection pads and the conductive vias, which pass through the substrate body. The second line parts are formed on the first surface and connect to the conductive vias. The third line parts are formed on the second surface and connect to the conductive vias. The second and third line parts are formed to have substantially the same length. The semiconductor package utilizes the above substrate for processing data at a high speed.

Abstract: A package includes a carrier, a first chip, a first dielectric layer and at least one first connecting part. The carrier has a first surface and a second surface, and at least one first pad is disposed on the second surface. The first chip is disposed on the first surface. The first dielectric layer is disposed on the first surface and covers the first chip. The first connecting part is disposed in the first dielectric layer and disposed around an edge of the first chip to electrically connect the first chip with the first pad. A package module of the package is also disclosed.

Abstract: Example embodiments of a semiconductor package are provided. In accordance with an example embodiment, a semiconductor package may include an external terminal connected to a concave surface of a bottom pad, wherein the bottom pad is recessed into a substrate. In accordance with another example embodiment, a semiconductor package may include at least one external terminal, a flexible substrate having a first surface with a plurality of convex portions and a second surface opposite the first surface having a plurality of concave portions, wherein the at least one terminal is recessed into the substrate and at least one of the concave portions surrounds a portion of the at least one external terminal.

Abstract: A semiconductor device includes a semiconductor chip, electrodes pads, first and second insulating layers, first and second conductive patterns and external terminals. The electrode pads are formed on a first area of a main surface of the semiconductor chip. The first insulating layer is formed on the first and second areas of the semiconductor chip and exposes the electrode pads. The first conductive pattern transfers a signal and is formed on the first insulating layer. A second insulating layer is formed on the first conductive pattern and the first insulating layer. The second conductive pattern is formed on the second insulating layer and provides a ground potential. The external terminals are formed on the first and second patterns at the second area.

Abstract: An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist openings, an electrically conducting layer (140, 440) in the solder resist openings over the finish layer, and a solder material (150, 810) in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.

Abstract: A flip chip mounting method which is applicable to the flip chip mounting of a next-generation LSI and high in productivity and reliability as well as a bump forming method are provided. After a resin 14 containing a solder powder 16 and a gas bubble generating agent is supplied to a space between a circuit board 21 having a plurality of connecting terminals 11 and a semiconductor chip 20 having a plurality of electrode terminals 12, the resin 14 is heated to generate gas bubbles 30 from the gas bubble generating agent contained in the resin 14. The resin 14 is pushed toward the outside of the generated gas bubbles 30 by the growth thereof and self-assembled between the connecting terminals 11 and the electrode terminals 12. By further heating the resin 14 and melting the solder powder 16 contained in the resin 14 self-assembled between the terminals, connectors 22 are formed between the terminals to complete a flip chip mounting body.

Abstract: A method and apparatus for packaging a semiconductor die with an interposer substrate. A semiconductor device assembly includes a conductively bumped semiconductor die and an interposer substrate having multiple recesses formed therein. The semiconductor die is mounted to the interposer substrate with the conductive bumps disposed in the multiple recesses so that an active surface of the semiconductor die is directly mounted to a facing surface of the interposer substrate. One or more openings may be provided in an opposing surface of the interposer substrate which extends to the multiple recesses and the conductive bumps disposed therein and dielectric filler material may be introduced through the one or more openings into the recesses.