Abstract: A plurality of microelectronic assemblies are made by severing an in-process unit including an upper substrate and lower substrate with microelectronic elements disposed between the substrates. In a further embodiment, a lead frame is joined to a substrate so that the leads project from this substrate. Lead frame is joined to a further substrate with one or more microelectronic elements disposed between the substrates.

Abstract: A multiple-chip-package (MCP) has multiple chip groups and multiple package terminal groups for electrical connections in the MCP. Semiconductor chips of the same chip group are electrically connected to the package terminals of the same package terminal group, while package terminals of different chip groups are electrically connected to the package terminals of different package terminal groups.

Abstract: A semiconductor device includes a wafer and a dicing saw tape that is laminated to a back surface of the wafer. An active surface of the wafer is opposite the back surface of the wafer. The semiconductor device further includes a lamination tape disposed in contact with the wafer. The lamination tape includes an under-film layer contacting the active surface of the wafer. The lamination tape further includes an adhesive layer contacting the under-film layer.

Abstract: Semiconductor device assemblies and systems that include at least one semiconductor device assembly include two or more semiconductor devices stacked one over another. Conductive pathways that extend around at least one side of at least one of the semiconductor devices provide electrical communication between conductive elements of the semiconductor devices, and optionally, a substrate. The conductive pathways may include self-supporting conductive leads or conductive traces carried by a substrate. Methods for forming semiconductor device assemblies having more than one semiconductor device include bending or wrapping at least one conductive pathway around a side of at least one semiconductor device and providing electrical communication between semiconductor devices of the assembly through the conductive pathways.

Abstract: In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC may be disposed between the substrate and the SFIC. The method includes making at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

Abstract: An integrated circuit structure includes a semiconductor substrate, and an active device formed at a front surface of the semiconductor substrate. A bond pad is over the front surface of the semiconductor substrate. The bond pad has a first dimension in a first direction parallel to the front surface of the semiconductor substrate. A bump ball is over the bond pad, wherein the bump ball has a diameter in the first direction, and wherein an enclosure of the first dimension and the diameter is greater than about ?1 ?m.

Abstract: A C4 grind tape and a laser-ablative adhesive layer are formed on a front side of a semiconductor substrate. A carrier substrate is thereafter attached to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, during which the carrier substrate provides mechanical support to enable thinning of the semiconductor substrate to a thickness of about 25 ?m. A film frame tape is attached to the back side of the thinned semiconductor substrate and the laser-ablative adhesive layer is ablated by laser, thereby dissociating the carrier substrate from the back side of the C4 grind tape. The assembly of the film frame tape, the thinned semiconductor substrate, and the C4 grind tape is diced. The C4 grind tape is irradiated by ultraviolet light to become less adhesive, and is subsequently removed.

Abstract: An insulative substrate includes a plurality of flexible retaining clips and a plurality of alignment and retaining pins. A metal leadframe includes a plurality of leads. Each lead terminates in a spring contact beam portion. The leadframe is attached to the substrate (for example, by fitting a hole in each lead over a corresponding alignment and retaining pin and then thermally deforming the pin to hold the lead in place). An integrated circuit is press-fit down through the retaining clips such that pads on the face side of the integrated circuit contact and compress the spring contact beams of the leads. After the press-fit step, the retaining clips hold the integrated circuit in place. The resulting assembly is encapsulated. In a cutting and bending step, the leads are singulated and formed to have a desired shape. The resulting low-cost package involves no wire-bonding and no flip-chip bond bump forming steps.

Abstract: A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive through hole vias (THV) are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.

Abstract: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Abstract: A semiconductor package includes a wiring board; a first electrode for external connection; a ball pad; a semiconductor chip; a mold resin; an electrode unit connected with the ball pad and penetrating the mold resin; and a second electrode for external connection connected with a portion of the electrode unit on a side of an outer surface of the mold resin. The electrode unit includes a first ball disposed on the ball pad; a second ball disposed between the first ball and the second electrode; and a solder material connecting between the ball pad and the first ball, between the first ball and the second ball, and between the second ball and the second electrode for external connection; each of the first ball and the second ball including a core part having a glass transition temperature which is higher than a melting point of the solder material.

Abstract: A packaged integrated circuit includes an integrated circuit and a package substrate. A trace in the package substrate includes a first portion and a second, high-inductance, portion. The high-inductance portion of the trace is proximate to a port of the integrated circuit and provides a selected inductance operating in cooperation with the capacitance of the port to reduce return loss from the port. The first portion of the trace is part of a transmission line having a characteristic impedance.

Abstract: An IC chip package, in one embodiment, may include an IC chip including an upper surface including an overhang extending beyond a sidewall of the IC chip, and underfill material about the sidewall and under the overhang. The overhang prevents underfill material from extending over an upper surface of the IC chip. In another embodiment, a ball grid array (BGA) is first mounted to landing pads on a lower of two joined IC chip packages. Since the BGA is formed on the lower IC chip package first, the BGA acts as a dam for the underfill material thereon. The underfill material extends about the respective IC chip and surrounds a bottom portion of a plurality of solder elements of the BGA and at least a portion of respective landing pads thereof.

Abstract: Adequate heat dissipation is essential for semiconductor devices. When a device exceeds a specified junction temperature, the device can be damaged, not perform correctly, or can have a reduced operating life. Semiconductor packages must dissipate heat from the chip to the external environment (i.e. to the PCB, air, etc) to keep the semiconductor device below a certain temperature threshold. For most devices, the most efficient way to dissipate the heat is through the package external I/O connections and into the PCB that it is mounted to. For Ball Grid Array (BGA) packages, the external I/Os are solder balls. Variable pitch packages pose advantages in heat dissipation without introducing significant costs.

Abstract: A method includes: mounting a plurality of semiconductor elements on a substrate having wirings; connecting electrically electrodes of the semiconductor elements and the wirings; sealing the semiconductor elements with a resin, which is carried out by bringing a thermal conductor having a concavity and the substrate to be in contact with each other so that the semiconductor elements are positioned within the concavity and by filling the concavity with the resin; and separating respective semiconductor elements 1. In the resin-sealing step, in a state where the thermal conductor is arranged with its concavity facing up and the concavity of the thermal conductor is filled with a liquid resin, the semiconductor elements are clipped in the liquid resin in the concavity and the liquid resin is solidified.

Abstract: An electronic multi-component package is assembled by placing multiple electronic components within multiple openings of a package substrate, then depositing and curing adhesive filler in gaps between the components and the inner peripheries of the openings. Circuit features, including conductive interconnects, are formed by thin-film photolithography over both front and back surfaces of the package substrate. Preformed conductive vias through the package substrate provide electrical connection between circuit features on opposite substrate surfaces. Additional electronic components may be attached to conductive lands on at least one side of the package. The circuit features also include contact pads for external package connections, such as in a ball-grid-array or equivalent structure.

Abstract: The present invention relates to a package and the method for making the same, and a stacked package. The method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice, and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned on the platforms during the reflow process, a die attach machine with low accuracy can achieve highly accurate placement.

Abstract: A semiconductor device comprising: a lower semiconductor package that comprises a first set of one or more semiconductor dies, an upper semiconductor package that is stacked on the lower semiconductor package, the upper semiconductor package comprises a second set of one or more semiconductor dies, and a first interconnect pad that is embedded in a top side of the lower semiconductor package to couple the upper semiconductor package to the lower semiconductor package.

Abstract: A semiconductor device includes a semiconductor package, a circuit board, an interconnection electrically connecting the semiconductor package and the circuit board, and a wiring structure. The wiring structure includes a through hole, a contact disposed at the through hole and a lead pattern extending from the contact. The wiring structure is disposed between the semiconductor package and the circuit board. The interconnection passes through the through hole and connects with the contact.

Abstract: A solder attach film includes a first cover film, a flux layer, a solder layer, and a second cover film, and it can be treated or kept in a roll shape. A solder ball forming method using the solder attach film includes preparing a semiconductor package or a semiconductor die, adhering the solder attach film, gridding, and reflowing. In the solder attach film adhering operation, the first cover film and the second cover film are removed, and the flux layer is adhered to electrically conductive pads of the semiconductor package or the semiconductor die. Subsequently, in the reflowing operation, the flux layer is volatilized and removed, and the solder layer is fused and fixed to the electrically conductive pads, so that solder balls are formed.

Abstract: A stack of semiconductor dies is disclosed. A first stack level includes a first semiconductor die and at least one first support that are attached to a substrate surface. A second level includes a second semiconductor die and at least one second support that are attached to the active surface of the first semiconductor die and to a coplanar surface of the first support(s). A third level includes a third semiconductor die attached to the active surface of the second semiconductor die and to a coplanar surface of the second support(s). The second and third semiconductor dies do not overlap bond pads of the first and second semiconductor dies, respectively. An adhesive film overlies the entire inactive surface of the second and third semiconductor dies, and attaches the second and third semiconductor dies to the immediately underlying active surface and support(s).

Abstract: The metallic bump is directly formed on a semiconductor wafer's I/O pad without UBM. First, a zinc layer is formed on the I/O pad or an anti-oxidation layer of the I/O pad is selectively etched off. Then, an isolative layer and a copper foil are arranged sequentially in this order above the I/O pad. The isolative layer is originally in a liquid state or in a temporarily solid state and later permanently solidified. Then, a via above the I/O pad is formed by removing part of the isolative layer and the cooper foil. Subsequently, A thin metallic layer connecting the copper foil and the I/O pad is formed in the via and a plating resist on the copper foil is formed. Then, a metallic bump is formed from the via whose height is controlled by the plating resist. Finally, the plating resist and the copper foil are removed.

Abstract: Stacked microelectronic dies employing die-to-die interconnects and associated systems and methods are disclosed herein. In one embodiment, a stacked system of microelectronic dies includes a first microelectronic die, a second microelectronic die attached to the first die, and a die-to-die interconnect electrically coupling the first die with the second die. The first die includes a back-side surface, a surface depression in the back-side surface, and a first metal contact located within the surface depression. The second die includes a front-side surface and a second metal contact located at the front-side surface and aligned with the first metal contact of the first die. The die-to-die interconnect electrically couples the first metal contact of the first die with the second metal contact of the second die and includes a flowable metal layer that at least partially fills the surface depression of the first die.

Abstract: A standing chip scale package is disclosed. The standing chip scale package provides electrical connection to bumped device contacts on both sides of the chip. The package is coupleable to a printed circuit board in a standing configuration such that front and back sides of the bumped chip are substantially perpendicular to a mounting surface. A process of fabricating the standing chip scale package is also disclosed.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a base conductive material on opposite sides of the base substrate; connecting an internal interconnect having a substantially spherical shape on the base substrate; forming a top substrate having a top conductive material on opposite sides of the top substrate with an upper component thereon facing the base substrate; and attaching the top substrate on the internal interconnect.

Abstract: A method for manufacturing an integrated circuit package system includes: providing a base device; attaching a base interconnect to the base device; applying an encapsulant over the base device and the base interconnect; and forming a re-routing film over the encapsulant, the base device, and the base interconnect for connectivity without a substrate.

Abstract: Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other.

Abstract: A semiconductor package includes a base substrate, a semiconductor chip mounted on the base substrate and including bonding pads, first and second connection terminals disposed adjacent to the semiconductor chip on the base substrate and electrically connected to the bonding pads, a first ball land disposed on the base substrate and electrically connected to the first connection terminal, a second ball land spaced apart from the connection terminals, the first ball land disposed between the second ball land and at least one of the first and second connection terminals, a first insulating layer covering the first ball land but exposing at least a part of the second ball land, and a first conductive wire extending onto the first insulating layer and connecting the second connection terminal to the second ball land.

Abstract: A manufacturing method of semiconductor package is provided. A carrier is provided. The chips are disposed on the carrier. The chips are encapsulated by a molding compound, so that the molding compound and the chips form a chip-redistribution encapsulant. The carrier is removed, so that the chip-redistribution encapsulant exposes the pads of the chips. The plasma is applied on the pads and the molding compound. A first dielectric layer is formed on the pads and the surface of the molding compound. The plasma is applied on a surface of the first dielectric layer. A patterned conductive layer is formed on the surface of the first dielectric layer. A second dielectric layer is formed on the patterned conductive layer and the first dielectric layer. A plurality of solder balls are formed on the second dielectric layer. The chip-redistribution encapsulant is divided so as to form a plurality of packages.

Abstract: There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.

Abstract: The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a plurality of vertical conductive walls and a BGA solder ball having an average diameter of greater than the width of the raised face, the BGA solder ball being adhered to the raised face and to a substantial portion of the vertical conductive walls.

Abstract: A semiconductor device is provided that includes a semiconductor chip, a plurality of solder bumps that electrically couple the semiconductor chip to the outside, and a metal bump being provided on the surface of each first solder bump which is at least a part of the plurality of solder bumps and being made of a metal having a melting point higher than that of the first solder bump. The wettability of the first solder bump is improved as each metal bump serves as a core when the corresponding first solder bump melts. Thus, the connection reliability of the first solder bump can be improved.

Abstract: Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.

Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 ?m. A plurality of traces are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.

Abstract: A semiconductor chip module including a plurality of semiconductor chips, each provided on the side face thereof with a part of connection terminals coupled with a circuit pattern formed on the front face, the chips being stacked and bonded. The stacked element in the lowermost layer is a semiconductor chip or an interposer dedicated for attachment to an external attachment board, and having a plurality of electrode elements (e.g., solder balls) arranged on a face on the attachment side, with each electrode element connected to any one of the connection terminals by a circuit pattern. Connection terminal portions on the side faces of the respective semiconductor chips and the stacked element in the lowermost layer are interconnected by a wiring pattern extending over the side faces.

Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12) on a wafer (10); a step of providing a resin later (14) as a stress relieving layer on the wafer (10), avoiding the electrodes (12); a step of forming a chromium layer (16) as wiring from electrodes (12) over the resin layer (14); and step of forming solder balls as external electrodes on the chromium layer (16) over the resin layer (14); and a step of cutting the wafer (10) into individual semiconductor chips; in the steps of forming the chromium layer (16) and solder balls, metal thin film fabrication technology is used during the wafer process.

Abstract: A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

Abstract: A semiconductor device of the invention includes a semiconductor substrate having a first insulating section formed on one surface thereof. A first conductive section is disposed on the one surface of the semiconductor substrate. A second insulating section is superimposed over the first insulating section and covers the first conductive section. A second conductive section is superimposed over the second insulating section. A third insulating section is disposed over the second insulating section and covers the second conductive section. These first conductive section, second insulating section, second conductive section, third insulating section, and terminal altogether constitute a structure. A third opening is formed between adjacent structures. The third opening is formed passing through the third and second insulating sections to expose the first insulating section.

Abstract: A semiconductor device includes an insulating substrate, a semiconductor chip, an insulating layer, and a sealing layer. The insulating substrate has an opening. A semiconductor chip is disposed in the opening. An insulating layer is disposed on a first surface of the insulating substrate. The insulating layer covers the opening. The sealing layer is disposed on a second surface of the insulating substrate. The sealing layer seals the semiconductor chip and the opening.

Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract: The semiconductor device comprises a semiconductor chip defining a first face and a second face opposite to the first face, the semiconductor chip comprising at least one contact element on the first face of the semiconductor chip, an encapsulating body encapsulating the semiconductor chip, the encapsulating body having a first face and a second face opposite to the first face, a redistribution layer extending over the semiconductor chip and the first face of the encapsulating body and containing a metallization layer comprising contact areas connected with the contact elements of the semiconductor chip, and an array of external contact elements located on the second phase of the encapsulating body.

Abstract: Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that has a large number of external connection terminals. The package substrate includes a slot, the external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The bonding finger arrangement includes a first bonding finger array, which is located at a close distance from the each longer side of the slot, and a second bonding finger array, which is located at a distance farther than the distance of the first bonding finger array from the each longer side of the slot. The central section of the bonding finger area includes at least the second bonding finger array, and the end sections of the bonding finger area includes the first bonding finger array.

Abstract: A chip scale package includes a patterned circuit layer attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive layer such that contact pads on a lower surface of the patterned circuit layer are electrically coupled to corresponding bonding pads on the semiconductor chip. The patterned circuit layer has a plurality of openings formed therein at locations corresponding to the contact pads such that each of the contact pads has a portion exposed from an upper surface of the patterned circuit layer through the corresponding opening. A plurality of metal bumps are respectively disposed in the openings and mounted to the exposed portions of the contact pads for making external electrical connection. The present invention further provides a method for manufacturing the chip scale package at the wafer-level.

Abstract: A package on package includes a lower semiconductor package including a plurality of stacked semiconductor chips, a connection portion including an electrically-conductive lead having a height lower than that of an encapsulation member, and an upper semiconductor package connected to the connection portion of the lower semiconductor package via a solder ball in a fan-in structure.

Abstract: An electronic package for containing at least a top packaging module vertically stacked on a bottom packaging module. Each of the packaging modules includes a semiconductor chip packaged and connected by via connectors and connectors disposed on a laminated board fabricated with a standard printed-circuit board process wherein the top and bottom packaging module further configured as a surface mountable modules for conveniently stacking and mounting to prearranged electrical contacts without using a leadframe. At least one of the top and bottom packaging modules is a multi-chip module (MCM) containing at least two semiconductor chips. At least one of the top and bottom packaging modules includes a ball grid array (BGA) for surface mounting onto the prearranged electrical contacts. At least one of the top and bottom packaging modules includes a plurality of solder bumps on one of the semiconductor chips for surface mounting onto the prearranged electrical contacts.

Abstract: A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free from encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.

Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.

Abstract: A semiconductor device, includes a package substrate having a first surface and a second surface opposite to the first surface, and a semiconductor element installed in the first surface of the package substrate. The package substrate includes a plurality of first land pads disposed in the first surface, second land pads disposed in the second surface and a second testing-dedicated pad disposed in the second surface.

Abstract: A first insulation film having a first opening is provided on an electrode pad of a semiconductor chip. A second insulation film having a second opening is provided on the first insulation film. A ground metallic layer which is to be in contact with the electrode pad via the first opening is provided on the first insulation film. A bump which is to be mechanically and electrically connected to the ground metallic layer is provided. Further, the above placement is made in a way that the ground metallic layer is provided in the second opening, and the ground metallic layer is provided on an inner side than an outer periphery of the electrode pad, covering the first opening.

Abstract: An electronic device comprises a device substrate, a plurality of compliant electrically-conductive balls, and a plurality of solder joints that couple the compliant electrically-conductive balls to the device substrate by a reflow process.