Abstract: A phase shift generation circuit has an edge detector for generating first and second edge signals indicating first and second edges of an input pulse signal. The circuit comprises a divide by N circuit that divides the frequency of a first clock signal by N. The circuit comprises a pulse counter, which receives the first edge signal and the second clock signal, and outputs a group of signals representing the number of the second clock pulses between occurrences of the first edge signal. The circuit has a first recycling timer that outputs a group of pulses as a uniformly spaced group across the period of the input pulse. The circuit also has a second recycling timer that outputs a group of pulses as a uniformly spaced group across the period of the input pulse. The first and second recycling timers are used to generate a phase shifted output pulse.

Abstract: A phase rotator based on voltage referencing is disclosed. A voltage signal is generated that is proportional to the phase difference between two input signals. The voltage signal is then used as the upper voltage limit for a digital-to-analog converter (DAC). The DAC is programmable via an input vector to generate a DAC output. The DAC output is used to generate a phase rotated (phase shifted) output, which is at an intermediate phase between the two input signals.

Abstract: A slew rate enhancing system includes first and second modules. The first module is configured to generate a first output signal in response to complementary first and second input signals. The second module is configured to generate a second output signal in response to the first and second input signals. The first module is configured to switch between tracking the first input signal and not tracking the first input signal during each half cycle of the first input signal based on values of the first input signal, the second input signal, and a predetermined threshold of the first module. The second module is configured to switch between tracking the first input signal and not tracking the second input signal during each half-cycle of the second input signal based on values of the first input signal, the second input signal, and a predetermined threshold of the second module.

Abstract: Systems, circuits and methods for phase-shifting pulse width modulated signal generation are disclosed. In some embodiments, a phase-shifting pulse width modulation circuit is configured to output pulses based on an input pulse width modulated signal. The pulses are staggered relative to one another, and can be received by a light-emitting diode driver for driving a light-emitting diode string at one or more time periods. The phase-shifting pulse width modulation circuit can include a counter-based programmable delay subcircuit consisting of two counter-based programmable delay blocks.

Abstract: A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

Abstract: A phase interpolation circuit includes a waveform shaping unit and a phase interpolator. The waveform shaping unit adaptively waveform-shapes first or second phase offset input clock signal pair that is applied, to output first and second buffered clock signals having a rising time and falling time each of more than about a quarter of a period of the first and second offset input clock signals. The phase interpolator is applied to generate a phase interpolation clock signal selected from phases between the first and second buffered clock signals in response to a weight value of a phase interpolation control signal.

Abstract: A phase shift generation circuit has an edge detector, which outputs a first and a second edge signal. The circuit also has a divide by N circuit, which receives a first clock signal and a group of signals representing a number N, and outputs a second clock signal. The circuit further comprises a pulse counter, which receives the first edge signal and the second clock signal, and outputs a group of signals representing the number of the second clock pulses between occurrences of the first edge signal. The circuit has first and second recycling timers, which output a group of pulses approximating a uniformly spaced group across the time duration of the period of the input pulse. The circuit also comprises at least one flip flop which generates a phase shifted output pulse.

Abstract: A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

Abstract: Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) and a second device (such as a memory component) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops, for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system.

Abstract: A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

Abstract: A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

Abstract: A third periodic signal is synthesized using a first output signal having a phase corresponding to a first periodic signal and a second output signal having a phase corresponding to the second periodic signal. A value of the third periodic signal is detected at a timing of the phase of the delayed first periodic signal. The value of the third periodic signal detected with the delayed first periodic signal is compared with the value of the third periodic signal detected by the first periodic signal delayed by the different delay amount. The delay amount is obtained for the detected third periodic signal being a maximum or a minimum. In a state of the optimum delay amount, an amplitude of the third periodic signal is adjusted so that the detected value of the third periodic signal falls within a predetermined range.

Abstract: A clock generator includes a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal. A first phase interpolation circuit has a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch. The first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals.

Abstract: One object is to provide a front-end module with a shared output terminal wherein an input impedance is readily matched and an insertion loss is suppressed. In accordance with one aspect, the front-end module 10 includes an input terminal, output terminals, a first filter circuit that passes signals in a first passband, a second filter circuit that passes signals in a second passband, a switch that is disposed between the input terminal and the first and second filter circuits and selectively connects the input terminal to the first and second filter circuits, and a matching circuit. The second filter circuit includes phase shifters.

Abstract: Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal.

Abstract: An interpolation circuit, includes a bias generating module, a load module consisting of a current source sub-module and a load resistance sub-module, first and second clock control modules, and an output module. The first clock control module includes a first input sub-module, a first source terminal negative feedback sub-module, a first multiplex switch sub-module and a first multiplex current sink sub-module. The bias generating module includes first, second and third FETs, and a bias current terminal. The current source sub-module includes fourth and fifth FETs. The load resistance sub-module includes first and second resistors. The first input sub-module includes sixth and seventh FETs. The first source terminal negative feedback sub-module includes a third resistor and a first capacitor. The first multiplex switch sub-module includes first and second groups of switches. The first multiplex current sink sub-module includes first and second groups of FETs. An interpolation system is further provided.

Abstract: An adjustable-frequency oscillator, is formed by two looped systems, functioning at the same frequency but the signals are phase shifted by 90°. Each looped system includes a phase shift device, an active element providing the gain and a resonator having a fixed phase-frequency characteristic. As the phase shift in each loop is imperatively a whole multiple of 2?, the phase shift added in each loop by the phase shift device entails that each resonator introduces a complementary phase shift to comply with the oscillation criterion. This complementary phase shift is produced at a frequency defined by the resonator, this then defining the frequency of oscillation. The frequency is adjusted by two phase shift stages, which carry out the analogue multiplication of the signals coming from the two looped systems by control voltages and the summing of these products.

Abstract: Methods, circuits, and apparatus for correcting the phase of a clock signal are presented. In one method, an operation is included for receiving, from a plurality of input lines, a plurality of input clock signals with respective input clock phases. The input clock phases form an ordered sequence of clock phases. The method further includes an operation for transmitting, over a plurality of output lines, a plurality of output clock signals with respective output clock phases. The input and output lines are coupled to a serially coupled ring of resistors, where each resistor in the ring has a terminal coupled to an input line and the other terminal coupled to an output line. Further, each output clock phase has a value that is between successive input clock phases of the ordered sequence of clock phases.

Abstract: A method and apparatus for a multiple lane transmission system that provides a fixed, low-latency mode of operation with reduced lane-lane skew while process, voltage, and temperature (PVT) variation, as well as other sources of variation, occur over time. Multiplexing techniques are utilized within each transmission lane to allow programmably adaptive use of phase alignment circuitry for various modes of operation. As a result, power consumption and semiconductor die area are reduced because multiple copies of phase alignment circuitry within each transmission lane are not required. Also, injection of additional jitter on the serial outputs due to continuous operation of phase alignment circuitry is prevented. Rather, multiplexers within the phase alignment circuitry selectively adapt the timing architecture to that required by the selected mode of operation.

Abstract: A third periodic signal is synthesized using a first output signal having a phase corresponding to a first periodic signal and a second output signal having a phase corresponding to the second periodic signal. A value of the third periodic signal is detected at a timing of the phase of the delayed first periodic signal. The value of the third periodic signal detected with the delayed first periodic signal is compared with the value of the third periodic signal detected by the first periodic signal delayed by the different delay amount. The delay amount is obtained for the detected third periodic signal being a maximum or a minimum. In a state of the optimum delay amount, an amplitude of the third periodic signal is adjusted so that the detected value of the third periodic signal falls within a predetermined range.

Abstract: Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

Abstract: A phase interpolation module comprising a first, second, and third phase interpolation units is proposed. Each of the first, second, and third phase interpolation units comprises a first through third inverters, a first and second resistors, wherein the first resistor is coupled between an output end of the first inverter and an input end of the third inverter, and the second resistor is coupled between an output end of the second inverter and the input end of the third inverter. The first and second inverters of the first phase interpolation unit receive a first signal, the first and second inverters of the third phase interpolation unit receive a second signal, and the first and second inverters of the second phase interpolation unit respectively receive the first and second signals.

Abstract: A signal control device controls the period of a three-phase signal used to control a three-phase high-voltage converter. An arithmetic unit of the signal control device determines a timing for changing the period for each phase so that the period of the signal for a V phase or a W phase is changed at the point when the phase difference between a U phase and the V or W phase reaches a prescribed phase difference after the period of the signal for the U phase has been changed. A control unit performs control such that the signal period for each phase is changed at the timing determined by the arithmetic unit.

Abstract: A 0-to-90-degree phase shifter (13) includes a voltage-variable power supply (16), a transistor (17), a 90-degree divider (18), gain-variable amplifiers (19) (19-1 and 19-2), and a combiner (20). The 90-degree divider (18) divides an input signal into a signal to which a 90-degree phase is given and a signal to which no phase is given, and outputs the divided signals to the gain-variable amplifiers (19). The gain-variable amplifiers (19) (19-1 and 19-2) output signals whose amplitudes are changed according to a phase control amount to the combiner (20). The combiner (20) combines the signals input from the two gain-variable amplifiers (19) and outputs the combined signal. The impedance between the source and the drain of the transistor connected to the isolation port of the 90-degree divider (18) can be changed as appropriate.

Abstract: To provide a power amplification device that can amplify an input signal having an envelope variation with high power-added efficiency in a wide frequency range, and a transmission device and a communication device using the power amplification device. A first orthogonal signal (Sd1) is generated by performing vector subtraction between first and second fundamental signals (Su1 and Su2) having the same amplitude and a phase difference ?? (0 degrees<??<180 degrees) therebetween. First and second fundamental signals are generated based on an input signal (Sin). A second orthogonal signal (Sd2) is generated by performing vector addition between the first and second fundamental signals (Su1 and Su2). First and second constant envelope signals (S1 and S2) are generated by performing vector addition between the second fundamental signal (Su2) and first and second constant envelope vector generation signals (e and ?e) obtained based on the first fundamental signal (Su1).

Abstract: Systems, circuits and methods for phase-shifting pulse width modulated signal generation are disclosed. In some embodiments, a phase-shifting pulse width modulation circuit is configured to output pulses based on an input pulse width modulated signal. The pulses are staggered relative to one another, and can be received by a light-emitting diode driver for driving a light-emitting diode string at one or more time periods. The phase-shifting pulse width modulation circuit can include a counter-based programmable delay subcircuit consisting of two counter-based programmable delay blocks.

Abstract: A time interpolator circuit increases the accuracy of digital counting circuits.

Abstract: In a phase excursion/carrier wave frequency excursion compensation device, increasing compensation processing speed using parallel processing deteriorates the transmission property.

Abstract: Circuits and systems for generating multiple frequencies are disclosed. In some embodiments, a circuit can include a first node, a second node, and a programmable phase rotator. The first node can receive a first signal having frequency f1, and the second node can output a second signal having frequency f2 that is different from f1. In some embodiments, a frequency divider can generate a third signal having frequency f3 based on the second signal. In some embodiments, a frequency divider can generate the first signal based on a reference signal having frequency f4. The programmable phase rotator can be capable of updating, at an update frequency that is substantially equal to f1 and/or f4, a phase difference between the first signal and the second signal. In some embodiments, the circuit can be part of a USB (Universal Serial Bus) 3.0 physical layer (PHY) circuit.

Abstract: A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; and a control that influences a delay associated with the data delay line and the remote clock delay line.

Abstract: A phase interpolator circuit includes first and second transistors coupled to form a differential pair, a load circuit, a first set of switch circuits, a second set of switch circuits, and a current source. The first set of switch circuits are coupled between the first transistor and the load circuit. The second set of switch circuits are coupled between the second transistor and the load circuit. The current source provides current for the differential pair.

Abstract: Systems and methods are disclosed for improving the accuracy of phase spacing of multiphase clocks. In one example, method includes receiving a reference clock having a first frequency and sampling the reference clock with a plurality of multiphase clocks having a second frequency to generate a plurality of samples. The second frequency is a non-integer multiple of the first frequency. The method also includes detecting transitions of the reference clock occurring between the samples generated from a plurality of pairs of the multiphase clocks and counting the transitions to generate a transition count for each pair of the multiphase clocks. The method also includes summing a set of the transition counts to generate a measured phase for a first multiphase clock, calculating a reference phase for the first multiphase clock, and generating a phase skew value for the first multiphase clock based on the measured phase and the reference phase.

Abstract: A stabilized quadrature RC/CR phase shifting network for generating quadrature RF and microwave signals. The network uses offset biasing of postamplifiers following the phaseshifter to fine tune quadrature-phase, and further uses an output quadrature-phase detector to stabilize quadrature-phase with negative feedback by using the quadrature-phase error signal to drive the quadrature-phase fine tuning control. In an alternative embodiment, the stability of quadrature-phase can be enhanced without the output quadrature-phase detector by making the quadrature-phase fine tuning control dependent upon the amplitude-difference negative feedback error signal.

Abstract: A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in a clock tree circuit, wiring the clock tree circuit in which the first clock distribution circuit is disposed, verifying timing of the wired clock tree circuit, and replacing the first distribution element by a second clock distribution circuit based on a result of the timing verification, the second clock distribution circuit having roughly a same input load capacitance as the first clock distribution circuit and a different delay value from the first clock distribution circuit.

Abstract: In at least one example embodiment, a phase signal generating apparatus includes a phase signal generator and phase controller. The phase signal generator is configured to receive a plurality of first phase signals and a plurality of second phase signals, adjust a phase difference between the plurality of first phase signals and the plurality of second phase signals and generate a plurality of adjusted first phase signals and a plurality of adjusted second phase signals, based on a switch control signal and a phase control signal, a phase difference between the plurality of adjusted first phase signals and the plurality of adjusted second phase signals being the adjusted phase difference. The phase controller is configured to generate the switch control signal and the phase control signal based on phase information for the plurality of first phase signals and the plurality of second phase signals.

Abstract: Systems and methods are disclosed for precise generation of phase variation in digital signals. The disclosed signal generation embodiments generate a pattern of information bits that represents a digital signal with desired phase variations and transmit this digital pattern at high speed utilizing a serializer to generate a high speed bit stream. The high speed bit stream can be used to generate one or more digital signals, such as clock signals, having desired rates and desired phase variations. In certain embodiments, the desired phase variation can be introduced into the resulting digital signal by removing and/or inserting bits in a digital pattern thereby moving logic transitions (e.g., rising edge transitions, falling edge transitions) as desired within the resulting digital signal. In addition to clock signals, the resulting digital signals generated can be control signals, data signals and/or any other desired digital signal.

Abstract: In a case where two constant envelope signals corresponding to an input signal are generated through analog signal processing, variation in detection sensitivities of amplitudes of those signals is suppressed. At least one of a mixer (24) for detecting an amplitude of a first intermediate signal S1 and a mixer (26) for detecting an amplitude of a second intermediate signal S2 detects an amplitude of a given reference signal, and sampling hold circuits (36, 38) hold a voltage related to those amplitudes. Then, detection sensitivities of the mixer (24, 26) are corrected based on the held voltage.

Abstract: A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain.

Abstract: An interpolation circuit for comparing an input voltage signal with an interpolated reference signal derived from a first reference voltage signal and a second reference voltage signal may include a transconductive circuit configured to generate a first differential current signal proportional to a difference between the first reference voltage signal and the input voltage signal and a second differential current signal proportional to a difference between the second reference voltage signal and the input voltage signal, an intermediate circuit configured to generate a third differential current signal, and a transinductive circuit configured to generate an output voltage signal having a first polarity if a value of the input voltage signal is greater than a value of the interpolated reference signal and a second polarity if the value of the input signal is less than the value of the interpolated reference signal.

Abstract: Two selected testing selectors output testing input signals of reverse phases from each other according to the first control signal. Two selectors corresponding to the two testing selectors output the testing input signals output from the two testing selectors according to the second control signal. Two mixers corresponding to the two selectors output an output signal in which weighting is added to the testing input signals output from the two selectors are compounded. A detection circuit outputs an error signal when the output signal output from the two mixers is larger than a threshold value.

Abstract: An electronic circuit for distributing a clock signal to several clock destinations includes phase adjustment circuits for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal receive from the respective one of the clock destinations; phase detectors for detecting a phase shift of the clock signal at the respective one of the clock destinations according to a nearest neighbor clock destination; loop filters for generating and transmitting respective DC voltage feedback signals; current sources, each configured to receive the respective DC voltage feedback signal and output a respective current to a respective one of the phase adjustment circuits according to said respective DC voltage feedback signals to adjust the phase shift of the clock signal for the respective one of the clock destinations.

Abstract: An inter-phase skew detection circuit includes a frequency division circuit that frequency-divides N-phase clocks to be measured at predetermined timings so as to generate N+2 frequency-divided clocks; a phase comparison target clock generation circuit that generates N phase comparison target clocks by using predetermined N frequency-divided clocks among the N+2 frequency-divided clocks; a phase comparison reference clock generation circuit that generates N reference clocks by using the N+2 frequency-divided clocks, in accordance with predetermined combinations between the N+2 frequency-divided clocks and an operation criterion; and a phase comparison circuit that detects respective phase differences between the N phase comparison target clocks and the corresponding N reference clocks.

Abstract: Disclosed are a device and a method for comparing a detected frequency signal (first frequency signal) and a second frequency signal which is obtained by delaying the detected frequency, to determine whether the frequency transitioned to a predetermined area on high frequency side or reached a predetermined value on the upward direction side. The frequency detection device (1) comprises: a delayed signal output circuit (11) that outputs a second frequency signal (F2) obtained by delaying the first frequency signal (F1), which has a frequency that changes over time, by a set period (?i); and a determination circuit (12), which inputs the first frequency signal (F1) and the second frequency signal (F2), determines whether or not the cycle of the first frequency signal (F1) is included in the cycle of the second frequency signal (F2) and/or whether or not the cycle of the second frequency signal (F2) is included in the cycle of the first frequency signal (F1), and outputs a determination signal.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A phase detection system (100) comprises an input terminal (101), first and second peak detectors (103, 113), an averaging unit (107), an offset unit (122), and a comparator (126). Input terminal (101) is coupled to the first and to the second peak detectors (103, 113) and provides an input signal to phase detection system (100). Averaging unit (107) is coupled between offset unit (122) and both the first peak detector and the second peak detector (103, 113), and generates an intermediate signal. Offset unit (122) is coupled to input terminal (101) and generates two comparable signals by applying a predetermined offset in signal strength to the input signal or the intermediate signal. The comparator (126) is coupled to the offset unit (122) and generates an output signal by comparing the two comparable signals which is indicative of the phase of the input signal.

Abstract: A method of communicating with a source synchronous device can include determining an expected number of pulses of a strobe signal to be received in response to a first read request directed to the source synchronous device and receiving the strobe signal from the source synchronous device. Pulses in the strobe signal can be counted. Responsive to detecting a last pulse of the expected number of pulses of the strobe signal, the strobe signal can be replaced with a reference signal that is phase and frequency aligned with the strobe signal.

Abstract: A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal.

Abstract: This invention deals with an advanced Real-time Grid Monitoring System (RTGMS) suitable for both single-phase and three-phase electric power systems. This invention provides an essential signal processing block to be used as a part of complex systems either focused on supervising and diagnosing power systems or devoted to control power processors interacting with the grid. This invention is based on a new algorithm very suitable for real-time characterization of the grid variables under distorted and unbalanced grid conditions. The main characteristic of this invention is the usage of a frequency-locked loop, based on detecting the grid frequency, for synchronizing to the grid variables. It results in a very robust system response in relation to existing technique based on the phase-angle detection since grid frequency is much more stable variable than the grid voltage/current phase-angle, mainly during grid faults.

Abstract: A first signal processor performs predetermined signal processing on an input signal to provide a change to at least one of the characteristic values thereof. A second signal processor is provided in the subsequent stage of the first signal processor and performs predetermined signal processing on an output signal from the first signal processor to provide a change to a characteristic value thereof. An amount of change provided to the characteristic value of the signal by the second signal processor is dependent on a power supply voltage. An amount of change provided to the characteristic value of the signal by the first signal processor is configured to be adjustable. A control circuit monitors a power supply voltage supplied to the second signal processor and adjusts in accordance with the power supply voltage the amount of change provided to the characteristic value of the signal by the first signal processor.