Abstract: A voltage controlled delay line having a plurality of delay cells is used to delay a first reference clock by a predetermined delay time to generate an in-phase first delay clock and to delay a second reference clock by the predetermined delay time to generate an in-phase second delay clock. Each delay cell has a first input port, a second input port, a first output port, and a second output port. The first output port of one delay cell and the second input port of another one delay cell having the same phase are electrically connected or the second output port of one delay cell and the first input port of another one delay cell having the same phase are electrically connected so that the first and second input port of each delay cell are not connected to the first and second output port of an adjacent delay cell.

Abstract: Non-iterative introduction of phase delay into a signal, without feedback, is disclosed. A system of one embodiment of the invention includes a controller and a mechanism. The controller provides a pulse having a length representative of a phase delay for introduction into a signal. The mechanism non-iteratively introduces the phase delay into the signal based on the pulse, without feedback.

Abstract: A clock edge placement circuit for implementing source synchronous communication between integrated circuit devices. The clock edge placement circuit includes a delay line having an input to receive a clock signal from an external clock source. A corresponding output is included to provide the clock signal to external logic elements. The delay line structure adapted to add a propagation delay to the input, wherein the propagation delay is sized such that the phase of the clock signal is adjusted to control synchronous sampling by the external logic elements. The delay line is adapted to dynamically adjust the delay such that the phase of the clock signal at the output remains adjusted to control synchronous sampling by the external logic as variables affecting the phase of the clock signal change over time. A series of taps are included within the delay line. The delay line uses the series of taps to add a variable delay for adjusting the phase of the clock signal.

Abstract: A system and method of implementing precision time delays that provides important and novel improvements over prior techniques of implementing time delays by utilizing a new strategy for selecting the values in the sine and cosine lookup tables. Sine and cosine values which result in non-uniform amplitudes enable increased overall accuracy with fewer bits communicated from the look-up tables to the analogue portion of the system. Further, herein is provided the addition of a variable amplitude threshold crossing capability following the combining of the sine and cosine signals. The time delay accuracy of the resulting phase and amplitude hybrid system can be improved either by increasing the number of bits in the sine/cosine phase management section or by increasing the number of bits in the amplitude section. There is provided herein an optimum strategy for choosing the number of bits used in the phase and amplitude sections for the best overall delay accuracy with the fewest overall control bits.

Abstract: An integrated circuit has a timing circuit with a power source and a capacitor. The timing circuit outputs an output signal whose time can be adjusted and which has a switching time delayed with respect to a reference time. A control signal output by a drive circuit is connected to the timing circuit for adjustment of the output signal with regard to the switching time. The output signal from the timing circuit is connected to the drive circuit for assessment of the output signal with regard to the switching time. The operation of the timing circuit can thus be adjusted independently of process fluctuations during the production of the integrated circuit.

Abstract: A transmitter pre-driver utilizing discrete-time charge sharing between multiple capacitors to create intermediate voltages. The intermediate voltages are fed into an output driver to produce Class AB and Class A output current flow.

Abstract: A timing signal generating circuit receives multiphase input signals and generates a signal having a phase intermediate therebetween, and weighting is applied to the multi-phase input signals by using a variable impedance circuit. The timing signal generating circuit (receiver circuit) can operate with a low supply voltage, is simple in configuration, and can generate timing signals with high accuracy.

Abstract: An apparatus comprising a first calibration circuit and a phase shift network stage. The first calibration circuit may be configured to generate a control signal. The phase shift network stage may comprise one or more tunable phase shift elements and be configured to provide a tunable impedance. The phase shift network stage may be tuned in response to the control signal and a conductance of the tunable phase shift elements.

Abstract: An additional clock is delayed from a master clock by 90 degrees to provide needed additional clock edges during a cycle. The need for the additional clock edges arises from the desire to perform a read and a write in the same clock cycle. The precise delay is achieved through a clock programmable delay that can be updated as the frequency of the master clock may change. The amount of delay is conveniently detected by using two other programmable delays to achieve a 180 degree delay. The 180 degree delay is easily detected using a flip-flop. The programming signal that caused the total of 180 degrees of delay caused 90 degrees per programmable delay. The same programming signal is then coupled to the clock programmable delay to achieve the desired 90 degrees of delay for the additional clock.

Abstract: The digital phase control circuit of the present invention is provided with: voltage-controlled delay line VCDL1 in which differential buffers (G1-G10) having a propagation delay time of 160 ps are concatenated in a plurality of stages; voltage-controlled delay line (VCDL2) in which differential buffers (H1-H8) having a propagation delay time of 200 ps are concatenated in a plurality of stages; selector (S2) that extracts a clock signal from any stage of voltage-controlled delay line (VCDL1) and outputs to the first stage of voltage-controlled delay line (VCDL2); and selector S3 that extracts and outputs a clock signal from any stage of voltage-controlled delay line (VCDL2).

Abstract: Structures and methods for CMOS voltage controlled phase shift oscillators are provided. The CMOS voltage controlled phase shift oscillators, or phase shift circuit, includes any odd number of stages coupled in series. Each stage includes a CMOS amplifier. A phase shift network is coupled to the CMOS amplifier. The CMOS amplifier provides a gain and allows a small phase shift in each stage to eventually provide a signal which is 180 degrees out of phase with the input signal. In the CMOS amplifier, the PMOS transistor is a diode connected PMOS transistor which acts as a low valued load resistance. In the phase shift network, an NMOS transistor is used as a voltage variable resistor for providing a resistance value in the circuit.

Abstract: A circuit, for use in a delay locked loop, provides a phase-shifted output relative to a first signal. The circuit includes plural current sources, current source switches that are selectable to transmit varying amounts of current from the plural current sources, and input switches that receive current via the current source switches and provide the phase-shifted output. The output switches include a first switch for receiving the first signal and a second switch for receiving a second signal phase-shifted from the first signal. The phase-shifted output relative to the first signal is based on an amount of current that passes through each input switch.

Abstract: A phase stable clock circuit includes a phase gate having track-and-hold (T/H) circuits with each T/H circuit receiving a phase shifted continuous sinusoidal signal of predetermined phase and a control input signal to capture and hold phase samples of the sinusoidal signals. In alternative embodiments, a phase correction circuit provides phase correction values that are added to the held phase values to generate corrected phase values and time-error phase lookup table is used to generate time position correction values. The corrected phase values are applied to the phase gate remove deterministic phase errors to generate an output signal with a predetermined startup phase relative to the control input signal transition. The phase error-to-time lookup table adjusts the time placement of waveform record samples after the acquisition of the samples.

Abstract: A source (20) provides an input signal (S1) to be phase shifted and a combining circuit (24) concurrently combines first (A), second (B) and third (C) intermediate signals derived from the input signal (S1), and having differing phase shifts (0, −45, +135 deg), to form a phase shifted output signal (S2). A first amplitude controller (34, 38, 30, 32), responsive to a phase control signal (S3) supplied thereto, varies the amplitudes of the second (B) and third (C) intermediate signals in opposite directions (38) for controlling the phase of the phase shifted output signal. Additionally, a further amplitude controller (40, 42) is provided for reducing a tendency for variations in the phase shift control signal (S3) to alter the amplitude of alternating current (FIG. 5) and direct current (FIG. 6) components of the phase shifted output signal (S2).

Abstract: An apparatus and method for adjusting the phase of an output digital signal while maintaining the symmetry of the input signal. The apparatus includes an input waveform signal and a comparator having a positive feedback path to an input and an output. An adjustable resistor is connected along the positive feedback path to the output of the comparator and to the positive input of the comparator. The apparatus produces an output waveform signal shifted in phase from the input waveform signal with the same duty cycle as the input waveform signal.

Abstract: A multiphase clock generator includes oscillator, selector circuit and frequency divider circuit. The oscillator generates a first multiphase clock having a first phase difference. The selector circuit receives the first multiphase clock from the oscillator and outputs a second multiphase clock including a plurality of clock signals. In the second multiphase clock, the phase of each clock signal is shifted from that of the previous one by a second phase difference. The second phase difference is n times as long as the first phase difference, where n is a predetermined positive integer. And the frequency divider circuit receives the second multiphase clock from the selector circuit, divides the frequency of the second multiphase clock by a predetermined number and then outputs a group of clock signals with the divided frequency as a third multiphase clock.

Abstract: An apparatus and method for an improved hardware implementation of a digital phase shifter which provides a simplified process for phase correction of digital signals and eliminates the use of a lookup ROM and complex digital Multipliers. The digital phase shifter operates by applying a phase correction to complex digital I/Q samples in separate stages, where each stage performs a phase rotation by an amount specified directly by the binary values of an integer input phase. In one aspect, an apparatus for applying a phase shift to a complex digital signal comprises a plurality of phase shift stages each having a phase shift value associated therewith, whereby each of the plurality of phase shift stages selectively applies the corresponding phase shift value to the complex digital signal.

Abstract: A delay-locked loop (DLL) circuit having a master-slave structure wherein the DLL circuit includes a master delay loop and a slave stage. The master delay loop delays an external clock signal by a predetermined delay time and generates a feedback signal which is phase-synchronized with the external clock signal. The slave stage delays the external clock signal by the predetermined delay time and generates an internal clock signal. The master delay loop includes a phase comparator, a delay controller, a delay part and a compensation delay part. The slave stage includes a low-pass filter and a slave delay part. The master delay loop may have a structure in which a plurality of delay parts are connected in series. According to the DLL circuit, the high frequency phase noise of the internal clock signal can be minimized in a locked state.

Abstract: A sampling clock generation circuit and a data transfer control device make it possible to ensure a set-up time and the like during sampling, while maintaining a high frequency. A sampling clock generation circuit comprises an edge detection circuit detecting between which two edges an edge of data DIN (data to be transferred in USB 2.0 HS mode) is located, the two edges are among edges of clocks CLK0 to CLK4 that have the same frequency but mutually different phases, and a clock selection circuit, which selects one of CLK0 to CLK4 based on this edge detection information and outputs the thus-selected clock as a sampling clock SCLK. When the set-up time of a D flip-flop of the edge detection circuit is TS, the hold time is TH, and the period of the clock is T, N which is the number of a multi-phase clock is given by: N≦[T/(TS +TH)] (where [X] is the maximum integer that does not exceed X).

Abstract: In simultaneous transmission of a signal using plural transmission lines, a synchronous cycle is set, plural signals A, B, C and D are simultaneously transmitted to the plural transmission lines, and the plural signals A through D transmitted through the plural transmission lines are received. Delay times &tgr;A, &tgr;B, &tgr;C and &tgr;D of the plural signals received in the synchronous cycle are detected, and the delay times of the transmission lines are adjusted on the basis of these detected delay times so that the simultaneously output signals A through D can be simultaneously received after passing through the plural transmission lines. Accordingly, even when a delay time between signals is long with a phase shift exceeding one cycle of a clock signal, the phase shift between the signals can be adjusted to be within one cycle.

Abstract: A skew correction apparatus for increasing the data transfer capacity and thus improving the system performance, by making it possible to carry out the deskew work even during the data transfer, is disclosed. The skew correction apparatus receives a plurality of serial data in synchronism, and reduces the skew mount constituting a phase shift between the serial data. A first correction unit (31) detects a skew between the serial data and corrects the skew during the idle time. A second skew correction unit (32) detects a skew between the serial data and corrects the skew during the data transmission.

Abstract: Phase locked loop integrated circuits include a phase detection circuit, a variable delay device and a delay control circuit. The variable delay device and delay control circuit provide improved characteristics by increasing the signal frequency bandwidth of the delay locked loop integrated circuit in a preferred manner. The phase detection circuit is configured to perform the functions of comparing first and second periodic signals and generating a phase control signal (e.g., VCON) having a first property (e.g., magnitude) that is proportional to a difference in phase between the first and second periodic signals. The delay control circuit is responsive to the phase control signal VCON and generates a delay control signal that is provided to the variable delay device. The delay control circuit may comprise a counter, a first comparator, a second comparator and a shift register. The variable delay device includes a variable delay line and a compensation delay device.

Abstract: A system (50) has a shifting delay circuit (60) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (70) which includes a delay line (72) which provides a variable delay for delaying the source clock. The delay line (18) has its delay varied by a counter (74). The counter (74) is incremented in order to change the delay. The shifting delay circuit (60) is based on half periods of a reference clock (GCLK) which has a known relationship to the source clock. The total delay for the source clock is a combination of that provided by shifting delay circuit (60) and delay line (72). The delay line (72), which requires relatively large amounts of die area in an integrated circuit can be smaller in size due to the usage of shifting delay circuit (60).

Abstract: A filter includes an FET and a capacitor in a phase shift network wherein the FET operates as a variable resistor. An impedance multiplier is coupled to the FET for increasing the range of resistance of the FET.

Abstract: A semiconductor integrated circuit device includes a first delay circuit delaying a first clock signal, a second delay circuit delaying a second clock signal which has an inverted phase with respect to the first clock signal, a phase comparator outputting a phase error signal based on a comparison of the first clock signal and a feedback signal corresponding to an output signal from the first delay circuit, a delay control circuit generating a delay control signal based on the phase error signal, for variably controlling a delay quantity of the first and second delay circuits, and a timing adjusting circuit variably controlling a delay quantity of the second delay circuit by supplying the delay control signal to the second delay circuit at a timing synchronized to the second clock signal.

Abstract: A synchronous integrated circuit clock circuit is disclosed. The clock circuit (200) receives a system clock (CLKX) and in response thereto, generates an internal clock (CLKI) that is shifted forward in phase with respect to the system clock signal (CLKX). The amount by which the internal clock (CLKI) is shifted remains relatively constant over a range of system clock (CLKX) frequencies. The clock circuit (200) includes a measuring section (202) that measures the period of the system clock (CLKX), a logic section (204) that determines a delay value based upon the duration of the system clock (CLKX) period, and a generation section (206), that provides the internal clock signal (CLKI).

Abstract: A variable phase shifting circuit includes a resistance unit and a variable capacitance unit. The resistance unit includes at least one resistor element. The resistance unit input a first signal and a second signal and also output a third signal and a fourth signal. The variable capacitance unit includes two base-to-emitter capacitors of two transistors. The variable capacitance unit is connected to the third signal and the fourth signal. The two base-to-emitter capacitors is varied by controlling collector currents of the two transistors. The third signal and the fourth signal are produced by shifting phases of the first and second signals based on the at least one resistor element and the two base-to-emitter capacitors.

Abstract: A semiconductor device has a DLL circuit or the like for adjusting the phase of an external clock and producing an internal clock that lags behind by a given phase. The semiconductor device further includes a clock frequency judging unit for judging the frequency of a first clock on the basis of an indication signal indicating a delay value of the first clock in the DLL circuit or the like to output a control signal; and a clock selecting unit for selecting either one of the first clock and the second clock, in response to the control signal.

Abstract: A circuit and method for selectively and dynamically delaying a signal is presented. A series of delay modules are used to provide progressively finer delays. A multiplexer is used after each delay module to select one of a plurality of signals to pass on to a subsequent delay module. Each multiplexer is controlled by a control signal which can vary in time so that different delays can be selected for different portions of the signal to be delayed. By providing the proper control signals to the multiplexers any delay corresponding to a sum of the available individual delays generated by the individual delay modules is possible. The circuit and method are particularly useful for imposing individual delay times on the pulses in a logic level signal.

Abstract: A semiconductor integrated circuit comprises a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls the first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit is correspondent to the frequency of the reference clock signal.

Abstract: A PLL circuit including a delay circuit which delays an output of one of inverters constituting a VCO by an amount designated externally via a delay control circuit. An operational circuit carries out logical operation between the output of the delay circuit and an output of the final stage inverter of the inverters, and outputs a second clock signal whose duty differs from that of a first clock signal output from a buffer circuit. The two clock signals are supplied to flip-flop circuits of different circuit blocks so as to prevent malfunction of these flip-flop circuits.

Abstract: A system (50) has a shifting delay circuit (60) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (70) which includes a delay line (72) which provides a variable delay for delaying the source clock. The delay line (18) has its delay varied by a counter (74). The counter (74) is incremented in order to change the delay. The shifting delay circuit (60) is based on half periods of a reference clock (GCLK) which has a known relationship to the source clock. The total delay for the source clock is a combination of that provided by shifting delay circuit (60) and delay line (72). The delay line (72), which requires relatively large amounts of die area in an integrated circuit can be smaller in size due to the usage of shifting delay circuit (60).

Abstract: A circuit and method are provided wherein a receiver receives an input train of pulses. The circuit includes a delay-locked-loop coupled to an output of the receiver. The delay-locked-loop includes a pulse generator responsive to received input train of pulses produced at the output of the receiver for producing first pulses in response to the leading edges of the received input train of pulses and second pulses in response to the trailing edges of received input train of pulses. The leading edge of the first pulse has the same edge type as the leading edge of the second pulse (i.e., the leading edge of the first pulse and the leading edge of the second pulse are either both rising edge types or both falling edges types). The first pulses and the second pulses are combined into a composite input signal comprising the first and second pulses with the leading edge of the first pulse maintaining the same edge type.

Abstract: By disposing the first filter circuit and the second filter circuit whose connection structures are the same and whose element values are different on an integrated circuit, a phase shifter with output signals whose frequency characteristics and errors of phase shift characteristics equally vary can be accomplished.

Abstract: The present invention is a method and an apparatus for measuring phase differences between signals A and B using an absolute voltage value for each phase difference between .+-.180.degree.. This is accomplished using a third signal C, which is a signal having a phase approximately equal to the average phase between signals A and B. Signals C and A are subsequently amplitude limited and mixed to produce a fourth signal D, which is a signal having associated an absolute voltage value for each degree of phase difference between .+-.180.degree. for signals A and B.

Abstract: A phase shifter circuit shifts the phase of a voltage varying RF signal at high RF power levels by using a diode arrangement of back to back diode sets connected in series to reduce the change in capacitive reactance of the diode arrangement. The diode arrangement is connected to a phase adjustment port of a phase shifting device which shifts the phase of the RF signal according to the capacitive reactance level at the phase adjustment port. A control circuit for each back to back diode set can be used to provide independent adjustment of each diode set to balance capacitive reactance responses between the diode sets to further reduce the change in capacitive reactance. In certain embodiments, the phase shifter circuit uses a ninely (90) degree hybrid coupler with two phase adjustment ports, a zero (0) degree port and a -90 degree port.

Abstract: A variable phase shift network (420) for a phase quadrature signal generator (320, 370) includes a variable current controller (909), a first NPN transistor (801) and a second NPN transistor (802). The variable phase shift network (420) produces a first quadrature input signal (830), a second quadrature input signal (834), a first quadrature output signal (821) and a second quadrature output signal (826) responsive to receiving a first differential input signal (919) and a second differential input signal (925).

Abstract: The circuit arrangement for generating two signals staggered in time from a clock signal and for measuring their time stagger receives at its input a clock signal, from which it generates an undelayed signal and a signal delayed relative to the undelayed signal. The generated signals appear at a first and second output of the circuit arrangement, respectively. A delay time measuring arrangement comprises a reversible inverter connected between the input of the circuit arrangement and the first output of the circuit arrangement and a NAND gate. The NAND gate receives at one input the delayed signal and at the other input the output signal of the inverter and furnishes an output signal from which the time stagger existing between the undelayed signal and the delayed signal can be precisely determined. The reversible inverter is switchable by a switching signal between a non-inverting condition in a working phase and an inverting condition in a measuring phase.

Abstract: A CML/ECL clock phase shifter device provides a 360.degree. phase control range and, upon being provided with two CML clock signals related by a known phase difference, the device produces any desired phase in response to a control signal. The device uses a CMOS current switch which generates current signals having the amplitude adjustable with the control signal, which is a digital word. Differential pairs provide amplitude modulated current signals for the input clock and the variant of the input clock. Two MOS transmission networks selectively invert each amplitude modulated signal and sum the signals from each side on a load network. The phase control resolution is optimal over four quadrants for quadrature input clock signals.

Abstract: The present invention relates to a voltage-controlled phase shifter including two differential stages, each including a biasing branch and output branches coupled with the output branches of the other stage; two first resistors coupling the output branches to a first supply potential; a first capacitor connected between the output branches; two second resistors connected in series between the biasing branches; a second capacitor connected in series between the two second resistors; means for applying an input signal in the form of a differential current across the second capacitor; and means for supplying, as an output signal, the sum of the current in one of the first resistors and of a predetermined fraction of a corresponding component of the differential current constituting the input signal.

Abstract: A waveshaping circuit, which includes a controller and current summing circuitry controlled by the controller. The controller receives a binary data signal and generates a different set of control signals in response to each of at least two bit patterns of the data signal. The current summing circuitry selectively sinks combinations of component currents in response to sequences of the control signal sets to generates an output current signal having a desired waveform. The current summing circuit can be controlled to operate in a two-stage cycle: a first stage generating a first partial current signal whose waveform determines a first portion of the transmit waveform of the output signal, and a second stage generating a second partial current signal whose waveform determines a second portion of such transmit waveform.

Abstract: A clock timing recovery circuit for recovering the clock timing from a baseband signal obtained by detection of a received signal. The clock timing is rapidly established using a clock signal which has been phase-shifted from the desired clock timing to sample the baseband signal, and by obtaining the optimum phase from the sampled signal obtained as a result. A clock-timing recovery circuit according to this invention does not require oversampling and provides easy optimization of circuit constants.

Abstract: A voltage controlled delay circuit is formed by m number of gates connected in series, phases of a clock signal and a delay signal are compared by a phase comparator, an up signal or a down signal is output, an integrated signal is generated by an integrator, a voltage signal following this is generated by a buffer and fed back as an operating power source voltage to the voltage controlled delay circuit, and further an internal power source voltage following the voltage signal is generated by a buffer and a pMOS transistor, therefore the internal power source voltage of the required lowest limit can be supplied in response to the frequency of the clock and a reduction of the voltage and conservation of the electric power of the LSI circuit can be achieved.

Abstract: A timing generating circuit formed as an LSI of CMOS.FETs is provided which enables correction of the variations of delay amount caused by the heat generated in the CMOS.FETs due to the propagation of pulses through the CMOS.FETs. A sub delay element 22 is connected in series to a main delay element 21 in which a timing is set and placed in the vicinity of the element 21. Both delay elements are connected in the same cell structure and arrangement. The sum of initial values of the delay amounts of respective delay elements is made to be a constant value. An input pulse to the main delay element is also supplied to a reference signal generator part 27 which outputs a reference signal using a reference clock after the lapse of the constant value from the time the input pulse is inputted. A time difference between this reference signal and the output from the sub delay element 22 is detected by a time difference detection part 29.

Abstract: A circuit for controlling frequency and/or phase response characteristic of a signal amplification system or channel has a serial architecture composed of a plurality of cells and a selector for deriving the signal after any one of the cascaded cells. At least one component of the RC network of each cell is in the form of a plurality of elements connected in series, each of the elements having a value which is a fraction of the design value of the component. A short-circuiting switch is associated with each element; the overall effect may be chosen by selecting the derivation node of the output signal and a certain configuration of the short-circuiting switches of the RC networks of the various cells. An outstanding flexibility of selection is achieved.

Abstract: Independent functional units are clocked by a clock source generator having at least two adjustable delay lines for independently adjusting the duty cycles of at least two clocks so that speed path margins are individually optimized for each functional unit.

Abstract: A signal generator generates a reference signal, centered about a reference voltage and having a predetermined period. The signal generator also generates output signals P and Z. The output signal P is a squarewave which changes levels at the peaks of the reference signal. The output signal Z is a squarewave which changes levels at the reference voltage crossings of the reference signal. A phase-shifted signal generator generates a phase-shifted signal using the output signals P and Z by switching in appropriate signal levels from the signal generator. The output signals P and Z are input to a switch control circuit which controls a network of switches, depending on a current region of the reference signal, to couple appropriate signals to an amplifier circuit. The switch control circuit determines the current region based on the state of the output signals P and Z. The amplifier circuit provides the phase-shifted signal in response to the signals coupled to it by the network of switches.

Abstract: A phase shifter using digital counters allows extremely accurate phase shifts. In a parallel circuit arrangement of a number of basic phase shift units, which each includes a dual modulus counter and phase control circuitry for controlling the counter modulus, the outputs of several units are combined in parallel. With the divider ratios of all the dividers of the units consisting of roots of pairwise relatively prime numbers, the total number of phase states is equal to the multiplication of its divider ratios.

Abstract: The present invention provides a phase shifting apparatus and method. The phase shifting apparatus comprises a signal generator and a converting device. An input signal is converted by the offset signals from the signal generator, thereby producing an output signal with the same frequency as that of the input signal. The phase of the output signal is determined by the difference of the offset signals applied to the converting device. In particular, when two offset signals are in quadrature, the output signal becomes in quadrature with the input signal. When the two offset signals have the same phase, the output signal has the same phase as that of the input signal. Preferably, the converting device includes two cascaded offset means, each having a multiplier and a filter coupling to the multiplier. A plurality of converting means may be coupled in parallel to the signal generator.

Abstract: A video clock input signal is applied to a delay line comprising a cascade connection of a plurality of delay elements formed in an integrated circuit for providing a plurality of delayed clock signals at respective taps of the delay line. A selection circuit, responsive to a horizontal synchronizing signal supplied thereto, couples a selected one of the taps to an output for providing a delayed output clock signal that is edge-aligned with the synchronizing signal. For reducing the number of taps required to provide a given minimum delay step resolution and a given minimum total delay for delay elements which may vary in delay, from one integrated circuit to another, the taps are spaced one element apart for a first group of the delay elements and are spaced more than one element apart for at least one second group of the elements.