Abstract: An electronic device which includes a first stage having an input capacitance, a switch, a buffer and a second stage having an input sensitive to charge injection and/or voltage glitches. An input of the buffer and the input of the second stage are coupled together at a first node which is configured to be coupled to a voltage source for supplying a reference voltage to the input of the first stage having the input capacitance. In a first configuration of the switch, the switch is arranged to either connect the input of the first stage to the first node and to disconnect the input of the first stage from an output of the buffer. In a second configuration of the switch, to connect the input of the first stage to the output of the buffer and to disconnect the input of the first stage from the first node.

Abstract: A circuit includes a diode circuit and a deactivation circuit. The diode circuit includes a first terminal, a second terminal, and a plurality of diodes coupled in parallel between the first terminal and the second terminal. The diode circuit is configured to be forward biased in an on-time and reverse biased in an off-time. The deactivation circuit is configured to switch a first group of the diodes into a deactivation state at a time instant before the end of the on-time, the first group of diodes including one or more but less than all of the diodes included in the diode circuit.

Abstract: An integrated circuit includes a plurality of power gating elements for controlling power applied to a first module which is in a powered off state, while a second module is in a powered on state, the second module being coupled to receive at least one signal from the first module when the first module is powered on. A a synchronization controller is provided for controlling the power gating elements to ramp up the power gated to the first module in order to power it up and, for a time while the power gated to the first module is below a first level, reducing the power gated to the second module, and for a time when the power gated to the first module is above the first level, increasing the power gated to the second module.

Abstract: In the device, a pair of transistors includes first and second transistors connected in parallel between a power-supply-line and a power-supply or between a ground-line and a ground-potential. A third transistor is connected between the power-supply-line and the power-supply or between the ground-line and the ground-potential. First to third nodes are gate nodes of the first to third transistors. A first buffer outputs a first control-signal for controlling the first transistor. A second buffer is connected between the first node and the second and third nodes to receive the first control-signal and transmit a second control-signal for controlling the second and third transistors to the second and third nodes in parallel. When power-supplying starts, the second control signal drives the second and third transistors to the conductive-state after the first control-signal controls the first transistor to be driven in an intermediate-state between the conductive-state and a shutoff-state.

Abstract: An electronic switch contains an input terminal, and output terminal and at least one first switch element, which provides a voltage-dependent characteristic. In this context, the first switch element connects the input terminal to the output terminal in a selective manner. The electronic switch further comprises a compensation element, which provides a voltage-dependent characteristic. In this context, the compensation element is arranged in such a manner that it at least partially compensates the frequency-dependent characteristic of the switch element.

Abstract: A gate driving device includes a gate driving unit, a first control unit, a second control unit and a switch unit. The first control unit includes an input terminal receiving a first output signal and a first clock input terminal receiving a first clock signal. The second control unit includes an input terminal receiving a second output signal and a first clock input terminal receiving a second clock signal. The switch unit, the first control unit and the second control unit are coupled to a carryout signal output node for generating a carryout signal at the carryout signal output node which indicates whether the gate driving unit is functioning correctly. The first output signal and the second output signal of the gate driving unit are respectively one signal generated by any two different stages of shift register in the gate driving unit.

Abstract: The present invention discloses a semiconductor device and relates to the semiconductor field. The semiconductor device comprises: a PMOS transistor for processing a input signal, the PMOS transistor comprising a gate and a source, the source being connected to a first voltage source; and a restoring circuit connected to the PMOS transistor for preventing degradation of the PMOS transistor, wherein the restoring circuit makes the gate voltage of the PMOS transistor to be higher than the voltage of the first voltage source, when the input signal is at a high level. According to the semiconductor device of the present invention, a positive bias voltage is applied on the gate of the PMOS transistor through the restoring circuit when the PMOS transistor is turned off, which can accelerate electric parameter recovery for PMOS transistors and therefore improve the performance of PMOS transistors.

Abstract: A sample and hold circuit and a method for sampling a signal are disclosed. The sample and hold circuit includes first and second switches, first, second, and third capacitors, and an amplifier. The amplifier receives a signal to be sampled on a first input. The first capacitor is characterized by a first capacitance and has a first terminal connected to an output of the amplifier by the first switch. The second capacitor is characterized by a second capacitance and has a second terminal connected to the output of the amplifier by the second switch. The third capacitor connects the first and second terminals. The amplifier is configured to form a capacitive transimpedance amplifier having the third capacitor as a feedback circuit when the first switch is in a non-conducting state and the second switch is in a conducting state.

Abstract: According to one embodiment, a semiconductor device includes: a substrate; a first circuit portion; and a second circuit portion. The first circuit portion includes: a first and a second switching elements, and a first and a second diodes. The second circuit portion includes a third and a fourth switching elements, and a third and a fourth diodes. The first switching element is juxtaposed with the second switching element in a first direction, and is juxtaposed with the fourth switching element in a second direction. The third switching element is juxtaposed with the fourth switching element in the first direction, and is juxtaposed with the second switching element in the second direction. A voltage is applied to electrodes of the first and third switching elements. A voltage of a polarity opposite the first voltage is applied to electrodes of the second and fourth switching elements.

Abstract: A transmission circuit is formed such that plural driver units of each driver circuit are connected together in parallel. A code setting section detects a voltage Vms output from a replica circuit corresponding to a driver unit of a driver circuit, and detects a voltage Vmo output from a replica circuit corresponding to one driver unit of the driver circuit, and based on a ratio of the voltages Vms, Vmo, sets operation numbers Na to Nd of driver units for each of the driver circuits such that the output resistance value of each of the driver circuits becomes pre-set output resistance values Roa to Rod. The driver circuit has a number of driver units according to the operation number connected together in parallel and operating.

Abstract: Provided is a semiconductor device with an output circuit in which a variation of a common voltage is suppressed in an idling mode and in a normal mode. The output circuit provided in the semiconductor device includes a first termination resistor and a second termination resistor and a drive circuit which flows current through the termination resistors. The output circuit is configured so as to be able to adjust the value of current which flows through the first termination resistor and the second termination resistor or the value of resistance of the first termination resistor and the second termination resistor.

Abstract: In a bipolar transistor, a thin gate oxide, preferably less than 600 ?, is formed over the base surface region between the emitter and collector. A conductive gate, such as doped polysilicon, is then formed over the gate oxide and biased at the emitter voltage. In the example of a PNP transistor, when the emitter is forward biased with respect to the base to turn the transistor on, the gate is at a positive potential relative to the base. This causes the holes in the base conducting the emitter-collector current to be repelled away from the surface, and the electrons in the base to be attracted to the surface, so that more of the emitter-collector current flows deeper into the base. Thus, the effect of defects at the base surface is mitigated, and 1/f noise is reduced. The invention is equally applicable to PNP and NPN transistors. Other benefits result.

Abstract: A data link circuit switches high-speed signals through FET-based circuitry between channels. A FET responds to control signals at the gate terminal to operate in either a signal-passing mode or another (blocking) mode. In the passing mode, an AC (high-speed) signal is passed between the S-D terminals by coupling a first signal portion (of the AC signal) and with another signal portion diverted by the inherent capacitances associated with the FET. For offsetting the loading caused by the inherent capacitances associated with the FET-based switch, a biasing circuit is configured and arranged to bias the back-gate terminal of the FET transistor with a follower signal.

Abstract: A Local Interconnect Network (LIN) driver circuit employs a charging/discharging current applied to the gate of a driver transistor coupled to an LIN bus. The charging current includes a constant charging current and an additional soft charging current, whereas the discharging current includes a constant discharging current and an additional soft discharging current. As a result of the soft charge/discharge components, there is a significant reduction in electromagnetic emission on the LIN bus.

Abstract: A single slope AD converter circuit includes a comparator that compares a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage, a counter that counts a predetermined clock in parallel with the comparing process of the comparator, and a controller that outputs a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value. The comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value.

Abstract: In accordance with an embodiment, a method of operating a gate driving circuit includes monitoring a signal integrity at an output of the gate driving circuit. If the signal integrity is poor based on the monitoring, output of the gate driving circuit is placed in a high impedance state and an external signal integrity failure signal is asserted.

Abstract: Radio-frequency (RF) switch circuits are disclosed providing uniform voltage swing across a transmit switch for improved device performance. A switching circuit includes a switch having field effect transistors (FETs) defining an RF signal path between the input port and the output port, the switch configured to be capable of being in a first state corresponding to the input and output ports being electrically connected so as to allow passage of the RF signal therebetween, and a second state corresponding to the input and output ports being electrically isolated. The switching circuit includes a voltage distribution circuit configured to reduce voltage distribution variation across the switch, including one or more elements coupled to a selected body node of one or more FETs so as to reduce voltage distribution variation across the switch when the switch is in the first state and encountered by an RF signal at the input port.

Abstract: A switch circuit, a control circuit, a grounding wire and a control wire are formed on a substrate. The switch circuit connects an antenna terminal with one of multiple high frequency terminals. The control circuit outputs a control signal to the switch circuit. The grounding wire is disposed between the switch circuit and the control circuit and extends from a location proximate to an edge of the substrate to a location proximate to an opposite edge of the substrate. The control wire that carries the control signal is disposed between one end of the grounding wire and an edge of the semiconductor substrate.

Abstract: An element substrate includes a plurality of terminals, a first receiving circuit and a second receiving circuit each receiving a differential signal via one of the terminals included in the plurality of terminals, a driving circuit including a first input unit for inputting a first signal and a second input unit for inputting a second signal and driving a driving element based on the first signal and the second signal, and a setting circuit for setting a first connection state of connecting an output from the first receiving circuit to the first input unit and connecting an output from the second receiving circuit to the second input unit, and a second connection state of connecting an output from the first receiving circuit to the second input unit and connecting an output from the second receiving circuit to the first input unit based on an externally input signal.

Abstract: A gate driving device includes a gate driving unit, a first control unit, a second control unit and a switch unit. The first control unit includes an input terminal receiving a first output signal and a first clock input terminal receiving a first clock signal. The second control unit includes an input terminal receiving a second output signal and a first clock input terminal receiving a second clock signal. The switch unit, the first control unit and the second control unit are coupled to a carryout signal output node for generating a carryout signal at the carryout signal output node which indicates whether the gate driving unit is functioning correctly. The first output signal and the second output signal of the gate driving unit are respectively one signal generated by any two different stages of shift register in the gate driving unit.

Abstract: There is provided a radio frequency switch circuit including a first switch circuit unit connected between a first node connected to a first signal port and a common node connected to a common port, and operated according to a first control signal, a second switch circuit unit connected between a second node connected to a second signal port and the common node and operated according to a second control signal having a phase opposite to that of the first control signal, a first shunt circuit unit connected between the second node and a common source node and operated according to the first control signal, a second shunt circuit unit connected between the first node and the common source node, and a source voltage generating unit generating a source voltage, wherein the source voltage is lower than a high level of the first control signal and higher than a ground potential.

Abstract: In a drive unit for a reverse-conducting switching element which is a driven switching element, a process to transfer electric charges to a conductive control terminal of the driven switching element is performed on the basis of a turn-on command or a turn-off command, thereby turning on and off the driven switching element. A transfer rate of the electric charges is changed in a period from when the transfer of the electric charges to the conductive control terminal is started until when it is completed. While judged that forward current flows in a free-wheel diode, the electric charges are inhibited from being charged to the conduction control terminal which corresponds to the free-wheel diode in which the forward current is judged to flow. While the electric charges are inhibited from being charged to the conductive control terminal, a change of the transfer rate is disabled.

Abstract: A gate driver includes a plurality of stages respectively outputting a plurality of gate output signals. An N-th stage of the gate driver (where N is a positive integer) includes a first input part, a second input part, a pull up part, a pull down part, a holding part and a stabilizing part. The first input part transmits a first clock signal to a second node in response to a signal at a first node. The second input part transmits an input signal to the first node in response to a second clock signal. The pull up part pulls up the gate output signal in response to a signal at the second node. The pull down part pulls down the gate output signal in response to the signal at the first node. The holding part maintains the signal at the second node in response to the first clock signal. The stabilizing part stabilizes the gate output signal in response to the signal at the second node and a third clock signal.

Abstract: A method for reducing a disturbance on a signal path is provided. The disturbance is caused by a capacitance of a semiconductor switch (131-133) of an integrated circuit (130). The semiconductor switch (131-133) switches the signal path. The capacitance (203, 214) acts between the semiconductor switch (131-133) and a power supply terminal of the integrated circuit (130). According to the method, the power supply terminal of the integrated circuit (130) is coupled via an impedance (138, 139) to a power supply (137, 140).

Abstract: Disclosed is a radio frequency (RF) switch branch having a reduced nonlinearity and an associated method for reducing nonlinearity in a RF switch branch. The RF switch branch includes a primary transistor, a first transistor having power terminals electrically connected between a drain node and a body node of the primary transistor, and a second transistor having power terminals electrically connected between the body node and a source node of the primary transistor. The RF switch may further include a body resistor electrically connected between the body node of the primary transistor and ground, and a gate resistor electrically connected between a gate of the primary transistor and a gate voltage source. A gate of each of the first transistor and the second transistor is electrically connected to the gate voltage source such that the first transistor and the second transistor are ON only when the primary transistor is ON.

Abstract: One embodiment of the present invention sets forth a mechanism for transmitting and receiving ground-referenced single-ended signals. A transmitter combines a direct current (DC) to DC converter including a flying capacitor with a 2:1 clocked multiplexer to drive a single-ended signaling line. The transmitter drives a pair of voltages that are symmetric about the ground power supply level. Signaling currents are returned to the ground plane to minimize the generation of noise that is a source of crosstalk between different signaling lines. Noise introduced through the power supply is correlated with the switching rate of the data and may be reduced using an equalizer circuit.

Abstract: AFE circuitry handles both voltage and current input signals. In one embodiment, both a voltage path and a current path are provided from the input. Switching circuitry selects one of the paths. A switch also turns on or off a current-to-voltage conversion circuit used to convert a current input into a voltage. In one embodiment, noise is significantly reduced by using a dedicated ground pin or terminal for the negative reference of a differential circuit. This applies the same external board noise, which is on the input signal, to the negative reference, so the noise is canceled in the differential signal. In one embodiment, temperature compensation is provided via an IPTAT circuit which is used to shift the voltage up in order to balance the decrease in DC voltage with increasing temperature.

Abstract: A system for transmitting data includes a plurality of data lines configured to transmit the data and a transmitting chip configured to output the data to the data lines and perform a crosstalk prevention operation in response to a data pattern of the data to be transmitted through the data lines and array information of the data lines to prevent crosstalk from occurring in the data lines.

Abstract: Radio-frequency (RF) switch circuits are disclosed having adjustable resistance to provide improved switching performance. RF switch circuits include at least one field-effect transistor (FET) disposed between first and second nodes, each of the FET having a respective gate and body. An adjustable-resistance circuit is connected to either or both of the respective gate and body of the FET(s).

Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each having a respective source, drain, gate, and body. The system includes a coupling circuit including a first path and a second path, the first path being between the respective source or the respective drain and the respective gate of the at least one FET, the second path being between the respective source or the respective drain and the respective body of the at least one FET. The coupling circuit may be configured to allow discharge of interface charge from either or both of the coupled gate and body.

Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each FET having a respective gate and body. A resonance circuit connects the body of each of the at least one FET to a reference node. The resonance circuit may be configured to behave as an approximately closed circuit at low frequencies below a selected value and an approximately open circuit at an operating frequency, wherein the approximately closed circuit allows removal of surface charge from the body to the reference node.

Abstract: Radio-frequency (RF) switch circuits providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each FET having a source, drain, gate, and body. A compensation circuit is connected to the respective source of the at least one FET. The compensation circuit may be configured to compensate a non-linearity effect generated by the at least one FET.

Abstract: A grounding switch is described which operates properly even in the presence of negative voltages on a signal line. The grounding switch uses isolated field effect transistors that have their substrates tied to different voltages. The isolated field effect transistor has a gate voltage and substrate voltage which can be pulled down to a negative voltage when the signal line has a negative voltage allowing the switch to remain open even with a negative voltage.

Abstract: A method for reducing spurious for a clock distribution system, the method including a) providing a system controller, b) providing clock distribution system, c) inputting characteristics of the clock distribution system in advance of operation thereof, d) calculating an expected level of the integer boundary spurious as a function of a fractional offset value, e) selecting an integer boundary solution based on the fractional offset value being within a preferred predetermined region, and f) programming the master clock subsystem and the one or more fractional synthesizers with the integer boundary solution, and g) repeating steps d) through f) as needed.

Abstract: A super high voltage device includes a first gate, a second gate, a drain, a first source, a second source, and a third source. The first gate is used for receiving a first control signal generated from a pulse width modulation controller. The second gate is used for receiving a second control signal generated from the pulse width modulation controller. The drain is used for receiving an input voltage. First current flowing from the drain to the first source varies with the first control signal and the input voltage. The second control signal is used for controlling turning-on and turning-off of second current flowing from the drain to the second source and third current flowing from the drain to the third source. The third source is proportional to the second current.

Abstract: A system includes control circuitry configured to provide one or more control pulses in response to a command signal, the one or more control pulses being communicated from the control circuitry to associated circuitry via a connection. A detector is configured to detect a disturbing signal that mitigates reception of the one or more control pulses via the connection. The command signal is controlled to cause the control circuitry to provide one or more additional control pulses when the disturbing signal is detected by the detector to improve a likelihood of the reception of the one or more control pulses via the connection.

Abstract: A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETs) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply.

Abstract: Apparatus and methods for a switch circuit to provide a substantially constant gate-to source voltage to a passgate are provided. In an example, a switch circuit includes a summing circuit having an output configured to couple to the gate of a passgate, the summing circuit can be configured to maintain a substantially constant voltage between the gate and the source of the pass gate.

Abstract: An element substrate includes a plurality of terminals, a first receiving circuit and a second receiving circuit each receiving a differential signal via one of the terminals included in the plurality of terminals, a driving circuit including a first input unit for inputting a first signal and a second input unit for inputting a second signal and driving a driving element based on the first signal and the second signal, and a setting circuit for setting a first connection state of connecting an output from the first receiving circuit to the first input unit and connecting an output from the second receiving circuit to the second input unit, and a second connection state of connecting an output from the first receiving circuit to the second input unit and connecting an output from the second receiving circuit to the first input unit based on an externally input signal.

Abstract: In a drive unit for a reverse-conducting switching element which is a driven switching element, a process to transfer electric charges to a conductive control terminal of the driven switching element is performed on the basis of a turn-on command or a turn-off command, thereby turning on and off the driven switching element. A transfer rate of the electric charges is changed in a period from when the transfer of the electric charges to the conductive control terminal is started until when it is completed. While judged that forward current flows in a free-wheel diode, the electric charges are inhibited from being charged to the conduction control terminal which corresponds to the free-wheel diode in which the forward current is judged to flow. While the electric charges are inhibited from being charged to the conductive control terminal, a change of the transfer rate is disabled.

Abstract: One embodiment of the present invention sets forth a mechanism for transmitting and receiving ground-referenced single-ended signals. A transmitter combines a direct current (DC) to DC converter including a flying capacitor with a 2:1 clocked multiplexer to drive a single-ended signaling line. The transmitter drives a pair of voltages that are symmetric about the ground power supply level. Signaling currents are returned to the ground plane to minimize the generation of noise that is a source of crosstalk between different signaling lines. Noise introduced through the power supply is correlated with the switching rate of the data and may be reduced using an equalizer circuit.

Abstract: An identifying circuit is connected between a Universal Serial Bus (USB) interface and a controller. The identifying circuit includes first to fourth electronic switches. When a power adapter connects to the USB interface, the first and fourth electronic switches are not turned on, and the second and third electronic switches are turned on. An identification pin of the controller receives a low level signal and determines that the power adapter connects to the USB interface. When a computer connects to the USB interface, the first and fourth electronic switches are turned on, and the second and third electronic switches are not turned on. The identification pin receives a high level signal and determines that the computer is connected to the USB interface.

Abstract: A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit.

Abstract: An electric circuit includes a first circuit, a second circuit, a synchronization detection circuit, a storage circuit, and a correction circuit. The first clock is configured to operate with a first clock, the second circuit is configured to operate with a second clock which is different in frequency from the first clock, and the synchronization detection circuit is configured to detect synchronization of the first and second clocks. The storage circuit is configured to store an output noise pattern of the second circuit, based on the synchronization detected by the synchronization detection circuit, and the correction circuit is configured to correct an output of the second circuit by using the output noise pattern.

Abstract: A noise rejection circuit for a touch sensitive display is disclosed. The noise rejection circuit can reject noise introduced by the touch sensitive display's display device into its touch panel. The noise rejection circuit can be integrated into the touch circuitry of the touch sensitive display and can include a resistor to sense the noise and an amplifier to isolate the sensed noise for rejection.

Abstract: A switch circuit is disclosed. The switch circuit may include one or more arrangements of transistors coupled in a cascode configuration. The transistors used to implement the switch circuit may be configured for operation within a first range of voltages. The application in which the switch circuit may be implemented may require conveying signals within a second range of voltages that is greater than the first range of voltages. Thus, the switch circuit may include one or more additional transistors to ensure that a voltage drop between any two terminals of the transistors used in the switch circuit is within the first range of voltages.

Abstract: Included are embodiments of a 3-level line driver. At least one embodiment of a method includes generating a repetitive wave; receiving an input signal and a complement of the input signal; providing a 3-level output signal; and filtering a feedback signal, the means for filtering including at least one of the following: a 0th order filter, and an even order filter.

Abstract: A voltage buffer may include a first signal path extending from an input terminal to an output terminal in which the first signal path further may include a buffer transistor that may have a control terminal, and a first and second current terminals responsive to the control terminal. In the first signal path, the control terminal may be connected to the input terminal, the first current terminal may be connected to the output terminal, and the first signal path may supply a load current to a load device responsive to an input signal at the input terminal. The voltage buffer further may include a second signal path extending from the input terminal to a current source node. The second signal path may include a replica load device. The voltage buffer further may include a current source supplying substantially constant current and coupled to the current source node.

Abstract: The present invention discloses a semiconductor device and relates to the semiconductor field. The semiconductor device comprises: a PMOS transistor for processing a input signal, the PMOS transistor comprising a gate and a source, the source being connected to a first voltage source; and a restoring circuit connected to the PMOS transistor for preventing degradation of the PMOS transistor, wherein the restoring circuit makes the gate voltage of the PMOS transistor to be higher than the voltage of the first voltage source, when the input signal is at a high level. According to the semiconductor device of the present invention, a positive bias voltage is applied on the gate of the PMOS transistor through the restoring circuit when the PMOS transistor is turned off, which can accelerate electric parameter recovery for PMOS transistors and therefore improve the performance of PMOS transistors.

Abstract: An integrated gate driver circuit includes an output drive circuit and a voltage stabilizing circuit. The voltage stabilizing circuit is configured to stabilize an output voltage outputted by the output drive circuit thereby reducing the ripple of the output voltage.