Abstract: Provided is a physical quantity sensor capable of improving physical quantity detection precision thereof. The physical quantity sensor includes a bridge resistance type physical quantity detection element for generating a voltage based on a bias current and a physical quantity, a current supply circuit for supplying the bias current to the physical quantity detection element, and a leakage current control circuit for causing leakage currents flowing when switches of the current supply circuit are in an off state to flow into a ground terminal.

Abstract: A DC-coupled two-stage gate driver circuit for driving a junction field effect transistor (JFET) is provided. The JFET can be a wide bandgap junction field effect transistor (JFET) such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit and a pull-down circuit. The driver is configured to accept an input pulse-width modulation (PWM) control signal and generate an output driver signal for driving the gate of the JFET.

Abstract: Printed circuit board having a termination of a T-shaped signal line having at least two line ends, one line end being terminated using a terminating resistor against a supply voltage, and the other line end being terminated against the reference potential of the supply voltage.

Abstract: Techniques are disclosed for reducing off-state leakage current in a differential switching device. The techniques can be embodied, for example, in a method that includes receiving a differential input signal at a differential input of each of a primary switch and a dummy switch. In an enabled-state of the device, the method further includes passing the differential input signal to a differential output of the primary switch. In a disabled-state of the device, the method further includes canceling off-state leakage current at the differential output of the primary switch, by virtue of the dummy switch having its differential output reverse-coupled to the differential output of the primary switch. The method may further include preventing the dummy switch from passing signals other than off-state leakage signals. The techniques can be embodied, for instance, in a switching device.

Abstract: A signal processor comprises a reference voltage circuit (RVC) for imposing a reference voltage (VR) onto a capacitance (Cr). The reference voltage circuit (RVC) comprises a negative slope module (NSM) for providing a negative slope signal (SN), which has a magnitude that decreases when a voltage that is present on the capacitance (Cr) increases. A positive slope module (PSM) provides a positive slope signal (SP), which has a magnitude that increases when the voltage that is present on the capacitance (Cr) increases. A minimum selection module (MSM) controls a maximum current (IMX) that the reference voltage circuit (RVC) can apply to the capacitance (Cr) substantially in dependence on the negative slope signal (SN), if the magnitude of the negative slope signal (SN) is smaller than that of the positive slope signal (SP).

Abstract: An exemplary gate driving circuit is adapted for receiving an external gate power supply voltage and an external control signal, sequentially generating multiple internal shift data signal groups and thereby sequentially outputting multiple gate signals. Each of the internal shift data signal groups includes multiple sequentially-generated internal shift data signals. The gate driving circuit includes multiple gate signal generating modules. Each of the gate signal generating modules includes a voltage modulation circuit and a gate output buffer circuit. The voltage modulation circuit modulates the external gate power supply voltage according to a corresponding one of the internal shift data signal groups and the external control signal, and thereby a modulated voltage signal is obtained. The gate output buffer circuit includes a plurality of parallel-coupled output stages. The output stages output the modulated voltage signal as a part of the gate signals during the output stages being sequentially enabled.

Abstract: Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching circuit may have a metastable state that is closer to a first voltage corresponding to the first binary level than it is to a second voltage corresponding to the second binary level. In other embodiments, the metastable state may be dynamically adjustable so that it is at one voltage before the circuit switches and at a different voltage after the circuit switches. As a result, the switching circuit may respond relatively quickly to the input signal transitioning from the first binary level to the second binary level.

Abstract: An integrated circuit device includes an I/O circuit which buffers and outputs an input signal D from a pad when an enable signal ENB is set at a second voltage level, a circuit block to which an output signal from the I/O circuit is input, and a malfunction prevention circuit which outputs to the circuit block an output signal QP of which a voltage level is set by a first power supply VDDC in a period T1 in which the signal ENB is set at a first voltage level and a period T2 including a period in which the signal ENB changes from the first voltage level to the second voltage level, and outputs to the circuit block the output signal QP corresponding to an output signal QI from the I/O circuit in a period T3 in which the signal ENB is set at the second voltage level.

Abstract: Systems and methods for generation of a low jitter clock signal for wireless circuits are disclosed. In an implementation, the system includes a wireless circuit powered by a first power supply and a low jitter clock (LJC) generator powered by a second power supply. The LJC generator provides at least one clock signal to the wireless circuit. The system further includes an LJC driver circuit including a clock buffer powered by the first power supply and a receive buffer powered by the second power supply.

Abstract: A signal matching module for a single or multiple subsystems is disclosed. The signal matching module includes a plurality of electronic components with a first part of the electronic components categorized into external electronic components and a second part of the electronic components categorized into internal components. Each of the electronic components may correspond to a switch that is controllable by a corresponding control pin. And the external electronic components may be used to compensate the internal electronic components when the latter fail to cause the impedance to reach the desired level. One of the embodiments is to provide a unit cell which is used to connect with one or multiple subsystems, and an external communication port to which the external electronic components are connected serving as a feeding point for the purpose of better impedance matching.

Abstract: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.

Abstract: A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits.

Abstract: Provided is a physical quantity sensor capable of improving physical quantity detection precision thereof. The physical quantity sensor includes a bridge resistance type physical quantity detection element for generating a voltage based on a bias current and a physical quantity, a current supply circuit for supplying the bias current to the physical quantity detection element, and a leakage current control circuit for causing leakage currents flowing when switches of the current supply circuit are in an off state to flow into a ground terminal.

Abstract: An enhanced transistor gate drive is disclosed in which a pair of Kelvin sense leads measure the voltage potential across at the gate and source of the transistor. The difference in the voltage potential of the Kelvin sense lead from the gate and the Kelvin sense lead of the source is provided to a voltage controlled current source, which compares the output of the voltage differentiator to an oscillating voltage input. Changes to the voltage difference between the Kelvin sense connectors will result in more or less voltage being applied at the gate of the transistor, thereby parasitic inductance in the transistor from causing the device to switch on and off.

Abstract: A switch circuit is disclosed. The switch circuit may include one or more arrangements of transistors coupled in a cascode configuration. The transistors used to implement the switch circuit may be configured for operation within a first range of voltages. The application in which the switch circuit may be implemented may require conveying signals within a second range of voltages that is greater than the first range of voltages. Thus, the switch circuit may include one or more additional transistors to ensure that a voltage drop between any two terminals of the transistors used in the switch circuit is within the first range of voltages.

Abstract: Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

Abstract: A switching transistor has its drain and source respectively connected to a gate and a source of an output transistor for supplying output current to a load, and its gate connected to an internal grounding wire GW to be connected to a grounding terminal GND. A resistance element R1 connects the gate to the source of the switching transistor. When a voltage not smaller than a predetermined value is generated across the resistance element R1 at turn-on, due to a parasitic capacitance existing between a power supply terminal. Vcc and the internal grounding wire GW, the switching transistor can be turned on to turn off the output transistor.

Abstract: A switching circuit configured to reduce the effects of signal oscillation on the operation of the switching circuit is provided. The switching circuit may include signal oscillation and detection circuitry that suppresses control signals during a detected oscillation, allowing stored energy to naturally decay in the switching circuit and thereby prevent unwanted extension of the oscillation that may be caused by the repeated switching of a semiconductor element coupled between the input and output of the switching circuit.

Abstract: One embodiment is a gate drive circuitry for switching a semiconductor device having a non-isolated input, the gate drive circuitry having a first circuitry configured to turn-on the semiconductor device by imposing a current on a gate of the semiconductor device so as to forward bias an inherent parasitic diode of the semiconductor device. There is a second circuitry configured to turn-off the semiconductor device by imposing a current on the gate of the semiconductor device so as to reverse bias the parasitic diode of the semiconductor device wherein the first circuitry and the second circuitry are coupled to the semiconductor device respectively through a first switch and a second switch.

Abstract: To easily judge a transmission signal outputted from an own electronic device. A transmission part 7 outputs a transmission signal to a transmission path 1 side. Switching parts Q1 and Q2 are connected between a constant voltage power source and the transmission path 1, to switch on/off of a signal supplied from the constant voltage power source, being the transmission signal from the transmission part 7, and output it to the transmission path 1. A reception part 9 receives the transmission signal from the transmission path 1. A detection part 13 is connected between the constant voltage power source and the switching parts Q1, Q2, to detect the transmission signal from the transmission part 7 flowing through the switching parts Q1 and Q2. A selection part 15 selects the reception part 9, when the transmission signal from the transmission part 7 is not detected by the detection part 13.

Abstract: An apparatus and system are provided to adjust an output voltage of an integrated circuit (IC) die. For instance, the apparatus can include an on-chip source termination and a bias generator. The bias generator can be configured to provide a source current to the on-chip source termination to adjust the output voltage. In particular, when adjusting the output voltage of the IC die, the bias generator can adjust the source current using a first current with a first adjustable current gain and a second current source with a second adjustable current gain.

Abstract: A wired signal receiving apparatus including a signal receiver, a signal peak detector, and a signal comparator is disclosed. The signal receiver includes an operation current detecting circuit for detecting an operation current. The signal receiver further receives a transmission signal. The signal peak detector receives the operation current, detects a peak thereof, and generates a peak current. The signal comparator compares a reference signal and the peak current to generate an output current for regulating the operation current.

Abstract: The present invention is directed to a capacitive decoupling module and method for an integrated circuit that features providing multiple capacitive elements to decouple the power rails from the integrated circuit. The multiple capacitive elements are spaced-apart, along a first direction, from the integrated circuit. A first set of capacitive elements is closer to the integrated circuit than a second set of capacitive elements. The first set has a smaller capacitance than the second set.

Abstract: The joint (36) comprises a tubular body (37) having two connecting zones (38, 39) each connected by an end to a tubular element (40) of a fluid transport line, giving continuity to passage of fluid. The tubular body is made of a mixture of an electrically-conductive material such as PVC, with carbon black to give it electrical conductivity. The joint has an internal surface (41) which is destined to come into contact with the transported fluid, and an external surface which is destined to have a grounded galvanic contact. The joint is inserted in the discharge fluid drainage line of a dialyzer filter, in an apparatus for intensive treatment of acute renal insufficiency, for eliminating ECG artefacts due to functioning of peristaltic pumps in the apparatus.

Abstract: In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a pulse threshold on the victim line. The induced voltage pulse is counteracted by coupling the victim line to a counteracting voltage source. After a predetermined delay period, the coupling of the counteracting voltage source is removed from the victim line. The voltage change on the aggressor line my be sensed from a node connected to either the aggressor line or the victim line. A rising induced pulse is counteracted by coupling the victim line to a more negative voltage source, and a falling induced pulse is counteracted by coupling the victim line to a more positive voltage source.

Abstract: The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.

Abstract: The present application discloses systems and methods to for a high speed electronic switch with the internal capability to reduce noise. This noise reduction is accomplished through a noise suppression circuit. A noise source is connected a signal source; a noise suppression circuit is electrically connected to the switching source; and a switch driver is electrically connected to a noise suppression circuit. The noise reduction unit prevents noise from being propagated from the noise source to an output switch, thereby preventing the noise from reaching the downstream signal line.

Abstract: A clock gating cell that comprises a latch in communication with an input enable logic and an output logic circuit, wherein the latch includes a pull-up and/or a pull-down circuit at an input node of the output logic circuit and circuitry preventing premature charge or discharge of the output logic circuit input node by the pull-up and/or the pull-down circuit when the clock gating cell is enabled.

Abstract: An input buffer circuit. In one embodiment, the input buffer circuit includes a first transistor operable to receive a first input signal, a second transistor operable to receive a second input signal, and a first mechanism coupled to the first transistor and to the second transistor. The first mechanism is operable to control the first and second transistors such that the first and second transistors can receive either single-ended input signals or differential input signals. According to the embodiments disclosed herein, the input buffer combines single-ended input and differential input functionalities without compromising performance.

Abstract: A transmission line driver and a serial interface data transmission device including the same are provided. The transmission line driver includes a pre-driver configured to generate and output differential input data signals based on a serial transmission data signal, a differential amplifier configured to receive the differential input data signals and to output differential output data signals, and a common mode controller configured to drive the differential output data signals to a predetermined common mode voltage in an idle mode. Accordingly, power consumption can be reduced and a common mode specification can be supported.

Abstract: A high voltage reception terminal is formed in a semiconductor integrated circuit without increasing the number of manufacturing processes and the manufacturing cost. A transfer gate configured from a NMOS, which is the high withstand voltage transistor, and a pull-up resistor are formed. An input terminal of the transfer gate is connected to the high voltage reception terminal and an output terminal of the transfer gate is connected to a CMOS inverter through an input resistor. One end of the pull-up resistor is connected to the output terminal of the transfer gate and the other end of the pull-up resistor receives source voltage VDD (5V). The transfer gate lowers the inputted high voltage VX (VX>VDD) to VDD-Vt1?. The pull-up resistor biases the voltage at the output terminal of the transfer gate to VDD and boosts the voltage at the output terminal that has been lowered by the transfer gate to about VDD.

Abstract: A circuit for actuation of a transistor. One embodiment provides an actuation output for connection to the actuation connection of the transistor. A measurement arrangement is provided for ascertaining a load current flowing through the load path or a voltage across the load path and for providing a measurement signal. An actuation current source having an actuation current output is connected to the actuation output and supplied with the measurement signal and designed to produce an actuation current at the actuation current output. The actuation current is at a current level dependent on the measurement signal.

Abstract: The present disclosure relates to constructing and operating a transistor or other active device with significantly reduced flicker noise.

Abstract: The invention relates to a method for monitoring whether or not the switching threshold of a switching sensor lies within a predefined tolerance region. The switching sensor comprises a signal input, to which an input signal is applied, and a signal output via which a switch output signal is emitted that can take a first value when the input signal is larger than the switching threshold and, otherwise, takes a second value. A modulator signal generated by a modulator (MD) is used as an input signal, characterized in that the modulator signal changes continuously or cyclically between an output value, which defines the upper limit of the tolerance region, and a test value which is smaller than the output value and defines the lower limit of the tolerance region. According to the invention, the switch output signal pulses at the rate of the modulator signal between the first and the second value when the switching threshold of the switching sensor lies within the tolerance region.

Abstract: A receiving circuit is provided for receiving a data signal and a clock signal, which are RSDS signals, and outputting an output data signal to a data driver. The receiving circuit includes a data comparator, a data intermediate circuit, a clock comparator, a clock intermediate, and a flip-flop. The data comparator, driven with a data bias current, receives the data signal, and outputs a compared data signal. The clock comparator, driven with a clock bias current, receives the clock signal, and outputs a compared clock signal. The flip-flop receives the compared data signal via the data intermediate circuit and the compared clock signal via the clock intermediate circuit. The phase difference between the compared data signal and the compared clock signal is improved by adjusting the data and the clock bias currents.

Abstract: A circuit for assisting signal transitions on a wire, and a method thereof. The circuit includes a first subcircuit that causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and then turn off. The first transistor drives the output to a high state to assist in the rising transition. The circuit also includes a second subcircuit that causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and then turn off. The second transistor drives the output to a low state to assist in the falling transition.

Abstract: The signal switch has flat resistance across the input/output voltage range when in the ON state while still isolating input/output nodes from overshoots and undershoots when in the off state.

Abstract: An apparatus and system are provided to adjust an output voltage of an integrated circuit (IC) die. For instance, the apparatus can include an on-chip source termination and a bias generator. The bias generator can be configured to provide a source current to the on-chip source termination to adjust the output voltage. In particular, when adjusting the output voltage of the IC die, the bias generator can adjust the source current using a first current with a first adjustable current gain and a second current source with a second adjustable current gain.

Abstract: An analog buffer circuit (10) includes a first p channel field effect transistor (11), an n channel field effect transistor (12) and a second p channel field effect transistor (13). The transistors are connected to one another in serial between power supplying terminals (VDD and GND). The transistors have gates connected to an input terminal (IN) in common. An output terminal (OUT) is connected to a connecting point between the n channel transistor and the second p channel transistor. With this structure, output voltage which appears on the output terminal is approximately proportional to input voltage supplied to the input terminal.

Abstract: A high-side driving circuit is provided, where Q terminal and Q terminal of the latch circuit respectively feed back to the first switch and the second switch, which may control asymmetric impedance, such that the high-side driving circuit can prevent noise.

Abstract: A noise reduction circuit outputs a signal corresponding to a voltage difference between two different signals. The noise reduction circuit includes: an amplifier circuit for amplifying the two different signals at different timings; and a voltage difference detection circuit for detecting a voltage difference between the two different signals amplified by the amplifier circuit. The noise reduction circuit accumulates, a predetermined number of times, an electric charge corresponding to the voltage difference detected by the voltage difference detection circuit and combines the accumulated electric charges to output a resultant electric charge.

Abstract: Methods, systems and apparatus for a controller for fast transient response, the controller including a linear compensation circuit for controlling output voltage during steady state operation and a non-linear control circuit to generate a non-linear signal during transient periods, only a first pulse of the non-linear signal is injected during each transient period. The combination linear and non-linear control provides stability and reduces delay times for fast transient response. The non-linear control circuit includes a step up and a step down non-linear control circuit for producing the non-linear signal with a short delay time when the load voltage is less or greater than the reference voltage. An embodiment includes an adaptive circuit or generating a current signal dependent on the load current, the current signal is combined with the output voltage to reduce the difference between the reference and output voltages.

Abstract: A communication system includes an integrated circuit (IC) die having an on-chip source termination. The on-chip source termination can be a non-precision resistor, such as an unsilicided poly resistor, or any other suitable termination. As compared to an off-chip source termination, the on-chip source termination can reduce voltage peaking and/or voltage overshoot in the IC die and/or at a load that is connected to the IC die. The IC die can further include a line driver to provide a source current. A bias generator can be included to provide a bias current to the line driver. The bias generator can include a first current source coupled to an off-chip resistor and a second current source coupled to an on-chip resistor. An output voltage of the IC die can be adjusted by manipulating a trim control of the off-chip resistor and/or a trim control of the on-chip resistor.

Abstract: A CAN receiver architecture design that provides better immunity against EMI interference than conventional designs is disclosed herein. This CAN receiver includes a voltage divider network connected to a front-end amplifier for dividing down the input signal from a two wire line by a predetermined amount and amplifying the signal by the same predetermined amount. The front-end amplifier generates the common-mode voltage of the input signal for a reference generator that determines the logic level of the incoming signal and subtracts a bandgap voltage reference from the common-mode voltage. A comparator compares the difference between the output of the front-end amplifier and the resultant signal generated by the reference generator to generate an output signal for the receiver. This CAN receiver architecture is faster than conventional designs and possesses an improved common-mode rejection, while operating over a wide input common mode range.

Abstract: There is provided a high frequency switching circuit having good characteristics of high-order harmonics that has little variation. A high frequency switching circuit according to an aspect of the invention may include: a high frequency switch having one end connected to an input terminal receiving a high frequency signal and the other end connected to an output terminal of the high frequency signal, the high frequency switch turned on or off by a control signal; and a capacitor having a predetermined capacitance, and having one end connected the output terminal and the other end connected to a ground by a bonding wire.

Abstract: A circuit and method for comparing and providing a signal indicative of a difference in magnitude between a differential signal voltage and a differential reference voltage.

Abstract: An analog insulation multiplexer not causing magnetic saturation even if a small transformer is used and having a wide use temperature range. The analog insulation multiplexer includes: a first switching element for generating a drive control signal in accordance with an external signal; a drive insulation transformer for receiving the drive control signal on a primary side via a first resistor and for delivering an insulated drive control signal from a secondary side; a second switching element for chopping an analog signal input in accordance with the insulated drive control signal; and an analog signal insulation transformer for delivering an insulated chopped analog signal on a secondary side.

Abstract: In order to further develop a circuit arrangement (100; 100?; 100?) as well as a corresponding method for controlling and/or for preventing injection current, said method comprising—switching at least one transistor means (20; 20?) between at least one enabled state and at least one disabled state in dependence on the signal level of at least one voltage and/or current signal, and—transmitting at least one analog and/or digital signal from at least one first pin (pin1) to at least one second pin (pin2) via at least one conductive channel (12, 14) in the enabled state of the transistor means (20; 20?), in such way that minimal disturbance due to unwanted current signals and/or due to unwanted is ensured, in particular that the MOS effect as well as the bipolar effect are prevented in the circuit arrangement (100; 100?; 100?), it is proposed—to prevent the transistor means (20; 20?) from starting to conduct due to being provided with at least one unwanted signal in its disabled state, and to prevent transmissio

Abstract: A circuit is disclosed, including a transistor switch having a first terminal to receive an input voltage, a second terminal to output an output voltage and a gate terminal; a determination circuit, coupled to the first terminal and the second terminal of the transistor switch, to determine a lower or higher voltage between the input voltage and the output voltage; a voltage generator, coupled to the determination circuit, to generate a sum voltage or difference voltage using the lower or higher voltage; and a control circuit, coupled to the voltage generator and the gate terminal of the transistor switch, to apply the sum voltage or difference voltage to the gate terminal of the transistor switch during a first time interval.

Abstract: The present invention discloses an output circuit that is able to adjust the output voltage slew rate and avoid short-circuit current, comprising: a control circuit for receiving an input data and generating a first set of control signals based on the input data; an output control device consisting of a first field effect transistor (FET) connected in series with a second field effect transistor (FET) and the point of connection is the output end for generating an output signal; a first capacitor having one end connected to a first working voltage and generates a first control voltage by charging/discharging on another end to control the gate of the first field effect transistor; a first switch for controlling charging/discharging of the first capacitor device based on the first set of control signals; a first current source for providing charging current for the first capacitor device; a second capacitor having one end connected to a second working voltage and generates a second control voltage by charging/d