Abstract: A charge pump with a MOS-type capacitor, where the MOS-type capacitor is operated in an inversion region in which capacitance varies as a function of the frequency of the applied signal. The charge pump is switched to transfer charge from an input node to the capacitor and from the capacitor to an output node. During a transition interval, a relatively high frequency switching signal is used to lower the capacitance and increase efficiency. During a settling interval, a relatively low frequency switching signal is used, in which case the capacitance is higher, but similar to a level which would be seen if the capacitor was operated in an accumulation region. MOS capacitor dimensions and switching intervals are mutually optimized to provide high efficiency and required throughput. The charge pump may be configured as a voltage multiplier, divider, inverter or follower, for instance.

Abstract: In a first functional block, a source voltage input terminal of a PMOS transistor and a substrate voltage input terminal of an NMOS transistor are connected to their voltage supply terminals, respectively. The substrate voltage input terminal of the PMOS transistor in the ith (1?i?n?1) functional block and the source voltage input terminal of the NMOS transistor therein are connected bijectively with the source voltage input terminal of the PMOS transistor in the i+1th functional block and the substrate voltage input terminal of the NMOS transistor therein. In the nth functional block, the substrate voltage input terminal of the PMOS transistor and the source voltage input terminal of the NMOS transistor are connected to their voltage supply terminals, respectively.

Abstract: The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

Abstract: A digital-to-analog converter (DAC) circuit includes a least significant bit (LSB) set of capacitors, each commonly coupled to an LSB node, and a most significant bit (MSB) set of capacitors, each coupled to an MSB node. A section-coupling capacitor couples the LSB and MSB nodes. The LSB node exhibits a parasitic capacitance, which tends to introduce a jump error voltage. Digital input signals are applied to the LSB and MSB capacitors, and in response, an analog output signal is developed on the MSB node. A compensation capacitor coupled to the MSB node has a compensation capacitance selected to offset the jump error voltage introduced by the parasitic capacitance. The compensation capacitor is enabled when all of the LSB capacitors are coupled to digital input signals having a logic ‘0’ state. Otherwise, the compensation capacitor is disabled (e.g., left in a floating state).

Abstract: An electronic circuit including: a first branch, placed between two terminals of application of a D.C. voltage, including a series connection of a first constant current source, of a first diode-connected N-channel MOS transistor, of a first diode-connected P-channel MOS transistor, and of a second constant current source; a second branch, parallel to the first branch, comprising a series connection of a second N-channel MOS transistor connected as a current mirror on the first N-channel MOS transistor and of a second P-channel MOS transistor connected as a current mirror on the first P-channel transistor; and an input terminal connected between the first N-channel and P-channel transistors and an output terminal connected between the second N-channel and P-channel transistors.

Abstract: An integrated circuit with body-bias inputs coordinated by a switch at initial power application. A switch coupled to the N-well bias and P-type substrate bias lines of an integrated circuit selectively couples the substrate to ground or the substrate bias supply, depending upon the state of the bias supply lines. During power-up and the initial application of the N-well bias, the substrate is coupled to ground to prevent a leakage induce rise in the substrate potential. Upon sensing the presence of the substrate bias potential on the substrate bias line, the switch couples the substrate to the substrate bias line instead of ground. In another embodiment, a switch indirectly senses the availability of the substrate bias potential by sensing a charge pump enable signal.

Abstract: A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.

Abstract: An over-voltage tolerant input circuit has a pad. An Nwell bias circuit is electrically coupled to the pad. A current block circuit is electrically coupled to the Nwell bias circuit. The current block circuit has a control signal coupled to a gate of a transistor in a current path of the Nwell bias circuit. The current block circuit includes a logic gate having a first input coupled to the pad and a second input coupled to an over voltage signal of the Nwell bias circuit. An output of the logic gate is the control signal. An n-type transistor is coupled between the over voltage signal and the first input of the logic gate. A transistor has a gate electrically coupled to the control signal and has a drain coupled to the first input of the logic gate.

Abstract: In one embodiment, a method is provided for preventing reverse input current from flowing into a power source.

Abstract: An internal voltage generating apparatus includes: a voltage detector that detects the level of the internal voltage and outputs a fixed level detection signal and a variable level detection signal. An oscillation controller generates an oscillation enable signal according to whether the fixed level detection signal and the variable level detection signal are enabled. An internal voltage generator generates the internal voltage in response to the oscillation enable signal.

Abstract: A substrate bias is controlled such that a leakage current is minimum. A semiconductor integrated circuit device comprises a leakage detecting circuit which detects a leakage current by using leakage detecting MOSFETs, a control circuit which generates a control signal depending on an output from the leakage detecting circuit, a substrate bias generating circuit which changes a substrate bias depending on the control signal, and a controlled circuit including a MOSFET having the same characteristics as that of each of the leakage detecting MOSFETs. The leakage detecting circuit detects a substrate leakage current which includes as the substrate bias becomes deep and a subthreshold leakage current which decreases as the substrate bias becomes deep.

Abstract: Semiconductor integrated circuit apparatus and electronic apparatus having a leakage current detection circuit where arbitrarily set leakage current detection ratio does not depend on power supply voltage, temperature, or manufacturing variations, and where leakage current detection is straightforward. Semiconductor integrated circuit apparatus extracts a stable potential from the center of two NchMIS transistors, amplifies drain current of an NchMOS transistor taking this potential as a gate potential to a current value of an arbitrary ratio using current mirror circuit, makes this current value flow through NchMOS transistor with the gate and drain connected, and applies drain potential of this NchMOS transistor to the gate of leakage current detection NchMOS transistor.

Abstract: Provided is a semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation thereof. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.

Abstract: Semiconductor integrated circuit apparatus and electronic apparatus having a leakage current detection circuit where arbitrarily set leakage current detection ratio does not depend on power supply voltage, temperature, or manufacturing variations, and where leakage current detection is straightforward. Semiconductor integrated circuit apparatus extracts a stable potential from the center of two NchMIS transistors, amplifies drain current of an NchMOS transistor taking this potential as a gate potential to a current value of an arbitrary ratio using current mirror circuit, makes this current value flow through NchMOS transistor with the gate and drain connected, and applies drain potential of this NchMOS transistor to the gate of leakage current detection NchMOS transistor.

Abstract: An emitter-follower bias circuit supplying a bias voltage to the base of an amplification transistor includes: a depletion mode FET boosting a reference voltage; and an emitter-follower circuit generating the bias voltage in response to the reference voltage boosted by the depletion mode FET.

Abstract: A voltage generator that prevents latch-up includes: a charge pump circuit that is controlled by first through third enable signals, boosts an internal power voltage generated from an external power voltage, and generates first through fourth voltages; a detector that detects the first through third voltages and generates first through third flag signals that go logic high when the first through third voltages reach predetermined respective voltage levels and maintain logic low when the voltages do not reach the predetermined respective voltage levels; and a charge pump controller that receives the first through third flag signals, and generates the first through third enable signals to have the first through fourth voltages sequentially generated. The voltage generator can prevent latch-up that may occur in a boosting mode or in a normal operation mode.

Abstract: A pair of power nodes of a logic circuit that needs to output a high level at the time of standby is connected to third and fifth dummy power lines and a pair of power nodes of a logic circuit that needs to output a low level at the time of standby are connected to second and sixth dummy power lines. Fourth, third, sixth, and fifth potentials of the second, third, fifth, and sixth dummy power lines satisfy fourth potential<third potential<first potential, and sixth potential>fifth potential>second potential. With this configuration, a leakage current flowing between a substrate and a gate of a transistor that becomes on at the time of standby, and a leakage current flowing between the substrate and a drain of a transistor that becomes off at the time of standby can be reduced.

Abstract: Examples of the present invention include a metamaterial comprising a plurality of resonators disposed on a substrate, the substrate comprising a dielectric support layer and a relatively thin semiconductor layer, having a Schottky junction between at least one conducting resonator and the semiconductor layer. The properties of the resonator may be adjusted by modifying the physical extent of a depletion region associated with the Schottky junction.

Abstract: A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.

Abstract: The invention provides an analog circuit that decreases an effect of variation of a transistor. By flowing a bias current in a compensation operation, a voltage between the gate and source of the transistor to be compensated is held in a capacitor. In a normal operation, the voltage stored in the compensation operation is added to a signal voltage. As the capacitor holds the voltage according to the characteristics of the transistor to be compensated, the effect of variation can be decreased by adding the voltage stored in the capacitor to the signal voltage. Further, an analog circuit which decreases the effect of variation can be provided by applying the aforementioned basis to a differential circuit, an operational amplifier and the like.

Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Abstract: The present disclosure relates to mitigating side effects of impedance transformation circuits.

Abstract: The present invention provides a body bias coordinator for use with a transistor employing a body region. In one embodiment, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor. These embodiments improve transistor active and passive performance, permit smaller transistor sizing and reduce leakage current.

Abstract: A microprocessor according to one embodiment includes a supply node providing a core voltage, a functional block, a charge node, select logic, and substrate bias logic. The functional block has multiple power modes and includes one or more semiconductor devices and a substrate bias rail routed within the functional block and coupled to a substrate connection of at least one semiconductor device. The select logic couples the substrate bias rail to the charge node when the functional block is in a low power mode and clamps the substrate bias rail to the supply node when the functional block is in a full power mode. The substrate bias logic charges the charge node to a bias voltage at an offset voltage relative to the core voltage when the functional block is in the low power mode. Semiconductor devices may be provided to clamp or otherwise couple the bias rail.

Abstract: A power supply control circuit comprises an output transistor which controls supply of electric power to a load and a gate driving circuit which generates control signals “a” and “b” for controlling on/off of the output transistor 32 based on an external input signal. A transistor 37 discharges a gate charge of the output transistor based on the control signals “a” and “b”, when turning off the output transistor. A transistor 39 discharges more slowly than the transistor. A diode is coupled to the transistor 37 in series and which cuts off a discharge path through the transistor 37 transistor and the diode when the gate voltage of the output transistor falls to a voltage level higher than the sum of the power supply voltage Vcc and a threshold voltage of the output transistor, at a time of turning off the output transistor.

Abstract: An integrated circuit (IC) includes at least one programmable digital logic cell that includes first dedicated digital logic cell having a plurality of transistors including at least one PMOS transistor and at least one NMOS transistor configured to perform at least one digital logical function. The first dedicated digital logic cell includes a plurality of nodes including at least one input node and at least one output node that reflects performance of a digital logical function. Programmable tuning circuitry includes at least one tuning input and at least one tuning circuit output. Circuitry for coupling or decoupling the tuning input or tuning circuit output to at least one of the plurality of nodes of the first dedicated digital logical cell is provided, wherein the coupling or decoupling is operable to change the processing speed for the first reprogrammable digital logic cell.

Abstract: An example method for optimizing power consumption of digital circuits using dynamic voltage and threshold scaling (DVTS) is provided. A propagation delay of a signal through a portion of the circuit is determined and if the propagation delay does not meet a specified delay requirement, then a supply voltage and/or threshold voltage of the circuit is adjusted. Subsequently, a power consumption level of the circuit is determined and compared to previous power consumption levels. The supply and/or threshold voltage of the circuit can be readjusted to enable the circuit to meet specified power consumption requirements and the specified delay requirement, for example.

Abstract: The internal voltage generation circuit includes an internal voltage enable signal generation unit generating an internal voltage enable signal whose enable pulse width is controlled according to an external voltage. An internal voltage generation unit generates an internal voltage corresponding to a reference voltage according to the internal voltage enable signal. The internal voltage generation circuit generates an internal voltage according to an internal voltage enable signal whose enable pulse width is controlled in response to an external voltage, and thus current consumption is improved, and the internal voltage generation circuit provides a stable internal voltage.

Abstract: A semiconductor device according to the present invention comprises a first semiconductor integrated circuit 11 having a predetermined function, the first semiconductor integrated circuit outputting a required output signal, a second semiconductor integrated circuit 12 in which a plurality of MOS elements (PMOS transistor or NMOS transistor) for independently switching to and from a conducted state and a non-conducted state in accordance with a plurality of gate signals each having a different timing is provided and the plurality of MOS elements is connected in parallel to an output or an input of the first semiconductor integrated circuit, and a pulse generating circuit 13 for generating and outputting the plurality of gate signals ?i (i=1, 2, 3) each having a different timing with respect to the plurality of MOS elements in the second semiconductor integrated circuit.

Abstract: An apparatus for generating a bias voltage for an active device is disclosed, comprising a first voltage source, a capacitive element adapted to generate a charge in response to the first voltage source, and a first switching element adapted to deliver the charge to generate the bias voltage for the active device. The apparatus may comprise a controller adapted to control a capacitive element based on one or more characteristics of the active device. Alternatively, the controller may also control the capacitance of the capacitive element based on a reference voltage that is, in turn, based on one or more characteristics of the active device. The apparatus may also comprise a second voltage source adapted to generate a second voltage from which the bias voltage may be generated. The second voltage may be based on one or more characteristics of the active device. The apparatus may comprise a second switching element adapted to selectively enable and disable the active device.

Abstract: A booster circuit includes a pump circuit having a plurality of charge pump circuits for outputting a boosted voltage to a first output terminal. The booster circuit also includes a clock adjusting circuit that generates, from a first clock signal, a second clock signal for operating the charge pump circuits. A pump controlling circuit outputs the first clock signal for operating the pump circuit. A first comparator outputs a first output signal. A second comparator outputs a second output signal. A third comparator outputs a third output signal. A gradient of the boosted voltage is decreased when the first output signal is output. A frequency of the first clock signal is reduced when the second output signal is output. The third output signal is output when the boosted voltage is higher than a set value of the boosted voltage.

Abstract: A method for compensating negative bias temperature instability (NBTI) effects on a given model of transistors includes monitoring the NBTI effects on the transistors over time, determining a change in a threshold voltage of the transistors over time based on the monitoring, determining a forward bias voltage based on the change in threshold voltage, and applying the forward bias voltage to the transistors over time. The method may further include storing the monitoring results in a lookup table, and adjusting the forward bias voltage based on the lookup table. The monitoring may include emulating the NBTI effects on a system comprising a plurality of semiconductor devices in which the transistors are used.

Abstract: A semiconductor switch circuit is provided that enables current consumption to be reduced even in a conduction state. A semiconductor switch circuit 100 has P-type MOS transistors Q101 and Q102 for conduction that share a source and are connected in series between an input/output terminal 101 and input/output terminal 102, a P-type MOS transistor Q103 and N-type MOS transistor Q105 having drains connected to the gate of Q101, a P-type MOS transistor Q104 and N-type MOS transistor Q106 having drains connected to the gate of Q102, and a control terminal 103 connected to the gates of the transistors. Further semiconductor switch circuit 100 is configured with the sources and back gates of Q103 and Q104 connected to the sources of Q101 and Q102. Therefore, it is possible to switch the path between input/output terminal 101 and input/output terminal 102 between a conduction state and non-conduction state by means of voltage control by voltage value Vcont of a control signal applied to control terminal 103.

Abstract: This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.

Abstract: A new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared with the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual supply/ground bounce for the proposed scheme is also presented.

Abstract: An embodiment of a variable stage charge pump includes a plurality of pump stages. Each stage is configured to generate an intermediate boosted output voltage. A pump stage selector selects the number of charge pump stages to be coupled between an input and output terminal of the variable stage charge pump. The pump stage selector may control a plurality of switches to select the number of stages. For example, two stages may be coupled in parallel and the parallel combination coupled in series to a third stage, resulting in a two stage charge pump. For a three stage charge pump, all three stages are coupled in series.

Abstract: A method of recovering gain in a bipolar transistor includes: providing a bipolar transistor including an emitter, a collector, and a base disposed between junctions at the emitter and the collector; reverse biasing the junction disposed between the emitter and the base with an operational voltage and for an operational time period, so that a current gain ? of the transistor is degraded; idling the transistor, and generating a repair current Ibr into the base, while forward biasing the junction disposed between the emitter and the base with a first repair voltage (VEBR), and while at least partly simultaneously reverse biasing the junction disposed between the collector and the base with a second repair voltage (VCBR), for a repair time period (TR), so that the gain is at least party recovered; wherein VEBR, VCBR and TR have the proportional relationship: TR ? (??)2×exp [1/(Tam+Rth×1e×VCER], VCER=VBER+VCBR, and 1e=?×Ibr, ? is the normal current gain of the transistor, ?? is the target recovery gain of the tra

Abstract: A receiver suitable for applications that desire a common-mode voltage range from approximately 0.7V to approximately 0.9V is arranged by coupling first and second differential pair circuit architectures based on first and second current-steering schemes into the same path to generate an output signal. The receiver includes first and second differential pair circuits. The first differential pair circuit is coupled to a first current-steering path via a first port and a second current-steering path via a second port. The second differential pair circuit is coupled to the first current-steering path via a third port and the second current-steering path via a fourth port. A bridge circuit is interposed between the first and second differential pair circuits. The bridge circuit integrates the first and second current-steering paths in a single-stage of the receiver assembly. A bias signal directs the bridge circuit over a set of worst case conditions.

Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

Abstract: A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.

Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.

Abstract: The nonlinearity effect of a rectifying element is enhanced, and further a resonant circuit is used to enlarge the input amplitude. Furthermore, the rectifying efficiency of a detection rectifier circuit is enhanced, thereby allowing the gain of an amplifier circuit in the following stage to be set to a low value. Signals having mutually opposite phases are inputted to RF input terminals (101,102). The signal at the terminal (102) is then inputted to the gate of a transistor (M1) via a capacitor (C3), while the signal at the terminal (101) is then inputted, via a capacitor (C1), to a node (N1) to which the source of the transistor (M1) and the gate and drain of a transistor (M2) are connected, whereby a capacitor (C2) is charged with a half-wave voltage-doubled rectified current. DC biases are inputted to terminals (301,302). There are formed series resonant circuits (L1,C15;L2,C16). A plurality of half-wave voltage-doubled rectifier circuits (M1,M2,C1-C3,R1) are connected in cascade.

Abstract: A method and circuit for changing a threshold voltage of a transistor. The circuit includes a sense circuit coupled to a switching transistor, a circuit transistor and to one terminal of a resistor. The other terminal of the resistor is connected to a body contact. The switching transistor directs current along one of two different paths in response to an input voltage sensed by the sense circuit. When the switching transistor directs a first current along one path, the first current is steered towards the resistor and flows through the resistor in one direction and when the switching transistor directs a second current along the other path, the second current is directed towards the resistor and flows through the resistor in the opposite direction from the first current. Steering the currents varies the potential of a body with respect to the potential at the source of the circuit transistor.

Abstract: A challenge in outputting a voltage near the midpoint potential in a semiconductor switch which operates based on a low voltage power supply is to avoid a decrease in operation speed and a deterioration in accuracy of the output voltage which would be caused due to an increase in ON-resistance or occurrence of current leakage. Thus, a structure including a gray level generation circuit, an analog switch circuit and a backgate voltage control circuit is provided wherein the backgate voltage of each of an N-channel MOS transistor and a P-channel MOS transistor of the analog switch circuit to which the voltage of the gray level generation circuit is input is supplied from the backgate voltage control circuit which has an equal structure as that of the gray level generation circuit.

Abstract: A low-voltage level converter provides level conversion for multiple-supply voltages for very large scale integration (VLSI) systems. Low voltage-level down conversion is achieved at very low voltage operation for on-chip test circuitry for multiple-supply voltage systems. The converter includes an output driver PMOS FET (positive metal-oxide semiconductor field effect transistor) with its well grounded. An output NMOS FET (negative MOS FET) and an extra input pulldown NMOS FET are connected in parallel to the input of the converter. The extra input pulldown NMOS FET provides a negative gate voltage at its drain to the output driver PMOS FET gate. The negative gate voltage and grounded well significantly decrease rise time of the output signal noise pulse of the converter and virtually eliminate a negative spike voltage at the initial transition of the output pulse produced by coupling effect between the input pulse and output pulse due to Miller capacitance effect.

Abstract: In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first package-substrate connection, a second package-substrate connection, and metallization coupling the first package-substrate connection to the second package-substrate connection. The substrate is coupled to the package via the first package-substrate connection and the second package-substrate connection. The substrate includes a plurality of power domains and a power control unit. The second package-substrate connection of the package is coupled to a particular power domain of the plurality of power domains. The power control unit includes logic and a switch, where the switch includes a first terminal coupled to a voltage supply terminal, a control terminal coupled to the logic, and a second terminal coupled to the first package-substrate connection of the package.

Abstract: The semiconductor integrated circuit device includes a voltage control circuit that generates a control voltage for deactivating a field effect transistor by a gate voltage. The voltage control circuit controls a voltage so as to substantially minimize the leakage current which flows when the field effect transistor is inactive with respect to a device temperature.

Abstract: A voltage level shifting circuit (FIG. 4) has a plurality of PMOS transistors M1, M2, M3 connected in parallel for respectively driving a capacitive load CL with a selected different voltage level V1, V2 or V3. Transistors M1, M2, M3 are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V1, V2 or V3 to charge the load CL. The largest voltage transistor M3 has its body connected to its source. The lower voltage transistors M1, M2 have their bodies respectively connected to switches S1, S2, which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V3 when the transistors are placed in the OFF condition.