Abstract: A method includes providing a wide bandgap semiconductor substrate that includes a first transistor and a second transistor defined thereon. The method also includes coupling the first transistor to the second transistor. The method further includes coupling a bias circuit to the first transistor and the second transistor and forming a junction therebetween. The method also includes coupling the first transistor to a first voltage source and coupling the second transistor to a second voltage source. The first voltage source and the second voltage source are configured to define a predetermined differential input voltage.

Abstract: An integrated circuit includes a conductive pad and a substrate. The conductive pad is used to transfer a first signal. The substrate blocks a second signal from a first region of the substrate to the conductive pad. A second region of the substrate insulates a third region of the substrate from the first region. The first and third regions include a first type of semiconductor and the second region includes a second type of semiconductor. In addition, a first shadow obtained by perpendicularly projecting the third region onto a surface of the substrate overlaps with a second shadow obtained by perpendicularly projecting the conductive pad onto the surface.

Abstract: Disclosed is an apparatus and method for controlling the voltage drop across output transistors in a charge pump.

Abstract: A control circuit for substrate potential regulation for an integrated circuit device. The control circuit includes a current source configured to generate a reference current. A variable resistor is coupled to the current source. The variable resistor is configured to receive the reference current and generate a reference voltage at a node between the current source and the variable resistor. The reference voltage controls the operation of a substrate potential regulation circuit coupled to the node.

Abstract: A semiconductor device includes an internal circuit; a plurality of power switches arranged in parallel configured to supply a current to the internal circuit; an instruction circuit configured to output a instruction signal for controlling power supply to the internal circuit; a variation detection circuit configured to detect the current and to output a detection result; and a logic circuit configured to control a timing when the plurality of power switches becomes a conducting state in accordance with the detection result and the instruction signal.

Abstract: A reverse current preventing circuit of an N channel type switching MOS transistor connected between a voltage input terminal and an output terminal to control a conduction state between the voltage input terminal and the output terminal, the circuit comprises: a first MOS transistor connected between a substrate of the switching MOS transistor and a ground point; and a second MOS transistor connected between the substrate of the switching MOS transistor and a point having a piece of predetermined constant potential higher than that of the ground point, wherein the piece of predetermined constant potential higher than that of the ground point is applied to the substrate of the switching MOS transistor while the switching MOS transistor is made to be in its on-state, and ground potential is applied to the substrate of the switching MOS transistor while the switching MOS transistor is made to be in its off-state.

Abstract: An internal voltage supplying device. A reference voltage generator generates a first feedback voltage having a predetermined voltage ratio with respect to a core voltage. An adjusting mechanism adjusts the voltage ratio, and a voltage generator supplies a high voltage having a level higher than a level of the core voltage by the level of a threshold voltage or higher and maintains the level of the high voltage in accordance with the first feedback voltage.

Abstract: An integrated circuit for emulating a resistor is based on the output resistance of a non-linear circuit element, such as a transistor. In the case of a transistor, it is biased into operation in its linear region, and a voltage dependent on the ac source-drain voltage is coupled to the gate voltage, thereby to improve linearity of the drain-source resistance with respect to the drain-source voltage. This modification to the gate voltage can be used to alter the transfer function such that the drain-source resistance is no longer dependent on the drain-source voltage.

Abstract: A switched-capacitor circuit including at least one first capacitor and a circuit for switching at least one armature of the first capacitor alternately to one and the other of two terminals at a switching frequency. The circuit further includes a second capacitor connected to the first capacitor at a node; and a filtering circuit connecting the node to a virtual ground only for frequencies belonging to a frequency range.

Abstract: A leak current detection circuit that improves the accuracy for detecting a leak current in a MOS transistor without enlarging the circuit scale. The leak current detection circuit includes at least one P-channel MOS transistor which is coupled to a high potential power supply and which is normally inactivated and generates a first leak current, at least one N-channel MOS transistor which is coupled between a low potential power and at least the one P-channel MOS transistor and which is normally inactivated and generates a second leak current, and a detector which detects a potential generated at a node between the at least one P-channel MOS transistor and the at least one N-channel MOS transistor in accordance with the first and second leak currents.

Abstract: A power circuit includes a reference potential circuit, a step-up circuit, and a conversion circuit. The reference potential circuit generates a reference potential. The step-up circuit generates a desired internal potential by stepping up a power supply potential. The step-up circuit includes a comparison circuit, a differential amplifier circuit, and a switch element. The comparison circuit outputs the result of comparison between a potential and the reference potential. The differential amplifier circuit is turned on or off by the operation control signal. The switch element performs on/off control according to the operation control signal and resets the output potential of the differential amplifier circuit. The conversion circuit converts the of the operation control signal so as to make longer the on period of the differential amplifier circuit and the off period of switch element.

Abstract: A method includes receiving a set of voltages comprising at least a first voltage, a second voltage, and a third voltage and biasing a well of a transistor based on the extreme voltage of the set of voltages. Biasing the well of the transistor can include concurrently providing a first signal and a second signal based on a comparison of the first voltage and the second voltage and selectively coupling the well of the transistor to a source of the extreme voltage of the set of voltages based on the first signal, the second signal, and the third voltage. An electronic device comprises a transistor and a power switching module. The power switching module includes a set of inputs, each input configured to receive a corresponding one of a set of voltages comprising at least a first voltage, a second voltage, and a third voltage, and includes an output coupled to a well of the transistor, the output configured to provide the extreme voltage of the set of voltages.

Abstract: The present invention provides a solution to avoid the robustness problems of sub-threshold circuits by switching small parts of circuits to nominal-voltage only when they are being used, and switching them back to sub-threshold levels when the operation finishes. Such “hybrid sub-threshold” approach is capable of supporting ultra-low power operation without the disadvantages of sub-threshold circuits. Hybrid power saving mode for logic circuits provide significant power saving and fast recovery time without performance degradation.

Abstract: An embodiment of a variable stage charge pump includes a plurality of pump stages. Each stage is configured to generate an intermediate boosted output voltage. A pump stage selector selects the number of charge pump stages to be coupled between an input and output terminal of the variable stage charge pump. The pump stage selector may control a plurality of switches to select the number of stages. For example, two stages maybe coupled in parallel and the parallel combination coupled in series to a third stage, resulting in a two stage charge pump. For a three stage charge pump, all three stages are coupled in series.

Abstract: The present disclosure relates to constructing and operating a transistor or other active device with significantly reduced flicker noise.

Abstract: A reference current generating circuit with high current mirror accuracy is provided by low power supply voltage operation. The reference current generating circuit includes a cascode current mirror circuit 1 outputting mirror currents I1 and I2, and a reference current Iref, a current-voltage converter circuit 2 converting the mirror current I1 into a voltage V1, a current-voltage converter circuit 3 converting the mirror current I2 into a voltage V2, a differential amplifier 4 in which the voltage V1 is input to a first input terminal and the voltage V2 is input to a second input terminal, a voltage-current converter circuit 5 converting a voltage V3 output from the differential amplifier 4 into currents I3 and I4, and a current-voltage converter circuit 6 converting the current I3 into a voltage V4 which is output to a gate of a transistor in the cascode current mirror circuit.

Abstract: The graphene device may include an upper oxide layer on at least one embedded gate, and a graphene channel and a plurality of electrodes on the upper oxide layer. The at least one embedded gate may be formed on the substrate. The graphene channel may be formed on the plurality of electrodes, or the plurality of electrodes may be formed on the graphene channel.

Abstract: Semiconductor circuit capable of mitigating unwanted effects caused by variations in a received input signal are provided, in which a main circuit receives an input signal and comprises a first current source coupled between a first node and a first power voltage to generate a first current according to a first bias voltage. A replica circuit is coupled to the main circuit to duplicate a variation in a voltage at the first node caused by a variation in the input signal and dynamically adjusts the first bias voltage according to the duplicated variation such that the first current is maintained at a constant.

Abstract: The present disclosure relates to constructing and operating a transistor or other active device with significantly reduced flicker noise.

Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

Abstract: A swing width control circuit and a high voltage pumping circuit using the same are disclosed. The swing width control circuit includes a swing width controller for receiving a first pumping signal having a first swing width and generating a second pumping signal having a second swing width larger than the first swing width of the first pumping signal, in accordance with a level of a supply voltage to pump or precharge a voltage of a specific node, and a swing width holding device for maintaining a swing width of the specific node to be equal to the second swing width of the second pumping signal.

Abstract: Semiconductor circuit capable of mitigating unwanted effects caused by variations in a received input signal are provided, in which a main circuit receives an input signal and comprises a first current source coupled between a first node and a first power voltage to generate a first current according to a first bias voltage. A replica circuit is coupled to the main circuit to duplicate a variation in a voltage at the first node caused by a variation in the input signal and dynamically adjusts the first bias voltage according to the duplicated variation such that the first current is maintained at a constant.

Abstract: A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.

Abstract: A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

Abstract: A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.

Abstract: A booster circuit includes a pump circuit having a plurality of charge pump circuits for outputting a boosted voltage to a first output terminal. The booster circuit also includes a clock adjusting circuit that generates, from a first clock signal, a second clock signal for operating the charge pump circuits. A pump controlling circuit outputs the first clock signal for operating the pump circuit. A first comparator outputs a first output signal. A second comparator outputs a second output signal. A third comparator outputs a third output signal. A gradient of the boosted voltage is decreased when the first output signal is output. A frequency of the first clock signal is reduced when the second output signal is output. The third output signal is output when the boosted voltage is higher than a set value of the boosted voltage.

Abstract: A solid-state power distribution system having a first solid-state switching device (SSSD) and a second solid-state switching device (SSSD) for distributing power from an AC power source to a load includes a leakage current reduction circuit for reducing leakage current generated by the SSSDs when Off. When the first and second SSSDs are Off, the leakage current reduction circuit provides a positive bias voltage across controlled terminals of the first SSSD and a negative bias voltage across controlled terminals of the second SSSD.

Abstract: Low leakage diodes and methods of forming the same are disclosed. In one embodiment an apparatus includes a designed or parasitic bipolar transistor having an emitter, a base and a collector. The bipolar transistor is configured to operate as a diode, the diode having reverse-biased and forward-biased modes of operation. The emitter and base operate as first and second terminals of the diode, respectively. The collector is configured to receive a collector bias voltage, which is controlled relative to a voltage of the emitter to reduce a diffusion leakage current of the diode when the diode is in the reverse-biased mode of operation.

Abstract: In a process automation controller, a universal digital input module is provided. The universal digital input module comprises a plurality of digital input channels, each channel to sink a first current at a first voltage level associated with an input having a digital high value and to sink a second current at a second voltage level associated with the input having a digital high value, wherein the first current is greater than the second current and wherein the first voltage is less than the second voltage.

Abstract: The present invention relates to a circuit arrangement and method for controlling power supply in an integrated circuit wherein at least one working parameter of at least one electrically isolated circuit region (10) is monitored, and the conductivity of a variable resistor means is locally controlled so as to individually adjust power supply for each of said at least two electrically isolated circuit regions (10) based on the at least one monitored working parameter. Thereby, a fast and simple control functionality with low area overhead can be provided.

Abstract: A low noise current source includes first and second voltage input terminals. The current source further includes an amplifying device having an input terminal and an output terminal, where the output terminal is coupled to the second voltage input terminal via a load. The current source also includes a bias circuit coupled between the first voltage input terminal, the second voltage input terminal, and the input terminal. The current source additionally includes a first bypass circuit coupled between the first voltage input terminal and the input terminal, where the first bypass circuit configured to provide a substantially high electrical resistance and substantially no electrical impedance between the first voltage input terminal and the input terminal.

Abstract: A leakage current suppressing circuit includes a bias generating unit and a switch unit. The bias generating unit is adapted to be coupled to a power source and an output terminal, and generates a bias voltage substantially equal to a voltage at the power source when the power source is turned on, and substantially equal to a voltage at the output terminal when the power source is turned off. The switch unit includes a first P-type transistor having a first terminal adapted to be coupled to the power source, a second terminal adapted to be coupled to the output terminal, a gate terminal, and a body terminal coupled to the bias generating unit for receiving the bias voltage therefrom.

Abstract: A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.

Abstract: A voltage booster for generating a boosted voltage, including a charge pump adapted to generate the boosted voltage starting from a supply voltage by a transfer of electric charge controlled by at least one oscillating signal having an oscillation frequency; an oscillator for providing the oscillating signal; and a regulation circuit arranged to receive and perform a comparison of a voltage related to the boosted voltage and a reference voltage, and adapted to provide at least one regulation signal indicative of a result of said comparison, wherein said regulation signal is fed to the oscillator to control said oscillation frequency. The regulation circuit is adapted to cause the at least one regulation signal take one among a plurality of discrete values, depending on the result of the comparison, so that the oscillation frequency of the at least one periodical signal accordingly can take one among a plurality of discrete oscillation frequency values.

Abstract: An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching terminals are electrically over stressed. As output related terminals experience switching related voltage excursions, the well-bias selectors select alternate terminals to continue selection of the respective highest or lowest voltages available and provide correct well-biasing conditions. Voltage dividers are incorporated to generate well-biasing control voltages.

Abstract: The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first transistor configured for connection to a supply voltage via a first terminal; a register connected to the first transistor; a second transistor in parallel with a resistor, wherein the second transistor is configured for connection to the first terminal, with a gate of the second transistor configured for connection to an output of the register; and wherein the second transistor is configured for connection to a second terminal, the second transistor having a state that depends on a status of the register.

Abstract: A substrate bias circuit may measure a leakage current of a baseline device, compare the leakage current with a reference current, and based on the comparison, adjust a reverse body bias voltage applied to a body of the baseline device.

Abstract: An integrated circuit with body-bias inputs coordinated by a switch at initial power application. A switch coupled to the N-well bias and P-type substrate bias lines of an integrated circuit selectively couples the substrate to ground or the substrate bias supply, depending upon the state of the bias supply lines. During power-up and the initial application of the N-well bias, the substrate is coupled to ground to prevent a leakage induce rise in the substrate potential. Upon sensing the presence of the substrate bias potential on the substrate bias line, the switch couples the substrate to the substrate bias line instead of ground. In another embodiment, a switch indirectly senses the availability of the substrate bias potential by sensing a charge pump enable signal.

Abstract: A thin film transistor is provided that includes a gate electrode, a source electrode, and a drain electrode, an oxide semiconductor active layer formed over the gate electrode, a fixed charge storage layer formed over a portion of the oxide semiconductor active layer, and a fixed charge control electrode formed over the fixed charged storage layer.

Abstract: A bias circuit according to the present invention includes: a transistor for supplying a bias current from the emitter of the transistor; an emitter potential generating device for supplying a potential to the emitter of the transistor; a switch element; and a voltage supply circuit for supplying a base voltage to the base of the transistor in response to the on/off of the switch element, wherein the emitter potential generating device generates a potential causing a potential difference between the base and emitter of the transistor to fall below a saturation voltage at the junction of the transistor, even in the case where the base of the transistor is fed with a voltage not lower the saturation voltage at the junction of the transistor.

Abstract: A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.

Abstract: According to an example embodiment, a chip includes a plurality of circuit blocks, a power switch unit configured to supply power to the plurality of circuit blocks, and a power switch controller configured to control the power switch unit in response to an external control signal. The external control signal selectively control supply of power to at least one circuit block of the plurality of circuit blocks.

Abstract: A RF transceiver includes an antenna, a receiver, a baseband circuit, a transmitter, and a T/R switch circuit. The T/R switch circuit is used for coupling the antenna and the receiver or coupling the antenna and the transmitter. The T/R switch circuit is coupled to the baseband circuit so as to receive biases provided from the baseband circuit. The T/R switch circuit includes four transistors and a power detector. The power detector detects the power of the output signal of the T/R switch circuit, so that the baseband circuit can adjust biases provided to the T/R switch circuit according to the power of the output signal.

Abstract: A semiconductor integrated circuit includes: an internal circuit; a detecting circuit which detects an element characteristic of the internal circuit; a calculating circuit which calculates a first consumption energy consumed when a power gating operation is performed on a task processed by the internal circuit and a second consumption energy consumed when an operation of reducing a voltage and a frequency is performed in accordance with the element characteristic; and a switching circuit which performs the power gating operation on the internal circuit when the first consumption energy is smaller than the second consumption energy and performs the operation of reducing a voltage and a frequency when the second consumption energy is smaller than the first consumption energy.

Abstract: Switches with improved biasing and having better isolation and reliability are described. In an exemplary design, a switch is implemented with a set of transistors, a set of resistors, and an additional resistor. The set of transistors is coupled in a stacked configuration, receives an input signal, and provides an output signal. The set of resistors is coupled to the gates of the set of transistors. The additional resistor is coupled to the set of resistors and receives a control signal for the set of transistors. The resistors reduce signal loss through parasitic capacitances of the transistors when they are turned on. The resistors also help split the signal swing of the input signal approximately evenly across the transistors when they are turned off, which may improve reliability of the transistors. The switch may be used in a switchplexer, a power amplifier (PA) module, etc.

Abstract: A low dropout voltage regulator (LDO) includes a bias voltage generator, a differential error amplifier, an output driver, a controlled active load, a Double Ended Cascode Miller compensation block. The bias voltage generator produces a plurality of bias voltages. The differential error amplifier produces a differential output voltage based on the difference between a reference voltage and a function of the output voltage. The input terminal of the output driver is coupled to one output of the differential error amplifier. The substrate terminal of the output driver is capacitively coupled to the output node and resistively coupled to the input supply node. The controlled active load is coupled to the output of the output driver, and its control terminal is coupled to a function of the second output of the differential error amplifier.

Abstract: An internal voltage generator of a semiconductor device includes a charge pumping unit for performing a charge pumping operation on the basis of the voltage level of a reference voltage to generate a charge pumped voltage having a voltage level higher than the external power supply voltage; and an internal voltage generating unit for performing a charge pumping operation on the basis of an internal voltage level that is linear with respect to a temperature change in a first temperature range to generate an internal voltage, and to perform a charge pumping operation on the basis of an internal voltage clamping level that is constant independent of a temperature change in a second temperature range to generate the internal voltage.

Abstract: A device capable of controlling a supply voltage and a supply frequency using information of a manufacturing process variation includes a data storage device storing data indicating performance of the device, a decoder decoding the data stored in the data storage device and outputting decoded data, and a frequency control block outputting a frequency controlled clock signal in response to the decoded data output from the decoder. The device further includes a voltage control block outputting a level controlled supply voltage in response to the decoded data. The voltage control block outputs a body bias control voltage controlling a body bias voltage of at least one of a plurality of transistors embodied in the semiconductor device in response to the decoded data. The performance is operational speed of the device or leakage current of the semiconductor device.

Abstract: Techniques of operating a charge pump are described. The charge pump is connectable to receive a clock signal and a regulating voltage and provide an output voltage. The charge pump can have one or multiple stages, each of the stages will include a capacitor. During the charging phase, the regulating voltage is used to regulate the potential of the capacitor's bottom plate. During the boosting phase, the capacitor's top plate is connected to supply the output for the stage and the bottom plate is connected to receive the stage's input. Each stage will also have a set of switching elements, allowing the capacitor to be alternately connected in the charging and boosting phases. For the first stage, the input is derived from the clock signal, and for any subsequent stages, the input will be the output of the preceding stage. The last stage provides the output voltage of the pump.

Abstract: A system and method are provided for biasing transistor switches in a semiconductor based high power switch. Off-state Vgsd biasing for the off transistor switches is based upon acceptable levels of spurious harmonic emissions and linearity.