Abstract: A voltage generator comprises a first booster that generates a first high voltage, and a second booster that generates a second high voltage by boosting an external voltage. The first booster comprises a comparator that controls a boosting operation with reference to the fed back first high voltage and uses the second high voltage as a drive voltage.

Abstract: Various embodiments of a semiconductor apparatus are disclosed. In one exemplary embodiment, the semiconductor apparatus may include an internal voltage generation unit configured to generate an internal voltage having a voltage level corresponding to a code value of a voltage control code, a voltage comparison unit configured to compare a voltage level of a target voltage with a voltage level of the internal voltage, and a voltage control code generation unit configured to adjust the code value of the voltage control code based on the comparison result of the voltage comparison unit.

Abstract: A system includes a bandgap temperature sensor to generate multiple base-emitter voltages. The system also include a controller to detect the base-emitter voltages generated by the bandgap temperature sensor and to generate a bandgap reference voltage according to the multiple base-emitter voltage signals, the bandgap reference voltage having a voltage level that remains substantially constant relative to environmental temperature variations.

Abstract: A method and circuitry for adjusting the delay of a variable delay line (VDL) in a delay locked loop (DLL) or other delay element or subcircuit on an integrated circuit is disclosed. Such delay circuitry will inherently have a delay which is a function of temperature. In accordance with embodiments of the invention, such temperature-dependent delays are compensated for by adjusting the power supply voltage of the VDL, delay element, or subcircuit. Specifically, a temperature sensing stage is used to sense the temperature of the integrated circuit, and hence the VDL, delay element, or subcircuit. Information concerning the sensed temperature is sent to a regulator which derives the local power supply voltage from the master power supply voltage, Vcc, of the integrated circuit.

Abstract: According to an embodiment, a semiconductor device includes a functional circuit, an electric current measurement circuit and a control circuit. The functional circuit operates with a supplied electric power. The electric current measurement circuit is configured to measure an electric current based on the electric power. The control circuit is configured to control an operation of the functional circuit in accordance with operation information about the functional circuit and the measured electric current.

Abstract: The present invention provides a reference voltage circuit making use of a non-volatile and non-modifiable storage of an electric charge. A tunable transformation module is adapted to transform a constant voltage corresponding to the constant stored charge into an output reference voltage. Further, a control loop provides tuning of the transformation module by means of an external calibration module with respect to a high precision reference voltage source. During a calibration procedure the transformation module is tuned in such a way that the output reference voltage equals the high precision reference voltage. After disconnecting reference voltage electronic circuit and calibration module, the output reference voltage is governed by the charge stored by means of the non-volatile storage and by the configuration of the tunable transformation module. It remains constant and accurate with respect to time and temperature and consumes only a minimum of electric current.

Abstract: A temperature independent reference circuit includes first and second bipolar transistors with commonly coupled bases. First and second resistors are coupled in series between the emitter of the second bipolar transistor and ground. The first and second resistors have first and second resistance values, R1 and R2, and third and second temperature coefficients, TC3 and TC2, respectively. The resistance values being such that a temperature coefficient of a difference between the base-emitter voltages of the first and second bipolar transistors, TC1, is substantially equal to TC2×(R2/(R1+R2))+TC3×(R1/(R1+R2)), resulting in a reference current flowing through each of the first and second bipolar transistors that is substantially constant over temperature. A third resistor coupled between a node and the collector of the second bipolar transistor has a value such that a reference voltage generated at the node is substantially constant over temperature.

Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.

Abstract: The voltage generation circuit having a standard voltage generation circuit, a reference voltage, a minimum voltage setting circuit, and a voltage setting circuit that gradually sets voltage by switching a plurality of the gate transistors to switch a combination of resistive elements. The voltage generation circuit includes a differential amplifier that has one input terminal connected to the reference voltage generated by the standard voltage generation circuit and another input terminal connected to the minimum voltage setting circuit. The differential amplifier has an output node showing the result of a difference voltage of the inputs. The voltage generation circuit includes a pump control circuit that outputs a control signal controlling a charge-pump motion, based on the differential voltage, and a charge pump circuit that sets up and outputs the voltage by the control signal.

Abstract: A low noise current source includes first and second voltage input terminals. The current source further includes an amplifying device having an input terminal and an output terminal, where the output terminal is coupled to the second voltage input terminal via a load. The current source also includes a bias circuit coupled between the first voltage input terminal, the second voltage input terminal, and the input terminal. The current source additionally includes a first bypass circuit coupled between the first voltage input terminal and the input terminal, where the first bypass circuit configured to provide a substantially high electrical resistance and substantially no electrical impedance between the first voltage input terminal and the input terminal.

Abstract: A semiconductor memory apparatus includes a initialization signal generating unit configured to vary a voltage level of an external voltage in response to a detection signal, the external voltage enables a power-up signal, an internal voltage generating unit configured to produce an internal voltage, the internal voltage generating unit is initialized by the power-up signal, and a detection signal generating unit configured to produce the detection signal in response to a voltage level of the internal voltage.

Abstract: A control circuit for a transistor arrangement comprises a monitoring arrangement (60) for monitoring the current flow and voltage across the transistor arrangement (50) and means (62) for determining if the current and voltage values define an operating point which falls within a stable operating region. The stable operating region comprises a region having a boundary (30) which comprises an electro-thermal instability line.

Abstract: A self-oscillating switch circuit for amplitude modulation dimming for dimming a LED load. The self-oscillating switch circuit comprises a high-power input terminal (S2) for supplying a first power to the load and a low-power input terminal (S1) for supplying a second power to the load. The switch circuit further comprises a power switch semi-conductor device (Q1) configured for controlling a load current from at least one of the high-power input terminal (S2) and the low-power input terminal (S1) to the output terminal. A control semi-conductor device (Q2) is configured to control the power switch semi-conductor device (Q1) in response to a sensing voltage.

Abstract: A semiconductor device includes an internal circuit and an internal voltage generation circuit which generates an internal voltage stabilized with respect to a variation of the power supply voltage supplied from the outside and supplies the internal voltage to the internal circuit. The internal voltage generation circuit performs control so that when the power supply voltage rises to exceed a predetermined value, an operation of stabilizing the internal voltage is stopped to cause the internal voltage to increase with the rise of the power supply voltage.

Abstract: A semiconductor device includes a first internal voltage driving unit configured to drive an internal voltage, a second internal voltage driving unit configured to drive the internal voltage in an operation period corresponding to an enable signal, a current amount detection unit configured to detect amount of current supplied by the first internal voltage driving unit, and a current amount comparison unit configured to compare the amount of detected current by the current amount detection unit with amount of a reference current, and determine whether or not to activate the enable signal in response to a comparison result.

Abstract: A voltage clamping circuit includes a current source having a fixed current source and a variable current source and a variable resistor receiving current from the current source. The variable resistor varies its resistance in response to an environmental operating condition. The voltage clamping circuit also includes an amplifier configured to compare a sensor node voltage with a reference voltage, the sensor node voltage being in communication with the voltage drop across the variable resistor. The amplifier is configured and connected to provide a control output to control the variable current source to modify current output from the variable current source to at least in part prevent the sensor node voltage from exceeding a reference voltage when certain operating conditions are present.

Abstract: A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.

Abstract: The electronic circuit comprises a functional module (10), a condition signaling module (20), a reference module (30) and a control circuit (40). The condition signaling module (20) generates an indication signal (Imeas) indicative for PVT conditions local to the functional module. The PVT conditions comprise a set of conditions relevant for a module comprising at least one of a voltage supplied to said module, a temperature within an area occupied by said module and the process conditions relevant for said area The reference module (30) generates a reference signal (Iref) having a value that is substantially independent of said PVT-conditions. The control circuit (40) compares the indication signal (Imeas) and the reference signal (Iref), and for generating a control signal (pvt<1>, . . . , pvt<n>) for the functional module.

Abstract: A current control circuit in accordance an exemplary aspect of the present invention includes a first transistor that controls a current flowing to a load, a first resistor through which a current flows according to a current flowing through the first transistor, a control signal generation circuit that generates a control signal used to control the first transistor based on a comparison voltage and a predetermined reference voltage, the comparison voltage being determined based on a resistance value of the first resistor and a current flowing through the first resistor, and a reference voltage generation circuit that generates the reference voltage, the reference voltage generation circuit including a constant current source and a second resistor connected in series with the constant current source.

Abstract: An internal voltage generation circuit includes a driving control signal generation unit configured to receive a temperature signal enabled when the internal temperature is below a preset temperature and generate first and second driving control signals, and an internal voltage generation unit configured to receive the first and second driving control signals and generate an internal voltage.

Abstract: An integrated circuit includes an electronic circuit and a device for adjustment of the operating parameter value of the electronic circuit. The electronic circuit comprises a resistive stage. The device comprises a first circuit portion adapted to adjust said operating parameter when the device is active and the electronic circuit is inactive, and adapted to be inactive when the electronic circuit is active, and a second circuit portion adapted to determine the active or inactive state of the device in response to the value of an external control signal. The integrated circuit comprises a first external terminal for the connection to ground, a second external terminal for inputting said control signal, a further external terminal for inputting a further external signal and a deactivation circuit driven by said further external signal to deactivate the electronic circuit when the device is active.

Abstract: Circuits, methods, and apparatus that provide for the powering of active components in connector inserts at each end of a cable may in various ways. For example, where a host is coupled to a device that is not self-powered, the host may provide power for circuitry at each end of the cable. In various embodiments of the present invention, the device may request higher voltage from the host, such that more power can be delivered. In these cases, the device may regulate the voltage received from the host to a lower voltage, and then provide the lower voltage to circuitry at one or both ends of the cable. Where the host is connected to a device that is self-powered, the host and the self-powered device may power their respective connector insert circuits.

Abstract: A power supply voltage reset circuit, provided in an apparatus having an internal circuit capable of adjusting an internal power supply voltage, for resetting the internal circuit when a power supply voltage of the apparatus rises, and includes: a unit that generates an internal power supply voltage reference signal and changes a signal level thereof; a unit that generates an internal reference voltage to be a reference level in generating a reset signal for the internal circuit at a time of rising of the power supply voltage; a unit that generates a power-on adjustment voltage which rises later than the internal reference voltage at the time of rising of the power supply voltage and becomes greater than the internal reference voltage after a predetermined time passes; and a unit that generates the reset signal by comparing the internal reference voltage with the power-on adjustment voltage.

Abstract: A first pump circuit generates a first voltage for decreasing the distance between primary electrodes. The first voltage is limited to a predetermined limit by a first limiter circuit. A second pump circuit generates a second voltage for keeping the distance between the primary electrodes constant. A third pump circuit generates the second voltage and has a supplying capacity smaller than the first one. The second voltage is limited by second and third limiter circuits. A ripple capacitor is charged up to the second voltage by the second pump circuit and the second limiter circuit within a period of time the first voltage is being generated. When a supplying voltage of the first pump circuit reaches to the first voltage, and a deformation stops, the second voltage is supplied by the third pump circuit and the third limiter circuit instead of the second pump circuit and the second limiter circuit.

Abstract: In one embodiment, to maintain the operation stability of a semiconductor device even when an external voltage changes. An input signal discrimination unit operates with a power supply potential supplied from a first power supply line VDDI. The input signal discrimination unit compares an input signal VIN with a reference potential Vref. The comparison result is inverted into a signal V0 by an inverter INV1. A power supply sensor circuit monitors the potential of the first power supply line VDDI. If an external potential VDDI falls below a reference potential VX, the power supply sensor circuit turns on a second current source. When the second current source is turned on, an operating current is supplied to a discrimination unit from the second current source as well as a first current source.

Abstract: N-channel field effect transistor Proportional To Absolute Temperature (N-PTAT) cells are connected to a first supply voltage and P-channel field effect transistor Proportional To Absolute Temperature (P-PTAT) cells are connected to a second supply voltage. A coupling circuit connects at least one of the N-PTAT cells to at least one of the P-PTAT cells. These circuits can be used to provide a voltage reference and/or a supply voltage level detector. Related operating methods are also described.

Abstract: An integrated circuit comprising a plurality of functional blocks, each functional block being operative to cause one or more power consuming events, each power consuming event being associated with a respective weight. The integrated circuit also comprises at least one accumulation block for monitoring the functional blocks over a time window and generating a weighted count of the number of occurrences of each power consuming event within the time window; and a power calculation module for calculating a runtime power consumption estimate over the time window using the weighted count. The weighted count may comprise a sum of products of each one of the power consuming events by its respective weight. Calculating the runtime power consumption estimate may comprise averaging the weighted count over the time window to generate a dynamic power estimate, calculating a leakage power estimate over the time window, and summing the dynamic power estimate with the leakage power estimate.

Abstract: In one embodiment of the invention, a circuit arrangement is provided. The circuit arrangement includes a plurality of differential amplifiers, coupled in parallel, including at least a first differential amplifier and a second differential amplifier. Each differential amplifier includes an adjustable current control circuit coupled to limit a tail current passing through the differential amplifier.

Abstract: A multi-level transmitter circuit with substantially constant output impedance has a capacitive transducer connected between a voltage input and ground. A first voltage path connects the voltage input to a first positive voltage source. The first voltage path is controlled by a first control signal. A second voltage path connects the voltage input to a second positive voltage source, less than the first positive voltage source. The second voltage path passes through a diode and is controlled by a second control signal. A third voltage path connects the voltage input to a third voltage source, less than ground, and is controlled by the second control signal. The impedance at the voltage input during the first control signal is substantially the same as the impedance at the voltage input during the second control signal.

Abstract: A method and apparatus are described for providing a current mirror type high voltage switching circuit (60) having a reference branch (M2, M3, R1) and a tracking branch (M1, M5), where the output peak current is limited by adding an additional branch (M4, M6) to the current mirror circuit which includes an additional mirror transistor (M4) and cascode transistor (M6), and where over voltage protection is provided by including a shut-off circuit (Q1, Q2) which turns “OFF” the cascode transistors (M5-M8) whenever the output voltage (Vout) exceeds the first reference voltage (Vbat) by a predetermined amount.

Abstract: A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.

Abstract: An exemplary gate driving circuit is adapted for receiving an external gate power supply voltage and an external control signal, sequentially generating multiple internal shift data signal groups and thereby sequentially outputting multiple gate signals. Each of the internal shift data signal groups includes multiple sequentially-generated internal shift data signals. The gate driving circuit includes multiple gate signal generating modules. Each of the gate signal generating modules includes a voltage modulation circuit and a gate output buffer circuit. The voltage modulation circuit modulates the external gate power supply voltage according to a corresponding one of the internal shift data signal groups and the external control signal, and thereby a modulated voltage signal is obtained. The gate output buffer circuit includes a plurality of parallel-coupled output stages. The output stages output the modulated voltage signal as a part of the gate signals during the output stages being sequentially enabled.

Abstract: A driver device for suppression audible transients of an audio amplifier includes an amplifier for receiving an audio signal and a bias circuit configured to quickly generate a voltage level for biasing the amplifier, wherein the voltage level is maintained even if the driver device is powered off. The bias circuit may include a CMOS inverter having a negative feedback that has a standby current of less than 100 nA. The bias circuit further includes a buffer for rapidly charging an external capacitor. The buffer may change to a high impedance state rapidly when the power supply is disconnected.

Abstract: A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay. A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined. The circuit design is synthesized such that the synthesized design includes the voltage scaling value. The synthesized design specifies setting an operating voltage to a value of a startup voltage value scaled by the voltage scaling value.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: Some embodiments regard a circuit comprising: a high voltage transistor providing a resistance; an amplifier configured to receive a current and to convert the current to a first voltage that is used in a loop creating the current; and an automatic level control circuit that, based on an AC amplitude of the first voltage, adjusts a second voltage at a gate of the high voltage transistor and thereby adjusts the resistance and the first voltage; wherein the automatic level control circuit is configured to adjust the first voltage toward the first reference voltage if the first voltage differs from a first reference voltage.

Abstract: A reference voltage generation circuit comprises: a first depletion mode FET; a second depletion mode FET; a first resistor; a first bipolar transistor; a second resistor; a second bipolar transistor; a third bipolar transistor; a third resistor; a third depletion mode FET having its drain connected to a second end of the first resistor and to the collector of the first bipolar transistor; and a fourth bipolar transistor having its base and collector connected to the gate and the source of the third depletion mode FET, and its emitter grounded, wherein source voltage of the second depletion mode FET is output as a reference voltage.

Abstract: An integrated circuit includes an energy controller that generates a power supply voltage level for the integrated circuit based on a desired target frequency value for the integrated circuit. The energy controller configures a programmable hardware process sensor based on the power supply voltage level such that the programmable hardware process sensor is capable of mimicking the electrical characteristics of a predetermined critical path associated with the integrated circuit when operating at the power supply voltage level. By monitoring the frequency of the programmable hardware process sensor over a period of time, the energy controller can compare the monitored frequency to an expected value and determine whether the power supply voltage level can be adjusted or whether it should be maintained.

Abstract: A power supply regulator circuit uses a feedback loop to control current through a first output transistor from a power supply input to a regulated power supply output. The first output transistor is included in an integrated circuit. In order to avoid heating of the integrated circuit in excess of an acceptable level due to permanent supply of a high current through the first transistor, current through a second output transistor in parallel with the first transistor, but outside the integrated circuit is raised when it is detected that the current through the first output transistor exceeds a threshold level. The second output transistor outside the integrated circuit serves to take over supply of a part of the power supply current from first output transistor inside integrated circuit, when long term supply of that part from first output transistor would lead to undesirable heating of the integrated circuit. During a limited time interval a first transistor current above the threshold level is acceptable.

Abstract: A downconversion mixer includes a configurable gate or bulk bias voltage to allow calibration and correction of device offsets. Calibration may be performed on the configurable bias voltages to minimize IM2 distortion in the mixer. The techniques have minimal impact on voltage headroom, impose no requirement for a signal path to be phase-matched with a calibration path, and are particularly well-suited for passive mixers.

Abstract: A reference voltage generator includes: a reference voltage source 1 that generates a direct-current voltage that is used as a reference; a low-pass filter 2 that is connected to an output node of the reference voltage source; a first voltage buffer circuit 10 with an input terminal to which the output node of the reference voltage source is connected and an output terminal to which an output node of the low-pass filter is connected, which has a voltage gain of one time; and a hysteresis comparator 11 with one input terminal to which the output node of the reference voltage source is connected and an other input terminal to which the output node of the low-pass filter is connected. At start-up, during a time period in which a voltage difference between an output of the reference voltage source and an output of the low-pass filter exceeds a predetermined value, an output impedance of the first voltage buffer circuit is controlled based on an output signal of the hysteresis comparator.

Abstract: A current source device that cuts off an output current when stopped and obtains a desired output current upon start-up includes a first circuit having a first FET and resistors in series, a second circuit having second and third FETs in series with a point between the second and third FETs and a gate of the third FET connected, a drive circuit supplying a common drive voltage to gates of the first and second FETs, and first and second current source circuits responsive to first and second drive voltages that are gate voltages of the second and third FETs. The first and second current source circuits respectively include first and second current source FETs having the first and second drive voltages as gate voltages, and a start-up circuit changing the first and second drive voltages forcedly when the first and second current source FETs are made conductive.

Abstract: A reference voltage circuit that obtains a precisely constant voltage by compensating a temperature variation of a reference voltage circuit using band gap voltage. A p-type MOS transistor (PNP) outputs a reference voltage according to a control voltage, and provides respective PNPs having diode connections with currents corresponding to the reference voltage. A temperature compensation unit adds compensation currents proportional to the second power of absolute current to currents flowing in the respective PNPs, so that both voltages generated corresponding to the currents flowing in the respective PNPs become the same in the case where the band gap unit has temperature characteristics including a peak value. The band gap unit has a differential amplifier for outputting the control voltage. In the case where the band gap unit has a bottom value, the compensation unit subtracts the above compensation currents from the currents flowing in the respective PNPs.

Abstract: An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock.

Abstract: Methods and apparatuses provide voltage regulation for a processor. Control or configuration parameters for a voltage regulator (VR) are provided digitally over a configuration bus to a VR controller. The parameters may be provided directly from a storage element, or via a processing element or processor core. Based in whole or in part on the parameters, the VR controller provides an output control signal to affect a power output from a power converter to the processing element. In one embodiment, the VR controller is integrated onto the same IC as the processing element.

Abstract: Multistage charge pumps with diode loss compensation are disclosed. In one example, a pre-regulated charge pump to generate a voltage is described. The example pre-regulated charge pump includes a charge pump having a plurality of stages and one or more diodes. The stages are configured to generate an output voltage at an output terminal based on an input voltage and a number of the multiplier stages. The example pre-regulated charge pump also includes a pre-regulator stage configured to adjust the input voltage to remove dependency on supply voltage variation. The pre-regulator includes a feedback diode configured to compensate for one or more voltage drops associated with the one or more charge pump diodes.

Abstract: The invention describes a charge-pump circuit (1, 1?) comprising a supply voltage input node (10) for applying an input voltage (Uin) to be boosted, a boosted voltage output node (11) for outputting a boosted voltage (Uout), and a plurality of transistor stages connected in series between the supply voltage input node (10) and the boosted voltage output node (11), wherein at least one transistor stage comprises a multiple-gate transistor (D1, . . . , D5), which transistor (D1, . . . , D5) comprises at least two gates, of which one is a first gate (G) for switching the transistor (D1, . . . , D5) on or off according to a voltage applied to the first gate (G), and one is an additional second gate (Gi) for controlling the threshold voltage of the multiple-gate transistor (D1, . . . , D5), independently of the first gate (G), according to a control voltage (?1, ?2) applied to the second gate (Gi).

Abstract: A semiconductor integrated circuit includes a first ground voltage pad, a second ground voltage pad, an internal voltage generation unit, and a division unit. The first ground voltage pad is configured to receive a first ground voltage. The second ground voltage pad is configured to receive a second ground voltage. The internal voltage generation unit includes a comparison unit configured to compare a reference voltage with a feedback voltage by using the first ground voltage, and a driving unit configured to drive an internal voltage terminal in response to an output signal of the comparison unit. The division unit is coupled between the internal voltage terminal and the second ground voltage pad, and configured to divide a voltage of the internal voltage pad and generate the feedback voltage supplied to the internal voltage generation unit.

Abstract: An internal voltage generator of a semiconductor integrated circuit includes a comparison unit configured to compare a reference voltage with a feedback voltage, a driving unit configured to drive an internal voltage terminal in response to an output signal of the comparison unit, and a feedback unit configured to divide a voltage of the internal voltage terminal according to a division ratio adjustable in response to a control signal and output a division voltage as the feedback voltage.

Abstract: Embodiments of the present invention are related to circuits and methods for generating a reference current (Idc). In an embodiment, a voltage-to-current converter circuit is used to generate the reference current (Idc) in dependence on a reference voltage (Vref) and a precision resistor (R0), wherein Idc=Vref/R0. A capacitor (C0) is used to shunt noise that couples into the voltage-to-current converter. A frequency dependent feedback network is used to compensate for instabilities introduced by the capacitor (C0). The capacitor (C0) can be used to shunt noise that couples into the voltage-to-current converter by connecting the capacitor (C0) in parallel with the precision resistor (R0). The frequency dependent feedback network can be used to compensate for instabilities introduced by the capacitor (C0) by connecting the frequency dependent feedback network between a feedback terminal of an amplifier of the voltage-to-current converter circuit and a terminal of the capacitor (C0).