Abstract: According to one embodiment, a semiconductor integrated circuit device is provided. The semiconductor integrated circuit device is provided with a plurality of booster circuits, a regulator and a plurality of switches. Each of the booster circuit receives an input voltage, boosts the input voltage, and generates a boosted voltage having a different value. The regulator is capable of generating a plurality of dropped voltages by dropping each boosted voltage from the booster circuits. The switches are connected between the booster circuits and the regulator. The switches provide the boosted voltages outputted from the booster circuits selectively to the regulator as a power-supply voltage.

Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.

Abstract: The disclosure relates to a method for detecting an attack in an electronic microcircuit, comprising: forming the microcircuit in a substrate, forming in the substrate a first well electrically isolated from the substrate, by a second well and an embedded well, forming in the first and second wells a data processing circuit comprising a ground terminal formed in the first well and a power supply terminal formed in the second well, and activating a detection signal when a voltage at the ground or power supply terminal of the data processing circuit crosses a threshold voltage.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: Information technology equipment includes a circuit block, a local power source line for supplying a power source to the circuit block, a power source line, and a first transistor which is provided with a source-drain path thereof between the power source line and the local power source line, in which the first transistor is controlled to an OFF state in a first state, and is controlled to an ON state in a second state, and when the first state is shifted to the second state, the first transistor is controlled such that a rate of changing a current flowing in the source-drain path of the first transistor does not exceed a predetermined value.

Abstract: The disclosure provides methods and apparatuses of measuring a temperature. A method of measuring a temperature can include generating a time varying signal that varies with time in a known manner, such as having a repeating sawtooth waveform. Further, the method can include generating a first intersecting signal that intersects with the time varying signal at a first time, and generating a second intersecting signal that varies with temperature and intersects with the time varying signal at a second time. Subsequently, the method can construct a pulse signal having a first edge corresponding to the first time and a second edge corresponding to the second time, with the pulse signal having a width corresponding to the temperature.

Abstract: A method and system of adaptive power control. Characteristics of a specific integrated circuit are used to adaptively control power of the integrated circuit.

Abstract: A compensation device that can include a bias-able device, a bias circuit that provides the bias-able device with a bias current, a signal conditioner selectively coupled to the bias-able device, and an emulator. The signal conditioner and emulator can divert current from the bias-able device in an operational and calibration mode, respectively. In calibration mode, the emulator generates a compensation current that is combined with a sense current so that the sense current equals the bias current.

Abstract: An integrated circuit for switching a transistor is disclosed. In some embodiments, an operational amplifier is configured to drive a transistor, and slew rate control circuitry is configured to control the slew rate of the transistor source voltage during turn on. The transistor source voltage is employed as feedback to the operational amplifier to facilitate closed loop control of the transistor source voltage during switching of the transistor.

Abstract: The device (12) is used for supplying power to a rapid clocking and/or a rapidly clocked integrated circuit (13), which has a circuit load (17) to be supplied with power and an internal capacity (15) connected parallel to the circuit load (17). The integrated circuit (13) has a high clocking frequency (f1) which is in particular at least in the MHz range. A supply unit (14) which is in particular designed as a current source is directly connected to the internal capacity (15). The supply unit (14) has an internal resistance, the impedance value of which is so high at the clocking frequency (f1) that a current (ID2) which supplies the circuit load (17) originates to a greater degree from the internal capacity (15) than from the supply unit (14).

Abstract: High-accuracy overcurrent detection is performed, while a loss resulting from the current detection is significantly reduced. A switch section outputs the voltage between the both terminals of a current detection resistor using an AND signal between an output signal from a hysteresis comparator and an output signal from a pre-driver. The voltage is filtered by an electrostatic capacitor element and a resistor, and inputted to a comparator. The comparator makes a comparison between the signals inputted to the two input terminals thereof, and outputs the result of the comparison to a digital filter. When an overcurrent begins to flow in a power supply unit, the levels of the voltages inputted to the two input terminals of the comparator are inverted so that the comparator outputs an inversion signal to the digital filter. The digital filter outputs a detection signal to an overcurrent detection circuit when an arbitrary time has elapsed.

Abstract: Provided are an internal supply voltage generator capable of reducing latch-up and a semiconductor device having the same. The internal supply voltage generator generates at least one internal supply voltage, and includes a first booster circuit that generates a first voltage from a first reference voltage and an input voltage and outputs the first voltage via a first output terminal, a second booster circuit that generates a third voltage from a second voltage and the first voltage and outputs the third voltage via a second output terminal, and at least one switch that is disposed to correspond to at least one of the first output terminal and the second output terminal and adjusts at least one of the first voltage and the third voltage.

Abstract: An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.

Abstract: This invention includes a bias origination section configured to originate an original bias voltage; a comparison section configured to compare the original bias voltage and a comparison voltage, and output a comparison result; a resistive divider section composed by a resistance circuit including a variable resistor section having a resistor and a switch, and configured to generate the comparison voltage; a bias decision control section configured to determine bias decision data for controlling a resistance value of the variable resistor section so as to bring the comparison voltage close to the original bias voltage, based on a comparison result of the comparison section; and a storage section configured to hold the bias decision data and also output the comparison voltage as a bias voltage by controlling a resistance value of the variable resistor section based on the held bias decision data, thereby generating a low-noise bias with a small area.

Abstract: A temperature independent reference circuit includes first and second bipolar transistors with commonly coupled bases. First and second resistors are coupled in series between the emitter of the second bipolar transistor and ground. The first and second resistors have first and second resistance values, R1 and R2, and third and second temperature coefficients, TC3 and TC2, respectively. The resistance values being such that a temperature coefficient of a difference between the base-emitter voltages of the first and second bipolar transistors, TC1, is substantially equal to TC2×(R2/(R1+R2))+TC3×(R1/(R1+R2)), resulting in a reference current flowing through each of the first and second bipolar transistors that is substantially constant over temperature. A third resistor coupled between a node and the collector of the second bipolar transistor has a value such that a reference voltage generated at the node is substantially constant over temperature.

Abstract: An improved reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the improved Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (E.g. Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply. This improves the sensing of Vssq-referenced signals in such a system.

Abstract: An amplifier biasing circuit that reduces gain variation in short channel amplifiers, an amplifier biasing circuit that produces a constant Gm biasing signal for short channel amplifiers, and a multistage amplifier that advantageously incorporates embodiment of both types of amplifier biasing circuits are described. Both amplifier biasing circuit approaches use an operational amplifier to equalize internal bias circuit voltages. The constant Gm biasing circuit produces a Gm of 1/R, where R is the value of a trim resistor value. The biasing circuit that reduces gain variation produces a Gm of approximately 1/R, where R is the value of a trim resistor value, however, the biasing circuit is configurable to adjust the bias circuit Gm to mitigate the impact of a wide range of circuit specific characteristics and a wide range of changes in the operational environment in which the circuit can used, such as changes in temperature.

Abstract: A method and system for limiting energy to a sensor and/or an environment in which the sensor is located. A high current sensor driver is powered through a resistance-capacitance (RC) circuit. In a failure mode, the RC circuit constrains output of a sensor driver to the sensor in order to limit average current applied to the sensor. In one embodiment, the capacitor is chosen so that it can provide adequate current to the sensor driver for a short period of time. The value of the resistor may be chosen to ensure that under short circuit conditions direct current (DC) is limited to a safe value. The combined values of the resistor and capacitor may be adjusted such that the capacitor can charge to a prescribed level during the interval between active pulses.

Abstract: A voltage trimming circuit of a semiconductor memory apparatus may include a first voltage generation block configured to select voltage levels of a first node and a second node and divide a voltage between the first node and the second node to generate a first division voltage group; a second voltage generation block configured to select voltage levels of a third node and a fourth node and divide a voltage between the third node and the fourth node to generate a second division voltage group; a first switch block configured to select one division voltage of the first division voltage group to output the selected division voltage as a first reference voltage; and a second switch block configured to select one division voltage of the second division voltage group to output the selected division voltage as a second reference voltage.

Abstract: Provided is a band gap reference voltage circuit having an improved power supply rejection ratio. Owing to a voltage supply circuit (51), a power supply voltage (V5) does not depend on variation of a power supply voltage (Vdd). A voltage (V3?V2) which is generated across a resistor (41) and has a positive temperature coefficient is determined based not on the power supply voltage (Vdd) but on the power supply voltage (V5), and hence the voltage (V3?V2) does not depend on the variation of the power supply voltage (Vdd). As a result, the power supply rejection ratio of the band gap reference voltage circuit is improved.

Abstract: An internal voltage generation apparatus for a semiconductor device is disclosed. The internal voltage generation apparatus includes a power-up detector for receiving an external supply voltage and generating a power-up signal, an internal voltage generator for generating a plurality of internal voltages, and an initial level holder including a plurality of transistors for supplying the external supply voltage to the internal voltage generator in response to the power-up signal, and a plurality of passive elements connected in parallel with the transistors, respectively.

Abstract: A memristor-protection integrated circuit. The memristor-protection integrated circuit includes a first current-bias circuit, a second current-bias circuit, an inverter, and a current limiter. The first and second current-bias circuits are configured to be coupled to first and second power-supply rails, respectively. The inverter is coupled to the first current-bias circuit and to the second current-bias circuit, and is configured to couple at least one memristor to at least one of the first current-bias circuit and the second current-bias circuit in response to an input signal applied to the inverter. The current limiter is coupled to the first current-bias circuit and coupled to the second current-bias circuit, and is configured to limit current flowing through the memristor.

Abstract: A main power supply supplies a power supply voltage to a power supply terminal of a DUT. A control pattern generator generates a control pattern including a pulse sequence. A compensation circuit intermittently injects a compensation current to the power supply terminal of the DUT via a path different from that of the main power supply. A switch is arranged between an output terminal of a voltage source and the power supply terminal of the DUT, and is turned on and off according to the control pattern.

Abstract: A level shift circuit and a semiconductor device are configured to prevent failure and malfunction even when an excessive negative voltage or ESD surge are applied to a high-voltage power supply terminal. The level shift circuit includes a level shift resistor, a current-limiting resistor connected in series to the level shift resistor, and an n-channel MOSFET, with its drain connected to the current-limiting resistor. An output of the level-up circuit is obtained from the positioned between the level shift resistor and the current-limiting resistor. By providing the current-limiting resistor, the current that flows due to an excessive negative voltage or ESD surge is suppressed to prevent the level shift circuit from failing or malfunctioning.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: A linear relationship is established between a gain control signal and an amplification factor (value in dB). Described is a current generation circuit including a first current output section which outputs a first current, a second current output section which outputs a second current proportional to the first current, and a variable-current control section which generates a third current proportional to the first current, divides the third current into a fourth current and a fifth current according to a first control signal, and outputs the fourth and the fifth currents. The current generation circuit outputs a sum of the first and the fourth currents as a reference current, and a sum of the second and the fifth currents as an output current.

Abstract: Embodiments of the invention describe a core circuit for a reference current generator circuit that biases a first transistor to source a first current and a second transistor parallel to the first transistor, biased to source a second current controlled by the first current. A third transistor is coupled parallel to the second transistor and sources a third current controlled by the first current. The third transistor has a different threshold voltage than a threshold voltage of the second transistor. A resistive component coupled to conduct the second current has a resistive voltage that is substantially equal to a voltage differential between the first transistor and the second transistor. The conducting current through the resistive component is substantially independent of temperature variations.

Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.

Abstract: The present invention provides a regulator circuit that can fast-respond to a variation in load current and supply a sufficient drive current so as to be capable of generating a stable internal source voltage. The regulator circuit includes a preamplifier circuit that detects and amplifies a different between a reference voltage and an internal source voltage, a clamp circuit that limits the amplitude of an output of the preamplifier circuit, a main amplifier circuit that amplifies the amplitude-limited output of the preamplifier circuit, and a driver circuit that outputs the internal source voltage according to the output of the main amplifier. Even though the internal source voltage varies abruptly, the regulator circuit does not oscillate owing to the effect of the clamp circuit.

Abstract: The voltage generation circuit having a standard voltage generation circuit, a reference voltage, a minimum voltage setting circuit, and a voltage setting circuit that gradually sets voltage by switching a plurality of the gate transistors to switch a combination of resistive elements. The voltage generation circuit includes a differential amplifier that has one input terminal connected to the reference voltage generated by the standard voltage generation circuit and another input terminal connected to the minimum voltage setting circuit. The differential amplifier has an output node showing the result of a difference voltage of the inputs. The voltage generation circuit includes a pump control circuit that outputs a control signal controlling a charge-pump motion, based on the differential voltage, and a charge pump circuit that sets up and outputs the voltage by the control signal.

Abstract: To solve the problem of the conventional reference voltage generation circuit in that an output voltage exceeds a predetermined voltage value, there is provided a reference voltage generation circuit including: a voltage generation circuit provided between a first power supply and a second power supply, to output an output voltage to an output terminal; an auxiliary start-up circuit provided between the output terminal and the first power supply, to supply a voltage of the first power supply to the output terminal; and a control circuit that switches the auxiliary start-up circuit between an operating state and a non-operating state according to a value of a voltage at the output terminal.

Abstract: An internal voltage control circuit includes active drivers, a control unit, and a time interval adjustment unit. The active drivers are configured to receive a common internal voltage. The control unit is configured to control respective enable operations of the active drivers. The time interval adjustment unit is configured to respectively supply enable signals, generated by the control unit, to the active drivers at respective predetermined time intervals.

Abstract: Embodiments of the invention describe a core circuit for a reference current generator circuit that biases a first transistor to source a first current and a second transistor parallel to the first transistor, biased to source a second current controlled by the first current. A third transistor is coupled parallel to the second transistor and sources a third current controlled by the first current. The third transistor has a different threshold voltage than a threshold voltage of the second transistor. A resistive component coupled to conduct the second current has a resistive voltage that is substantially equal to a voltage differential between the first transistor and the second transistor. The conducting current through the resistive component is substantially independent of temperature variations.

Abstract: According to an optical-receiving apparatus including an APD converting input light into an electric signal and a bias-voltage-control method used for the optical-receiving apparatus, a multiplication factor appropriate for the APD is predetermined and a multiplication factor used for the APD can be maintained at the level of the predetermined multiplication factor at all times according to a change in the ambient temperature of the APD so that the intensity of input light-transmitted to the APD can be monitored with accuracy. The optical-receiving apparatus further includes a bias circuit generating a bias voltage applied to the APD based on a control signal, a temperature-monitor circuit monitoring the ambient temperature, and an operating circuit that stores data on the predetermined multiplication factor and that controls the bias circuit so that the multiplication factor corresponding to the monitored temperature becomes the predetermined multiplication factor.

Abstract: A delay circuit includes a delay unit having a first and a second power supply terminals, a pair of differential signal input terminals and a pair of differential signal output terminals. The signals entered to the pair of differential signal input terminals are delayed and output at the pair of differential signal output terminals. The delay circuit also includes a current controller that exercises control to cause a current of a current source, controlled by a current control terminal, to flow through the first and second power supply terminals of the delay unit. The delay circuit also includes a voltage controller that exercises control to provide for a constant potential difference between the first and the second power supply terminals (FIG. 1).

Abstract: A transistor circuit is provided. The transistor circuit includes a first output transistor, a second output transistor, and a switch arrangement. The first and second output transistors are arranged for providing an output signal to a common output of the transistor circuit. The switch arrangement couples an output of the first output transistor and the output of the second output transistor to the common output in sequence. The first and second output transistors are controlled to provide the same steady state output. The switch arrangement is adapted such that when the output of the first output transistor is coupled to the common output, changes in drive conditions voltage of the first output transistor are isolated from the second output transistor.

Abstract: A bias voltage generation circuit includes a data holding section, a correction value storage section, a computing circuit, a voltage dividing circuit and a selection circuit. The data holding section holds a variable n-bit data value that is set from an exterior, wherein n is a positive integer. The correction value storage section stores an n-bit correction value for correcting the n-bit data value. The computing circuit computes the n-bit data value and the n-bit correction value, and outputs an n-bit computing result. The voltage dividing circuit divides a reference voltage into 2n voltages, and outputs 2n levels of divided voltages. The selection circuit selects one level of a divided voltage from the 2n levels of divided voltages on the basis of the n-bit computing result and outputs the selected divided voltage as a bias voltage, the output bias voltage having a variation over 2n levels.

Abstract: A temperature compensated current reference circuit has a differential amplifier and a first feedback transistor with a gate coupled to the differential amplifier output. The first feedback transistor couples a supply voltage line to an inverting input of the differential amplifier. There is also a second feedback transistor with a gate coupled to the differential amplifier output, which couples the supply voltage line to a non-inverting input of the differential amplifier. A first temperature dependent conductor couples the inverting input to ground. A primary reference resistor and a second temperature dependent conductor are connected in series and couple the non-inverting input to ground. An output current control transistor has a gate and one other electrode coupled together and a third electrode coupled to the supply voltage line. A secondary reference resistor and a conductivity change sensing transistor are connected in series and couple the gate of the output current control transistor to ground.

Abstract: Voltage regulation circuitry is provided comprising a pull-up p-type threshold device connecting a supply voltage node to an output voltage node, the pull-up p-type threshold device configured to be switched off in dependence on a control signal. A pull-down stack connects the output voltage node to a reference voltage node, the pull-down stack comprising a pull-down p-type threshold device and a pull-down n-type threshold device connected in series. An inverter is configured to receive an input from the output voltage node and is configured to generate a cut-off signal, wherein the pull-down n-type threshold device is configured to be switched on in dependence on the control signal and the pull-down p-type threshold device is configured to be switched off in dependence on the cut-off signal.

Abstract: Provided is an intermediate potential generation circuit with a lower power supply potential. The intermediate potential generation circuit includes: a current mirror circuit including a first transistor and a second transistor each having a source input with a power supply potential; a current source circuit including a third transistor having a drain connected to a drain of the first transistor; a grounded source amplifier circuit including a fourth transistor having a gate input with the intermediate potential, and a drain connected to a drain of the second transistor; a parallel connection circuit including a fifth transistor connected in parallel with the first transistor, and a sixth transistor connected in parallel with the second transistor; and a source follower circuit including a seventh transistor and an eighth transistor having gates that are connected in common to each other, and connected with the drains of the second transistor and the sixth transistor.

Abstract: A reference voltage generating circuit includes a resistance dividing circuit formed with resistors connected in series.

Abstract: A semiconductor apparatus includes a constant voltage circuit that converts an input voltage and outputs a prescribed constant voltage. The constant voltage circuit includes an output transistor that receives an input of a control signal and outputs a current (from an input terminal to an output terminal) in accordance with the control signal. Also included is an error amplifier circuit that controls the output transistor to create a voltage in proportion to an output voltage outputted from the output terminal becomes a prescribed reference level. A direct current power source supplies direct current power to the constant voltage circuit. A voltage creating circuit creates and outputs a voltage higher than that of the direct current power.

Abstract: The present invention relates to an improved PTAT current source and a respective method for generating a PTAT current. Opportune collector currents are generated and forced in two transistors exploiting the logarithmic relation between the base-emitter voltage and the collector current of a transistor. A resistor senses a voltage difference between the base-emitter voltages of the two transistors, which can have either the same or different areas. A fraction of the current flowing through the resistor is forced into a transistor collector and mirrored by an output transistor for providing an output current. By this principle an all npn-transistor PTAT current source can be provided that does not need pup transistors as in conventional PTAT current sources. The invention is generally applicable to a variety of different types of integrated circuits needing a PTAT current reference, especially in modern advanced technologies as InP and GaAs where p-type devices are not available.

Abstract: A temperature independent reference circuit includes first and second bipolar transistors with commonly coupled bases. First and second resistors are coupled in series between the emitter of the second bipolar transistor and ground. The first and second resistors have first and second resistance values, R1 and R2, and third and second temperature coefficients, TC3 and TC2, respectively. The resistance values being such that a temperature coefficient of a difference between the base-emitter voltages of the first and second bipolar transistors, TC1, is substantially equal to TC2×(R2/(R1+R2))+TC3×(R1/(R1+R2)), resulting in a reference current flowing through each of the first and second bipolar transistors that is substantially constant over temperature. A third resistor coupled between a node and the collector of the second bipolar transistor has a value such that a reference voltage generated at the node is substantially constant over temperature.

Abstract: Implementations related to compensating for on-current leakage associated with current source arrangements are disclosed. An implementation may be provided that includes a replicated current mirror output stage. A circuit may be disposed between a current mirror output stage and the replicated current mirror output stage. The circuit may be implemented to drive a voltage associated with the current mirror output stage to a voltage level associated with the replicated current mirror output stage. A current may be supplied by the circuit to drive the voltage associated with the current mirror output stage. In one implementation, the current is substantially equal to an on-current leakage associated with the current mirror output stage.

Abstract: A design structure integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC system architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-chip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributors; the noise event arbiter determining when each noise contributor may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributor as to when permission is granted to execute its operations.

Abstract: A current driving circuit includes: a reference input terminal to which a first reference current is given; a current mirror circuit for receiving the first reference current and outputting a first internal current corresponding to the first reference current; a bias voltage generation section for receiving the first internal current and generating a bias voltage corresponding to the first internal current; an output reference current generation section for receiving the bias voltage and generating a second reference current corresponding to the bias voltage; a reference current output terminal for outputting the second reference current; an internal current generation transistor for receiving at a gate thereof the bias voltage and generating a second internal current corresponding to the bias voltage; and an output current generation section for receiving the second internal current and generating n output currents corresponding to the second internal current.

Abstract: A system includes a first circuit, a first charge pump, a second circuit, and a second charge pump. The first circuit has a first power supply terminal coupled to a positive power supply terminal and a second power supply terminal. The first charge pump has an input coupled to positive power supply terminal and an output coupled to the second power supply terminal of the first circuit. The second circuit has a first power supply terminal coupled the second power supply terminal of the first circuit and a second power supply terminal. The second charge pump has an input coupled to the first power supply terminal of the second circuit and an output coupled to the second power supply terminal of the second circuit.

Abstract: In an RF tag, a mask ROM or a flash memory is used for storing data such as an ID number. Although the mask ROM can be realized at a low price, rewriting is not possible. In addition, in the flash memory, although electric rewriting is possible, production cost increases. Accordingly, it is difficult to provide an RF tag by which data rewriting is possible at a low price. An RF tag is provided with a power supply circuit having a function to generate a power supply voltage from a weak radio signal and a memory which can hold data stored in a data holding portion by the power supply voltage. With the above structure, a high-performance RF tag capable of rewriting data such as an ID number after production can be provided at a low price.

Abstract: A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage).