Abstract: This document discusses, among other things, apparatus and methods for pre-biasing an edge rate controlled output stage of a switch circuit. In an example, a switch circuit can include an output transistor and a pre-bias circuit coupled to the output transistor. The pre-bias circuit can include a pre-bias transistor configured to selectively couple a control node of the output device to a first voltage, and wherein the pre-bias transistor can include a lower threshold voltage than the output transistor.

Abstract: A semiconductor integrated circuit includes a first ground voltage pad, a second ground voltage pad, an internal voltage generation unit, and a division unit. The first ground voltage pad is configured to receive a first ground voltage. The second ground voltage pad is configured to receive a second ground voltage. The internal voltage generation unit includes a comparison unit configured to compare a reference voltage with a feedback voltage by using the first ground voltage, and a driving unit configured to drive an internal voltage terminal in response to an output signal of the comparison unit. The division unit is coupled between the internal voltage terminal and the second ground voltage pad, and configured to divide a voltage of the internal voltage pad and generate the feedback voltage supplied to the internal voltage generation unit.

Abstract: A low power reference device is disclosed. The low power reference device includes a precision reference module, a low power reference module, a calibration module, an output module and one or more sequencers. The precision reference module is configured to output a first reference signal while the low power reference module is configured to output a second reference signal. The calibration module is configured to receive the first and second reference signals and output a correction signal to the low power reference module. The output module is configured to receive the first and second reference signals and output a final reference signal. The one or more sequencers are configured to drive each of the precision reference modules, low power reference module, calibration module and output module according to a predetermined timing sequence.

Abstract: A circuit comprises a plurality of segments and a clamp circuit. Each of the plurality of segments comprises a bond pad coupled to a multi-bonded pin via a respective bond wire and a conductor coupling the bond pad to a respective internal connection. The bond pad from each of the plurality of segments is coupled to the same multi-bonded pin. The clamp circuit comprises a plurality of input pins and a plurality of clamp transistors. Each input pin is coupled to the bond pad of a respective one of the plurality of segments via the respective conductor. Each clamp transistor is coupled to a respective one of the input pins, wherein each of the plurality of clamp transistors is configured to prevent a voltage on the respective conductor from exceeding a respective voltage limit.

Abstract: Various embodiments of the present invention provide systems and methods for governing power dissipation in a semiconductor device. For example, various embodiments of the present invention provide semiconductor devices that include a first function circuit, a second function circuit, and a power state change control circuit. The power state change control circuit is operable to determine a combination of power states of the first function circuit and the second function circuit that provides an overall power dissipation within a power dissipation level.

Abstract: Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current.

Abstract: Techniques are described to mirror currents and subtract currents accurately. In an implementation, a circuit includes a first current source coupled to a first node to provide a current IPD1 and a current mirror coupled to the first node through a first switch T1 to provide a current IREF1. In a closed configuration, the current IREF1 flows from the current mirror into the first node. A sigma delta modulator controls the switch T1 such that over a period of time an average current flowing from the current mirror into the first node is equal to the current IPD1 flowing out of the first node. The sigma delta modulator generates a digital output to control switch T2 to allow a current IREF2 into a second node, thus subtracting a portion of a current IPD2 at the second node over a period of time.

Abstract: A DC motor is provided. The DC motor prevents rush or overload of current in the DC motor during and/or after power input irregularities to the DC motor. A control circuit of the DC motor is configured to control current provided to the DC motor. When power irregularities in the power input to the DC motor are detected by the control circuit, the control circuit stops generating PWM (Pulse Width Modulated) signals and stops the current provided to the DC motor. After the stoppage of PWM signals, the control circuit can perform a soft-start of the PWM signals when the power irregularities are no longer detected. The soft starting of the PWM signals generates gradual increase in current to the DC motor, thus, preventing sudden rush of current that cause malfunction of the DC motor.

Abstract: Systems and methods are disclosed that use multiple DC-DC (direct-current-to-direct-current) regulators and configurable DC-DC regulators with respect to multi-band audio receivers in order to allow for the use of different DC-DC regulator switching clock signals for different audio broadcast bands. The systems and methods disclosed thereby help to alleviate interference problems typically caused by switching devices used in the DC-DC conversion process. The embodiments described are also applicable to switching power supplies run from alternating current (AC) power sources and to Class D amplifiers working with broadcast radios.

Abstract: A level formatter is provided that has differentially coupled closed loop current sources, each configured to precisely establish a current proportional to a reference voltage. A bridge circuit is differentially coupled to two supplementary current sources and controlled to rapidly switch the current from the supplementary current sources to produce output voltages at respective outputs that are approximately equal to respective one of two reference voltages.

Abstract: A semiconductor integrated circuit includes a selector to selectively output and supply to a monitoring target voltage terminal one of a power supply voltage from an outside of the semiconductor integrated circuit and a predetermined reference voltage depending on an adjusting mode signal, a voltage monitoring circuit to monitor a voltage fluctuation at the monitoring target voltage terminal and converting the voltage fluctuation that is monitored into a control signal, and an input and output circuit to output the control signal to the outside.

Abstract: A power supply circuit includes a PWM controller, which is capable of providing pulse signals to the CPU, a temperature feedback circuit coupled to the PWM controller, and a temperature sensor. The temperature sensor is coupled to the temperature feedback circuit, the temperature sensor is located adjacent the CPU, and capable of detects a temperature of the CPU. The PWM controller is capable of adjusting the pulse signals to maintain the pulse signals stably when the temperature sensor detects the temperature of the CPU rising.

Abstract: Provided is an integrated circuit system and method for biasing the same that features bifurcating a power distribution network to provide a bias voltage to the integrated circuit system. One of the branches of the power distribution network attenuates an impedance in the power distribution network that supplies transient currents and the remaining branch supplies a substantially steady-state currents.

Abstract: The present invention relates to circuits and methods for limiting the operating area of a transistor in a constant current source. The circuits and methods use a detector and a driver to limit the operating area of a transistor. The detector and driver have parameters selected so that, when the voltage at the drain of the transistor satisfies a reference condition, the driver causes drain current of the transistor to decrease. The reference condition is determined relative to the maximum safe drain-to-source voltage at the design drain current of the constant current source.

Abstract: Systems and methods for realizing current drivers without current or voltage feedback for devices that require accurate current drive with zero standby current has been disclosed. In a preferred embodiment of the invention this current driver is applied for write circuits for MRAMs. A fast and accurate reference current is generated by diode voltage divided by resistor without any feedback. The diode current is not fed back from the reference current. The diode current is generated from a regulated voltage. Temperature compensation of the write current is inherently built in the diode current reference. Fine-tuning of the temperature coefficient is achieved by mixing poly and diffusion resistors. A switch inserted in the current driver can turn on the driver fast and without a need for standby current. Leading boost in the current driver can fast charge the large coupling capacitance of word and bit lines and speed up write timing.

Abstract: A device for providing a high precision current reference comprising a PTAT generator circuit for supplying a voltage, a high precision current reference offset generator circuit for generating a high precision current offset to compensate for variation in a resistance component due to variation in temperature, and a current adding circuit for aggregating the current from the PTAT generator circuit and the current from the high precision current reference offset generator circuit. In one embodiment, a high precision current reference generated is substantially independent of temperature. On-chip resistors may be used to design a high precision current reference. Accordingly, high precision current reference generated maintains high precision with zero temperature co-efficient using on-chip resistors that are substantially cheaper than off-chip resistors.

Abstract: Conventional bias circuits exhibit a number of limitations, including the time required to power-up a bias circuit following a low-power state. Large current surges in the supply network induce ringing, further complicating a power-up process. Example embodiments reduce power-up time and minimize current surges in the supply by selectively charging and discharging capacitance to the circuit during power-up and power-down of the bias circuit.

Abstract: A device that includes at least one current consuming component. The device is characterized by including a compensation circuit adapted to compare between a voltage level at a sensing point within an integrated circuit and between a reference voltage derived from a voltage peak level at the sensing point; and to selectively increase the voltage at the sensing point in response to the comparison. A method for compensating for voltage drops in an integrated circuit, the method includes providing at least a first supply voltage to an integrated circuit; the method is characterized by including: comparing between a voltage level at a sensing point within an integrated circuit to a reference voltage derived from a voltage peak level at the sensing point; and selectively increasing the voltage at the sensing point in response to the comparison.

Abstract: An apparatus is provided that includes a drift trimming stage that includes a first current source providing a current with a first temperature dependency and a second current source providing a current with a second temperature dependency. The first and the second current source are coupled at a first node and configured to have equal currents at a first temperature. There is further a third current source providing a current with a third temperature dependency and a fourth current source providing a current with a fourth temperature dependency. The third current source and the fourth current source are coupled at a second node and configured to have equal currents at the first temperature. There is a first resistor coupled between the first node and a third node, a second resistor coupled between the second node and the third node. The first node and the second node are coupled to provide a combined voltage drop across the first resistor and the second resistor for reducing the offset drift.

Abstract: A temperature compensation circuit includes a bias circuit configured to output a bias current having a current value increasing in proportion to an absolute temperature in a low-temperature region in which a temperature is lower than a predetermined temperature, and having a greater current value than the current value proportional to the absolute temperature in a high-temperature region in which the temperature is equal to or greater than the predetermined temperature, and a transistor having a control terminal supplied with the bias current.

Abstract: A circuit for providing a reference voltage can be widely used in audio applications. However, at startup an abrupt start in the reference signal can cause undesirable audible artifacts. A circuit employing feedback of a reference voltage to control the charging of a capacitor which provides the reference voltage can be used to provide a smooth startup to the reference voltage. The circuit contains a differential pair for steering a fixed current source from one path to another as the reference voltage increases. The steered current can then be mirrored into one or more current mirrors where the newly mirrored current can be squeezed to zero when the difference between a desired reference voltage and the reference voltage approaches zero. This newly mirrored current can be used to charge a capacitor which is used to provide the reference voltage.

Abstract: A semiconductor integrated circuit can include a reference voltage pad that can be configured to receive an external reference voltage and supply the external reference voltage to the inside of the semiconductor integrated circuit, an internal reference voltage generator that can be configured to generate an internal reference voltage by voltage dividing, a selector that can be configured to select and output one of the external reference voltage and the internal reference voltage in response to a selection signal, and a voltage trimming block that can be configured to regulate the level of the output voltage from the selector in response to trimming signals and outputs the level-regulated voltage as a reference voltage.

Abstract: An integrated circuit (IC) includes a functional circuit and a capacitor cell. The functional circuit may operate with one of two power supply voltages. The capacitor cell is used to provide power supply decoupling for the functional circuit, and includes multiple capacitors, each designed to withstand a maximum voltage equal to the lower of the two power supply voltages. When the functional circuit is to operate with the higher of the two power supply voltages, the capacitors in the capacitor cell are coupled in a series arrangement between power supply and ground terminals of the IC. When the functional circuit is to operate with the lower of the two power supply voltages, the capacitors in the capacitor cell are coupled in a parallel arrangement between the power supply and ground terminals. In an embodiment, the functional circuit is an input-output (I/O) circuit powered by 1.8V or 3.3V power supplies.

Abstract: An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator, and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.

Abstract: A field effect transistor device comprising: a source electrode; a drain electrode; a semiconductive region comprising an organic semiconductor material and defining a channel of the device between the source electrode and the drain electrode; a first gate structure comprising a first gate electrode and a first dielectric region located between the first gate electrode and the semiconductive region; and a second gate structure comprising a second gate electrode and a second dielectric region located between the second gate electrode and the semiconductive region; whereby the conductance of the semiconductor region in the channel can be influenced by potentials applied separately or to both the first gate electrode and the second gate electrode.

Abstract: A mix mode wide range divider is provided for dividing a first signal by a second signal to generate an output signal. A third signal is generated depending on the resistance of a first adjustable resistor, and a fourth signal is generated according to the third signal and a target value determined by the second signal, to adjust the resistance of the first adjustable resistor and the resistance of a second adjustable resistor. The resistance of the first adjustable resistor is so adjusted to make the third signal equal to the target value, and the resistance of the second adjustable resistor is so adjusted to maintain a ratio of the resistance of the second adjustable resistor to the resistance of the first adjustable resistor. The output signal is generated depending on the first signal and the resistance of the second adjustable resistor.

Abstract: A temperature independent reference circuit includes first and second bipolar transistors with commonly coupled bases. First and second resistors are coupled in series between the emitter of the second bipolar transistor and ground. The first and second resistors have first and second resistance values, R1 and R2, and third and second temperature coefficients, TC3 and TC2, respectively. The resistance values being such that a temperature coefficient of a difference between the base-emitter voltages of the first and second bipolar transistors, TC1, is substantially equal to TC2×(R2/(R1+R2))+TC3×(R1/(R1+R2)), resulting in a reference current flowing through each of the first and second bipolar transistors that is substantially constant over temperature. A third resistor coupled between a node and the collector of the second bipolar transistor has a value such that a reference voltage generated at the node is substantially constant over temperature.

Abstract: A voltage generator for a peripheral circuit, the voltage generator includes: a voltage supplier supplying a peripheral circuit voltage having a voltage level maintained at a reference voltage level, the peripheral circuit voltage outputted in response to a driving signal; and a voltage level compensator increasing the voltage level of the peripheral circuit voltage in response to a column path command.

Abstract: An integrated circuit and method are provided, the integrated circuit comprising retention voltage generation circuitry which receives a supply voltage from a supply voltage node and provides a retention voltage at a retention voltage node. Functional circuitry is connected between the retention voltage node and a reference voltage node, the functional circuitry being held in a data retention state when at least a minimum voltage is provided between the retention voltage node and the reference voltage node.

Abstract: A power-up circuit comprises an external supply voltage potential detector, a first internal supply voltage potential detector, a second internal supply voltage potential detector, and a logic circuit. The external supply voltage potential detector is configured to detect a supply voltage that is external to the memory device and to generate a first detection signal indicating whether a voltage potential of the external supply voltage reaches a first predetermined value. The first internal supply voltage potential detector is configured to detect a first internal supply voltage that is internal to the memory device and to generate a second detection signal indicating whether a voltage potential of the first internal supply voltage reaches a second predetermined value.

Abstract: A MEMS sensor comprises a substrate and at least one proof mass having a first plurality of combs, wherein the proof mass is coupled to the substrate via one or more suspension beams such that the proof mass and the first plurality of combs are movable. The MEMS sensor also comprises at least one fixed anchor having a second plurality of combs. The first plurality of combs is interleaved with the second plurality of combs. Each of the combs in the first plurality of combs and the second plurality of combs comprises a plurality of conductive layers electrically isolated from each other by one or more non-conductive layers. Each conductive layer is individually coupled to a respective electric potential such that fringing electric fields are screened to reduce motion of the first plurality of combs along a sense axis due to the fringing electric fields.

Abstract: An internal voltage supplying device. A reference voltage generator generates a first feedback voltage having a predetermined voltage ratio with respect to a core voltage. An adjusting mechanism adjusts the voltage ratio, and a voltage generator supplies a high voltage having a level higher than a level of the core voltage by the level of a threshold voltage or higher and maintains the level of the high voltage in accordance with the first feedback voltage.

Abstract: A signal processor comprises a reference voltage circuit (RVC) for imposing a reference voltage (VR) onto a capacitance (Cr). The reference voltage circuit (RVC) comprises a negative slope module (NSM) for providing a negative slope signal (SN), which has a magnitude that decreases when a voltage that is present on the capacitance (Cr) increases. A positive slope module (PSM) provides a positive slope signal (SP), which has a magnitude that increases when the voltage that is present on the capacitance (Cr) increases. A minimum selection module (MSM) controls a maximum current (IMX) that the reference voltage circuit (RVC) can apply to the capacitance (Cr) substantially in dependence on the negative slope signal (SN), if the magnitude of the negative slope signal (SN) is smaller than that of the positive slope signal (SP).

Abstract: A voltage regulator includes a programming interface via which programming instructions may be applied to a processor of the voltage regulator. The voltage regulator operates the processor according to the programming instructions to select one of multiple active internally-generated analog voltage levels to determine an output voltage level of the voltage regulator.

Abstract: An amplifier biasing circuit that reduces gain variation in short channel amplifiers, an amplifier biasing circuit that produces a constant Gm biasing signal for short channel amplifiers, and a multistage amplifier that advantageously incorporates embodiment of both types of amplifier biasing circuits are described. Both amplifier biasing circuit approaches use an operational amplifier to equalize internal bias circuit voltages. The constant Gm biasing circuit produces a Gm of 1/R, where R is the value of a trim resistor value. The biasing circuit that reduces gain variation produces a Gm of approximately 1/R, where R is the value of a trim resistor value, however, the biasing circuit is configurable to adjust the bias circuit Gm to mitigate the impact of a wide range of circuit specific characteristics and a wide range of changes in the operational environment in which the circuit can used, such as changes in temperature.

Abstract: A system for generating a tunable DC slope includes: a first stage, supplied with an external voltage, for receiving a process, voltage and temperature (PVT) insensitive reference voltage and generating a voltage independent current; a second stage, coupled to the first stage and supplied with the external voltage, for generating a voltage dependent current and summing the voltage dependent current and the voltage independent current to generate a sloped voltage; and a third stage, coupled to the second stage and supplied with the external voltage, for amplifying the sloped voltage, and tapping the resultant sloped voltage at a desired point for generating the output DC slope.

Abstract: The voltage generation circuit having a standard voltage generation circuit, a reference voltage, a minimum voltage setting circuit, and a voltage setting circuit that gradually sets voltage by switching a plurality of the gate transistors to switch a combination of resistive elements. The voltage generation circuit includes a differential amplifier that has one input terminal connected to the reference voltage generated by the standard voltage generation circuit and another input terminal connected to the minimum voltage setting circuit. The differential amplifier has an output node showing the result of a difference voltage of the inputs. The voltage generation circuit includes a pump control circuit that outputs a control signal controlling a charge-pump motion, based on the differential voltage, and a charge pump circuit that sets up and outputs the voltage by the control signal.

Abstract: An integrated circuit includes a first driving unit configured to drive an output terminal to a first power supply voltage in response to an active mode signal, a second driving unit configured to drive the output terminal to a second power supply voltage in response to a standby mode signal, and a current control unit configured to control the current path between the first driving unit and the first power supply voltage terminal in response to a mode control signal denoting the active mode signal and the standby mode signal.

Abstract: A display system is disclosed in the present invention, which includes a low drop-out voltage regulator (LDO) for receiving an input voltage and providing a stable output voltage. The low drop-out voltage regulator includes a regulating circuit, a first switch, a current source circuit and an inverting circuit. The regulating circuit has a regulating circuit input, a regulating circuit output and a regulating circuit control terminal. The first switch selectively forms short or open circuit in accordance with ON/OFF states thereof. The current source circuit provides a fixed current to the control terminal and the output of the regulating circuit. The inverting circuit has an inverting circuit input coupled to the regulating circuit output and an inverting circuit output terminal coupled to the regulating circuit control terminal, the inverting circuit inverting the output voltage from the regulating circuit output.

Abstract: The present invention discloses an offset cancellation current mirror and method thereof. The offset cancellation current minor comprises a first current mirror, a second current minor, switches and resistors. The first current minor comprises two transistors and a capacitance, the capacitance is used to store an electrical potential difference when the switches are turned on in ways of connecting the first current mirror with the resistor. When the switches is turned off in ways of disconnecting the first current mirror with the resistor and connecting the first current mirror with the second current minor, the electrical potential difference stored in the capacitance is used to correct the difference of the two transistors due to manufacture process.

Abstract: The invention describes an electric circuit (100), a method and a computer program for hot-swapping an electronic board in a telecommunication system, where the increase in current in the electric circuit is controlled by a microcontroller (130) switching a power transistor in a switching circuit (150) so as to gradually increase the capacitor voltage for the electronic board. The current level is measured either in the microcontroller (130) itself or in an external current sense circuit (140) and compared to a maximum current level.

Abstract: A method and circuit for managing thermal performance of an integrated circuit. In accordance with an embodiment, a thermal limit circuit and a semiconductor device are manufactured from a semiconductor material, wherein the thermal limit circuit is configured to operate at a temperature level that is different from a threshold temperature in response to the thermal sensing element sensing a temperature at least equal to the threshold temperature.

Abstract: In current driving circuit a desired value of a driving current is promptly written in a load of each pixel despite load variations that may occur in each pixel. A constant current source circuit delivers a driving current Idata to a load. An output voltage difference amplifier circuit detects a voltage change produced at a load driving end within a preset time period, and delivers a current or a voltage corresponding to the voltage change during a time period different from the preset time period. The output voltage difference amplifier circuit temporally repeats detection of the voltage change and delivery of the current or the voltage to the load.

Abstract: Circuits, methods, and systems are disclosed in which a current is provided to compensate for spurious current while receiving signals through a line. For example, the spurious current can be sensed and the compensating current can be approximately equal to the sensed spurious current. The spurious current could include photocurrent from a bright light, and the compensating current can prevent bright light effects.

Abstract: A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.

Abstract: The semiconductor integrated circuit device includes load circuits and internal voltage generators for generating internal source voltages for driving the load circuits. Each of the internal voltage generators includes a reference voltage generating circuit for generating reference voltages, and regulator circuits for generating the internal source voltages with reference to the reference voltages. The regulator circuit is formed over an SOI substrate and includes a preamplifier circuit for detecting and amplifying a difference between each of the internal source voltages and each of the reference voltages, a main amplifier circuit for amplifying the output of the preamplifier circuit and generating a control signal, and a driver circuit for generating the internal source voltage in response to the control signal. An input stage of the main amplifier circuit is configured by MOS transistors coupling the gates and bodies of the MOS transistors.

Abstract: An integrated circuit die includes a microprocessor and a control circuit to control elements of a voltage regulator to supply power to the microprocessor.

Abstract: An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.

Abstract: A power control circuit includes an input/output controller hub (ICH), and first to third metal-oxide-semiconductor field effect transistors (MOSFETs). A drain of the first MOSFET is connected to a standby power source through a first resistor. A gate of the first MOSFET is connected to a sleep control terminal of the ICH through a second resistor. A drain of the second MOSFET is connected to the drain of the first MOSFET through a third resistor. A gate of the second MOSFET is connected to a general purpose input/output terminal of the ICH through a fourth resistor. A source of the third MOSFET is connected to the standby power source. A gate of the third MOSFET is connected to the drain of the second MOSFET. A drain of the third MOSFET is connected to a power terminal of an onboard network interface card.

Abstract: In one embodiment the present invention includes circuits and methods for calibrating switching current sources. A difference between a source current and a sink current is detected during a calibration phase. The difference is used to generate a digital signal to adjust a programmable current source to reduce the difference between currents. In one embodiment, a binary search is used to generate the digital signal during an initial calibration phase, and a linear approximation is used to generate the digital signal during an operational calibration phase.