Abstract: The present invention is an all digital timing and address generator which automatically adjusts its output pulse intervals to fit within the duration of periodic input pulses. The intervals are alway synchronous with the leading edges of the input pulses, and their number within the duration of a periodic input pulse is selectable in increments of one. The generator uses direct digital feedback to control its output timing for changes in input pulse width, and employs an integer time mark to prevent "unlocking" on non-integer width input pulses.

Abstract: The present invention comprises a communication system including a number of independently operating equipment modules in which the operations of these modules are referenced to a common external signal and thereby phase synchronized in order to reduce intra-system interference. The system includes a number of phase lock loop type processing circuits one of which is associated with each equipment module for tracking the external reference signal and generating a base reference for use by module with which each processing circuit is associated. The system takes advantage of the inherent capabilities of phase lock loop circuits to provide a base reference for each equipment module which is characterized by a frequency spectrum having a reduced level of spurious signals and noise. The preferred embodiment includes components for automatically switching between internally and externally generated reference signals and for automatically converting an external reference signal to a standard frequency.

Abstract: A phase locked loop circuit is arranged such that the frequency of an input reference clock signal is selected on the basis of a first or second transmission rate of an incoming digital signal, whereby an output digital signal correctly synchronized with the incoming digital signal having the first or second transmission rate can be transmitted. Also, the phase locked loop circuit is arranged so that a first or second central frequency value and a first or second boundary frequency value are set in response to the first or second transmission rate of the incoming digital signal so that, if a frequency value of an output digital signal lies outside of a range of the first or second boundary frequency values, the frequency of the output digital signal is set to the first or second central frequency values. Thus, the phase locked loop circuit of the invention can deliver the output digital signal correctly synchronized with the incoming digital signal having the first or second transmission rate.

Abstract: This invention provides an improved method for synchronizing a slave oscillator with a master oscillator. The slave includes two counters designated Reference and System, driven by its oscillator; the master includes a System Counter driven by its oscillator. The master sends a reset signal to the slave, simultaneously resetting its System Counter. Periodically, the master sends to the slave a synchronization signal, which signal is generated at predetermined intervals based upon the master's System Counter. Upon receipt of the reset signal, the slave resets its counters. Later, upon receipt of the synchronization pulse, the slave modifies the value of its System counter based upon the closest multiple of the expected count value for the synchronization signal interval. The Reference Counter is not synchronized and runs free.

Abstract: An automatic phase controlling circuit according to the present invention has a phase shifter and an auxiliary detector for producing a sensitizing signal in association with a signal loop constituted by a main detector for producing a control signal and a voltage-controlled oscillator for producing a variable-phase signal, and the sensitizing signal is delayed in phase from the control signal by about 90 degrees by virtue of the phase shifter, so that the main detector achieves a stability around a phase difference of 0 degree without sacrifice of quick response characteristics at a large difference in phase between the variable-phase signal and a reference signal.

Abstract: A reference time signal generation system 10 is provided which comprises a phase lock loop circuit 12 which generates a reference voltage V.sub.m. The phase lock loop circuit 12 comprises first and second divider circuits 14 and 18 coupled to the input of a phase comparator 16. The output of the phase comparator 16 is coupled to a loop filter 20 which generates a DC representation of the phase differential of the inputs of the phase comparator 16. The output of the loop filter 20 is input into a bias generator 26. The output of the bias generator 26 is coupled to the input of a voltage controlled oscillator 28 which has its output coupled to the input of second divider circuit 18. The reference voltage signal V.sub.m is taken from the output of the bias generator 26 and is transmitted to remote timing elements 32, 34 and 36 where it may be used to create reference timing signals which will accurately track the reference clock signal input into phase lock loop circuit 12.

Abstract: The present invention is directed to a self-calibrating clock synchronization system that receives a periodic, digital clock signal as a reference and generates therefrom a system clock signal that dynamically tracks and is synchronized to the reference clock. The invention utilizes state machine controlled selection circuitry that comprises a plurality of predetermined delays tapped to produce a number of phase-related clock signals, and multiplexing circuitry, for selecting one of the plurality of clock signals as the system clock. A comparator compares the selected clock signal and the reference clock to determine which leads or lags the other. In response to the comparison, selection, from the plurality of clock signals, of a system clock that most clearly matches the reference signal is made.

Abstract: Video signal time scaling apparatus includes a gated oscillator enabled and disabled in synchronism with a line scanning rate and capable of generating an oscillatory signal which is other than a multiple of a line scanning rate. The phase of an oscillator output signal is compared to the phase of a reference signal a predetermined time after the oscillator is enabled. Phase coincidence indicates a correct oscillation frequency. Otherwise, the oscillator frequency is incremented or decremented until phase coincidence is achieved. The oscillator signal acts a READ clock for permitting a video signal to be read out of a line memory at a rate different than that at which the video signal was written into memory, thereby producing a time scaled output video signal.

Abstract: A frequency synthesizer which uses a direct digital synthesizer (DDS) to generate a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. The DDS output signal is bandpass filtered and amplitude limited to reduce spurious noise. In one embodiment, the DDS frequency synthesizer is coupled to a phase lock loop which receives the DDS generated reference signal and a divide-by-N signal for generating an output signal at a frequency determined by the divide-by-N signal. The frequency resolution of the phase lock loop is N times the reference signal. In a second embodiment, the DDS is incorporated within the feedback path of the phase lock loop. An input reference frequency signal is provided to the phase lock loop with the DDS clock signal provided as a function of the phase lock loop output frequency. The DDS receives an input frequency control signal which determines the DDS step size.

Abstract: Metal detection apparatus comprises an oscillator circuit including an inductive detection coil and a detector for rectifying the output of the oscillator circuit synchronously with the frequency of oscillation. A comparison circuit compares the rectified output of the oscillator circuit with a reference signal and generates an output signal having a value related to the amplitude of the oscillator output. A feedback circuit generates a positive feedback signal and applies it to the oscillator circuit to maintain its oscillation at a predetermined amplitude under quiescent conditions. The circuit is largely immune to electromagnetic interference and temperature sensitive effects.

Abstract: A method for eliminating subharmonic false locking in a sampler and frequency multiplier phase-locked-loop source locking system comprising the modification of a prior known algorithm for determining the frequency of the first local oscillator used for controlling the sampling of the output of a source voltage controlled oscillator. The frequency of the first local oscillator is determined using prior algorithms for determining the lowest usable harmonic number H and the highest usable first oscillator frequency which will maximize sampler efficiency and minimize local oscillator phase noise due to frequency multiplication. Thereater, the harmonic number H as thus determined is modified depending upon whether when divided by a multiplication factor M, where M is the factor by which the frequency of the VCO is multiplied, the remainder thereof is equal to 1/M, 2/M or zero. If the remainder of the division step is zero, then H is increased by one.

Abstract: A frequency synthesizer for use in a high-frequency multichannel radio apparatus and so on. More particularly, a phase-locked loop (PLL) type frequency synthesizer which can perform a pulling process at high speed. Namely, a frequency synthesizer of the present invention can effect a pulling process at high speed by putting input signals to a phase comparator into a state in which the input signals are in phase with each other in an intermittent operation mode and can have strong resistance to noises by providing a 1-bit data latch and gate circuits in a data inputting portion thereof and synthesizing strobe signals at the time of inputting data thereto.

Abstract: The invention relates to the synchronization of a frequency-controllable oscillator in a PLL circuit with a carrier. The adjustment of this oscillator to the carrier frequency can be dispensed with in that additionally a frequency discriminator is provided which initially tunes the oscillator in accordance with the frequency difference. The frequency discriminator compares each oscillator frequency with a stable reference frequency which is proximate to the desired frequency and tunes the oscillator until it is in the range of the reference frequency. Subsequently the frequency discriminator is blocked and the further synchronization is taken over by the phase discriminator in the PLL circuit.

Abstract: A multi-frequency comb generator (2-4; FIG. 1) for radar and the like using a feedback loop through a frequency multiplier, such as for example, a doubler (3). A reference or master oscillator output goes through a directional coupler (2), for example, a ten dB coupler with twenty dB directivity, to the frequency doubler and then an amplifier (4). The amplifier output is superposed on the reference oscillator output (1) and is applied to the input of the doubler. Frequency doublers, when driven by multiple frequencies, cross modulate and generate sum and difference frequencies, which in going around the loop are fed back to the input, resulting in a comb of frequencies (5). As part of the frequency selecting section of a radar exciter (FIG. 2) the comb of frequencies and the output of a parallel frequency multiplier (8) are fed to a mixer (7), and the mixer's output, along with the coupled output ("N.times.

Abstract: A method and apparatus for synchronization of a clock generator, especially a clock generator of a digital telecommunications exchange. When there is a brief outage of the reference frequency, the voltage controlled oscillator of the phase control circuit whose output frequency determines the frequency of the clock generator continues to operate with the control voltage prevailing until then. Upon resumption of the reference frequency, the phase difference between the reference frequency and the output frequency of the oscillator is measured and corrected with the value of the valid phase difference before the loss of the reference frequency. The corrected value is used as the basis for resumed frequency control.

Abstract: A frequency synthesizer which uses a direct digital synthesizer (DDS) to drive a phase lock loop. The DDS generates a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. A phase lock loop receives the DDS generated reference signal and a divide-by-N signal for generating an output signal at a frequency determined by the divide-by-N signal. The frequency resolution of the phase lock loop is N times the reference signal.In a second embodiment, the DDS is incorporated within the feedback path of the phase lock loop. An input reference frequency signal is provided to the phase lock loop with the DDS clock signal provided as a function of the phase lock loop output frequency. The DDS receives an input frequency control signal which determines the DDS step size.

Abstract: A microprocessor or other integrated circuit including a clock generator circuit which is dependent on an externally-provided reference signal includes the capability of detecting the loss of this externally-provided reference signal and producing an alternate clock signal despite the loss of the reference. In a particular embodiment, the clock generator comprises a phase locked loop frequency synthesizer which normally relies on an external crystal oscillator for its reference frequency signal. The generator includes a circuit for detecting abnormalities in the crystal signal and switching the voltage controlled oscillator of the frequency synthesizer to an internally-generated reference voltage. In the particular embodiment, the clock generator is also capable of producing a reset signal in response to the loss of the reference signal.

Abstract: A programmable low noise frequency modulated signal source including a voltage controlled oscillator (VCO) having a frequency locked loop (FLL) constituting a first feedback path and a phase lock loop (PLL) constituting a second feedback path is provided. The PLL includes a VCO, a programmable fractional-N frequency division network for changing the rational number by which the VCO output signal is frequency divided, a phase detector for comparing the phase of the VCO output signal with the phase of a reference signal and for producing an error signal for controllably adjusting the output frequency of the VCO. The FLL includes a delay line frequency discriminator, a loop amplifier and filter to provide a first feedback signal to the VCO to thereby reduce the phase noise on the VCO output signal.

Abstract: The phase of an actual pulse signal (2') with respect to a phase reference pulse signal (1') can be accurately determined and a control output signal in form of a digital number be obtained rapidly depending on the relative temporal position of the phase pulse signals by counting at a high rate with respect to the pulse repetition rate of the phase reference pulse signal and providing count numbers as well as count rates in dependence of the time of occurrence of the actual pulse signal in relation to the reference pulse within a window period; if the actual pulse falls within the window period, the counting rate for the counter is increased, for example by decreasing the division ration of a divider (6), and the starting time for counting after the reference pulse is likewise extended, for example by addressing a starting time counter (4) from a PROM (5) the address of which is changed in dependence on the relationship of the actual pulse and the reference pulse.

Abstract: In a variable bit rate clock recovery circuit, a phase difference between an input demodulated signal and a recovered clock signal is detected, the detected phase difference signal is filtered by a loop filter and is then integrated, the integrated signal is supplied as an address to first and second ROMs, which store data of cosine and sine waves in advance, output data from the first and second ROMs are respectively D/A-converted by first and second D/A converters, an output signal from a variable frequency generator is modulated by using an output from the first D/A converter, a signal obtained by shifting the output signal from the variable frequency signal generator by .pi./2 radians is modulated by an output from the second D/A converter, and the respective modulated signals are synthesized, thereby obtaining a reference clock signal.

Abstract: A programmable low noise frequency modulated signal source including a voltage controlled oscillator (VCO) having a frequency locked loop (FLL) constituting a first feedback path and a phase lock loop (PLL) constituting a second feedback path is provided. The PLL includes a VCO, a programmable fractional-N frequency division network and a phase detector for comparing the phase of the VCO output signal with the phase of a reference signal and for producing an error signal to controllably adjust the output frequency of the VCO. The FLL includes a delay line frequency discriminator, a loop amplifier and filter to provide a feedback signal to a frequency control terminal of the VCO. The frequency discriminator includes a first signal path having a frequency sensitive time delay network to provide a phase shift as a function of the VCO output signal frequency and a second signal path which includes a voltage controlled phase shifting network.

Abstract: A frequency locking device, with pre-positioning in which an oscillator is controlled by the output of a frequency discriminator. Shifts in the frequency discriminator are removed by performing calibrations on this discriminator through two signals with known frequencies Fo and F1 produced by a generator. The signal resulting from this calibration is used to prepare a reference voltage for a digital/analog converter which also receives a digital oscillator control signal and which then produces a voltage representing the control voltage of the oscillator.

Abstract: A microwave frequency synthesizer which simultaneously provides increased frequency coverage, reduced channel spacings and improved settling times with a single phase-locked-loop. A VCO and a parametric divider enables a wide frequency coverage to be used in a phase-locked-loop. The fast hopping capability is primarily derived from the wide loop bandwidth which, in turns, is permitted by using a high reference frequency. The small channel spacings are created by using a 90.degree. phase shifter installed in the feedback path of the phase-locked-loop. The 90.degree. phase shifter permits channel spacings as small as 1/4 the reference frequency value.

Abstract: Circuit imperfections in phase modulators will introduce offsets in the servo error signals in frequency locking circuits. Such offsets will also cause a frequency offset. The frequency offset is first reduced by reducing or removing amplitude modulation at the modulating frequency in the modulated carrier signal. In the preferred embodiment, this is accomplished by a coupled servo which includes a matrix loop filter. After the amplitude modulation at the modulating frequency has been removed, sideband imbalance can be corrected by amplitude modulating the modulating signal so that the offset caused by sideband imbalance is reduced or eliminated. This will be the case provided that the integral of at least the third power of the amplitude modulation vanishes.

Abstract: A first oscillator outputs a signal having a reference frequency. A first frequency divider divides the frequency of the output signal from the first oscillator. A second oscillator outputs a signal having a target frequency. A second frequency divider divides the frequency of the output signal from the second oscillator. A phase comparator compares phases of output signals from the first and second frequency dividers. An integrator integrates an output signal from the phase comparator and controls the second oscillator in accordance with the integration of the output signal from the phase comparator. A first gate is connected between the first oscillator and the first frequency divider. A second gate is connected between the second oscillator and the second frequency divider. A third gate is connected between the phase comparator and the integrator.

Abstract: In addition to a filter phase comparator, an integrator, a first filter and a voltage-controlled oscillator of relatively low stability and having a wide pull-in range, a circuit arrangement for generating a clock signal comprises a frequency generator of high stability having a narrow pull-in range, a second phase comparator and second and third filters. The first phase comparator is supplied with the reference frequency and the clock signal emitted by the voltage-controlled oscillator. The second phase comparator is supplied with the clock signal and a normal frequency generated by a normal frequency generator. In the event of the failure of the reference frequency or the overshooting of predetermined phase difference values, a regulating circuit formed by the second phase comparator, the second filter, the third filter and the voltage-controlled oscillator is closed.

Abstract: There is provided a digitally controlled first order hold circuit and waveform synthesizer for digitally controlling the representation of a function over an approximation interval. In accordance with the operation of the invention, the first order hold circuit and waveform generator receives a digital data input signal which contains initial condition data, up/down data, and slope data for the approximation interval. The initial condition data is loaded into an up/down counter which is incremented using counting data at a rate depending on the value of the slope data and in a direction depending on the value of the up-down data. In order to minimize delays arising from data acquistion, two frequency synthesizer circuits are provided such that one frequency synthesizer provides counting data while the other frequency synthesizer receives slope data. During alternating intervals, the other frequency synthesizer circuit provides counting data while the other circuit receives slope data.

Abstract: A digital signal synthesizer stores a representation of a desired analog signal in the form of digital samples. The digital samples are converted to an analog signal by a sample clock having a frequency greater than or equal to twice the bandwidth of the desired analog signal. The analog signal is band pass filtered to recover the desired analog signal.

Abstract: A wide deviation tracking filter is provided which has the input signal to be tracked applied to a low frequency phase-locked loop circuit which performs coarse filtering of the phase noise on the input signal. A digital phase shifter is connected in series in the low frequency phase-locked loop and produces a pair of quadrature clock signals which are at the frequency of the input signal and at half the frequency of the output of the voltage control oscillator of the low frequency phase-locked loop. The pair of quadrature signals are connected to an image reject circuit. The image reject circuit is connected in series in the loop of a high frequency phase-locked loop which operates at a much higher frequency than the low frequency phase-locked loop and performs the function of further filtering the phase noise on the input signal to provide an output signal having ultra-low phase noise.

Abstract: A communication transceiver is described which can permit operation of the transceiver unit in either the trunked dispatch mode or in the cellular mode. The ability to utilize two sets of frequencies with different transmitter channel separation can be accomplished by providing a phase lock loop configuration with a signal having a frequency that is the separation between the transmit channels of the selected communication system or is a fraction thereof. Similarly, a controllable reference oscillator frequency is forced through the phase locked loop configuration, to provide a signal for which a the frequency multiple of the difference frequency for the selected communication mode and is the frequency of the channel. A scaling network provides a signal for the phase lock loop that, for the correct frequency of a controllable oscillator, is the difference between the transmitter or receiver channels.

Abstract: A microwave band frequency synthesizer comprises first and second phase-locking loops. The first phase-locking loop includes a first voltage controlled oscillator, a variable frequency divider and a first multiplier and generates an output signal whose frequency changes at the rate of a unit frequency change width of the oscillator.

Abstract: A clock apparatus provides variable frequency system clock signals for synchronizing the operation of data processing apparatus and constant frequency timing signals, in phase with the system clock signals, for controlling the operation of an interval timer or related apparatus. The variable frequency system clock signals are produced by placing a controllable divider network in the phase locked loop. The input signals to the controllable divider network are distributed as the system clock signals. The constant frequency is obtained by distributing count signals from the controllable divider network of the phase locked loop circuit to a plurality of comparator circuits and output signals from the comparator provide a multiplicity of timing intervals that result in the constant frequency signals. The timing intervals are determined by the control signals that are applied to controllable divider network and to a plurality of divider circuits associated with the comparator circuits.

Abstract: A microwave frequency synthesizer comprised of a phase-locked loop having a low noise and highly stabilized reference voltage-controlled oscillator and further two phase-locked loops each having a stabilized voltage controlled oscillator, the signal outputs from which are frequency-converted with as small multiplication factors as possible. This frequency synthesizer can minimize the phase noise that may be generated by frequency dividers in a digital system.

Abstract: An automatic frequency control circuit having the ability to resolve the frequency of an incoming signal to an extreme level of accuracy and to tolerate amplitude and pulse modulation on the incoming signal is disclosed. Two negative feedback loops are utilized. A coarse adjustment feedback loop resolves the frequency of the incoming signal to within the authority of a fine adjustment feedback loop. A computer is a common element of both loops and makes decisions regarding whether to resolve incoming a signal frequency using the coarse or the fine adjustment loops. Phase differences between a signal derived from the incoming signal and a reference signal are sampled at controllable time intervals apart to determine frequency adjustments within the fine adjustment loop.

Abstract: A voltage/frequency converter is formed of a V/F converter circuit which converts an input potential into a frequency corresponding to the instantaneous value of the input potential, and a difference detection circuit which generates an output corresponding to the difference between the output frequency of the V/F converter circuit and a predetermined reference frequency. The V/F converter circuit is controlled according to the level of the output from the difference detection circuit, thereby reducing the deviation of the output frequency of said V/F converter circuit from the reference frequency.

Abstract: A frequency synthesizer comprises a voltage controlled generator (11) for generating an output signal of a desired frequency in response to a control signal and a reference signal generator (13) for generating a reference frequency signal. The output signal is sampled (21) by the reference frequency to produce a sampled signal. The reference frequency signal is frequency divided (22) by a division factor determined by the desired frequency and the reference frequency. The sampled signal and the divided signal are compared (15) in phase and frequency and the control signal is produced depending on the phase difference between the two signals. For the division factor, two different values are determined by the desired frequency and the reference signal and one of the two values is selected according to a selection pattern determined by the reference frequency and the desired frequency.

Abstract: A method and apparatus for phase locking the signal of a controlled oscillator (1) to that of a reference oscillator (3), a correction quantity depending on the difference between the relative phase angles of the signals being generated at correction instants for correcting the frequency of the controlled oscillator. According to the invention, the phase lock may also be achieved with a controlled oscillator (1), having a frequency which is not a whole number multiple of the reference oscillator (3) frequency by, in one embodiment, the reference oscillator signal or in another embodiment, the controlled oscillator signal being phase shifted such that the phase difference occurring at the correction instants as a result of the controlled oscillator frequency not being a non-integer multiple of the reference oscillator frequency is eliminated at the formation of the correction quantity.

Abstract: A phase-lock loop circuit of a television apparatus is synchronized by a horizontal synchronizing input signal. The phase-lock loop circuit includes a frequency-to-voltage converter that is responsive, during vertical trace, to the synchronizing input signal for generating a control voltage indicative of the frequency of the synchronizing input signal. During vertical trace, the control voltage varies the free running frequency of a controlled oscillator of the phase-lock loop circuit such that the free running frequency of the oscillator is directly related to the frequency of the input signal. During vertical retrace, the frequency-to-voltage converter is responsive to the oscillator output signal for generating the control signal that maintains the free running frequency of the oscillator substantially unchanged during vertical retrace.

Abstract: A wireless data communications network utilizes a frequency synthesizer to achieve a systematic frequency hopping arrangement wherein frequency is incremented by two times the channel spacing from lowest frequency to highest frequency. When adjusting the frequency from highest frequency to lowest frequency a one times the channel spacing frequency hop is utilized for the first and half and last hop and two times the frequency spacing is utilized otherwise. In this manner, alternating frequencies are selected so that the same frequency is only utilized once during any complete cycle and the size of frequency transitions is held to a minimum allowing a narrow bandwidth filter and inexpensive implementation of the phase locked loop portion of the synthesizer.

Abstract: A frequency stable RF oscillator 10 comprises a variable frequency RF source in the form of a microwave cavity 24 having a Gunn diode 26 and a varactor 28 mounted therein, and produces an RF output frequency f.sub.o. The output of a frequency stable reference oscillator 14 having a frequency f.sub.r is impressed upon the RF source. Through self-mixing action of the Gunn diode, an IF whose frequency is f.sub.IF =.vertline.nf.sub.r -f.sub.o .vertline. is generated, n being a high harmonic number. The IF is detected by an IF amplifier 18 which forms part of a frequency lock loop controlling the frequency of the RF source.

Abstract: Variations, due to aging, of resonant frequency characteristics of electromechanical resonators are compensated by an oscillator including the resonantor. An indication of the amount of time that the oscillator is operating addresses a table of values indicative of the manner in which the oscillator changes frequency as the resonator ages. From the table of values a signal having a value indicative of a correction factor for the resonator aging is derived. The frequency of the oscillator is controlled in response to the value of the correction factor. The table of values is stored in a re-programmable memory. The values stored in the memory are corrected by comparing the oscillator frequency with a standard frequency.

Abstract: A frequency synthesizer produces a variable frequency output using a controllable oscillator and a variable frequency divider which form part of a phase locked loop. The integer division ratio of the divider can be altered during a division cycle to simulate a fractional divisor value. The phase noise or jitter which is caused by the step change in divisor value is removed by altering the divisor value in accordance with the terms of a plurality of sequences, each of which sums to zero and which represents successive rows in a Pascal's triangle. A cascaded sequence of accumulators is used to determine the starting instants of each sequence, and the length of each sequence is dependent on the number of delay lines used. Although only four accumulators are illustrated, more can be added to give any desired degree of phase noise cancellation.

Abstract: A frequency synthesizer of the pulse cancellation type which predicts the phase jitter that will be caused by the pulse cancellation and generates a compensation signal C which precisely compensates for the phase jitter. The compensation signal is derived directly, from a pulse train in the synthesizer which itself contains jitter, via a d.c. removal circuit DCR and an analogue integrator INT.

Abstract: A frequency synthesizer includes frequency reduction means which includes a pulse swallow circuit PS which cancels cycles from the frequency Fo under the control of a rate multiplier RM. To prevent phase jitter at the output of phase comparator PC due to the cancelled cycles, a compensation signal HP is derived from a swallow command signal A and from a multiplying fraction n/x of the rate multiplier. In order to keep the DC level of the signal HP constant, the signal HP is bidirectional with respect to a mid-point voltage level and the total area of the pulses in one direction is the same as the total area of the pulses in the other direction. The invention is applicable to both phase locked loop synthesizers (FIG. 2) and direct synthesizers (FIG. 11).

Abstract: A clock pulse generator system for providing a highly stable clock signal consists of two separate redundant clock signal generators which are controlled to operate in dead synchronization with each other. A microprocessor controlled digital phase lock loop operates to control each of the two clock signal generators and selects among a plurality of operating states such that the average dynamic phase difference in the two clock pulse signals generated is practically zero. Furthermore, the instantaneous dynamic phase difference does not exceed the phase noise of the voltage controlled crystal oscillators of the phase lock loops and, in one embodiment, is normally less than ten pico seconds, each phase lock loop comprising means for performing a fine, as well as coarse, phase comparison among internally or externally generated reference signals, only one of which is the highly stable clock signal output.

Abstract: An apparatus and method is disclosed for operating a modulus control loop of an LSI a phase locked loop integrated circuit (or descrete equivalent) and a dual modulus prescaler at higher frequencies. This is accomplished through the use of a flip flop whose input is the modulus control output from the synthesizer IC and whose clock input is provided by the output of the prescaler. This greatly extends the time available to shift the prescaler modulus control insuring that the control signals will not be missed and increasing the available frequencies that the modulus control loop may operate at.

Abstract: A line synchronizing circuit for a picture display device comprising a control loop for controlling a line oscillator. An incoming line synchronizing signal and also a reference signal generated by the oscillator are applied to a phase discriminator circuit. The output signal of the phase discriminator circuit is smoothed to obtain the control voltage for the oscillator. Pull-in of the control loop is established by means of a coincidence detector. Prior to that, an edge of the reference signal is compared with the center instant of a line synchronizing pulse. When the control loop is in the pulled-in state, it is changed by the coincidence detector to compare the leading edge of a line synchronizing pulse to the center instant between the said edge of the reference signal and its first preceding edge.

Abstract: The present invention is a phase-locked circuit for use in digital circuits such as a high frequency clock generator, counter and memory. The circuit provides an output which is locked to the received input tone signal in both frequency and phase.

Abstract: A disciplined oscillator system having a standard oscillator which is automatically corrected for both frequency errors and time error accumulation to a constant frequency signal which is derived from the WWVB carrier frequency and the WWVB TIME CODE to maintain overall frequency accuracy within one part in 10.sup.9 notwithstanding oscillator aging and in spite of jitter and distortion due to propagation delays and noise which may cause loss of, or time jitter in, the WWVB signals. Frequency errors are detected through the use of a counter (24) having a measurement accuracy greater than one part in 10.sup.10. An error detector (26) derives correction signals by averaging a plurality of frequency variances obtained in successive measurement cycles.

Abstract: A phase-lock system including an oscillator providing a switching output that continuously switches between first and second states, a trigger circuit for inducing switching of the oscillator, a sensing circuit monitoring the switching output and providing an anticipating indication of an imminent switching thereof from the first to the second state, and a primary voltage source providing a variable voltage that periodically varies from and returns to a given voltage level. Also included is a detector circuit monitoring the variable voltage and detecting the presence of the given voltage level and a synchronizing circuit responsive to the sensing and detector circuits and providing an input to the trigger circuit, the synchronizing circuit being operative to cause switching of the oscillator in response to the simultaneous provision of the anticipating indication by the sensing circuit and detection of the given level by the detector circuit.