Abstract: An integrated frequency source with an integrated frequency standard and an integrated frequency synthesizer is disclosed. A voltage-controlled oscillator in the frequency standard is eliminated with a resulting improvement in phase noise. A reference frequency in the frequency standard is provided directly to the frequency synthesizer. The integrated frequency source is put on frequency over temperature by storing reference frequency errors over temperature in a lookup table, measuring the temperature, and calculating in a microprocessor synthesizer control data that offsets the synthesizer to compensate for reference frequency errors.

Abstract: Circuitry for a phase locked loop (PLL) includes a first frequency doubler; a first equalizer having an input coupled to an output of the first frequency doubler; a second frequency doubler having an input coupled to an output of the first equalizer; and a second equalizer having an input coupled to an output of the second frequency doubler and an output which is fed into the PLL. Each frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The combination of the two frequency doublers in series quadruples the reference signal into the PLL, which allows the, PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter. Advantageously, controls for the selection of the initial reference signal are provided.

Abstract: A multi-loop phase lock loop (PLL) contains multiple loop filters, each having different bandwidths. The multi-loop PLL receives one of multiple high-frequency clock signals as an input. A phase detector outputs a signal, based on the phase difference between the high-frequency clock signal and a feedback signal to the loop filters. A voltage controlled oscillator generates an output clock signal based on signals received from the loop filters. During a clock switch over sequence between the multiple high-frequency input clock signals, the multi-loop PLL uses one of its loop filters with a wide bandwidth to quickly lock the input clock signal. Once the clock signal is locked, a narrower bandwidth loop filter in the PLL is then used to reduce jitter in the locked signal.

Abstract: A Phase-locked Loop (PLL) (204) that is dynamically and automatically altered in response to changes in the jitter of the input is disclosed. The Analysis Block (304) receives one or more inputs from the PLL operation. The output of the Analysis Block (304) triggers a change in the Parametric Control Block (308) which in turn imparts changes on the gains of one or more of the various components or the value of &ohgr;N of the PLL Low Pass Filter (116). The dynamic change to at least one parameter of the PLL adjusts the tradeoff between removing as much of the jitter as possible and having a responsive system that has a reduced risk of buffer underflow or overflow. This abstract is provided as a tool for those searching for relevant disclosures, and not as a limitation on the scope of the claims.

Abstract: The invention relates to a frequency synthesis device comprising a direct digital synthesis device (22) for producing by calculation a signal oscillating at a determined frequency (Fdds), the calculation being performed by a logic circuit clocked by a clock signal (Sh) having a determined clock frequency (Fh), characterized in that it further comprises transposition means (74) for transposing the signal which oscillates at the determined frequency (Fdds) using the clock frequency signal (Sh), the signal thus transposed being supplied as an output (Sref).

Abstract: The invention relates to a method for adjusting an oscillator (44), a packet switched network (21) locating between the oscillator and a specified time source (31), which knows a clock time with a specified accuracy. In the method, a clock (42), which is on the same side of the packet switched network (21) as the adjustable oscillator (44), is updated over the packet switched network (21) on the basis of the clock time known to said time source (31). Said clock (42) is used in the adjustment of the oscillator (44) for making the oscillator (44) to oscillate at a desired frequency. The invention also relates to an apparatus and computer software for adjusting the oscillator. (FIG.

Abstract: Feedback methods and systems are provided to achieve rapid switching of oscillator frequencies without compromising operational feedback loop bandwidths that filter out spurious tones and phase noise to thereby enhance loop spectral and noise performance. The methods respond to frequency changes in a reference signal by providing an open-loop drive current to drive a feedback signal towards the reference signal. The drive current is terminated and the feedback control loop closed when the feedback signal is within a predetermined acquisition range of the reference signal. This is determined by successively comparing a feedback frequency of the feedback signal to a destination frequency of the reference signal over a comparison window of time. The invention also provides a feedback control system that practices the invention's methods.

Abstract: An electric low-pass filter with blocking behavior for a predetermined rejection frequency, comprising a series connection including a FIR filter and an IIR filter, with the parameters of the FIR filter being matched in essence with respect to the blocking behavior at the rejection frequency and the parameters of the IIR filter being matched in essence with respect to the low-pass behavior. It is possible with such a filter to obtain good low-pass behavior with very high attenuation of the frequency to be rejected, with relatively low circuit expenditure and high stability with respect to oscillation tendency.

Abstract: A phase-synchronizing circuit includes a phase error detection circuit detecting a phase-error in a given clock signal and producing an output indicative of the phase-error as a first phase-error signal, a phase-error creating circuit creating a second phase-error signal determined so as to minimize a time for establishing a phase-synchronization for the clock signal, and a selection circuit selectively supplying the first or second phase-error signal selectively to a phase control circuit.

Abstract: A method and a device for reducing cycle slips resulting from frequency hops in a wireless communication device. In the method, a first signal pulse is received, which first signal pulse is either said reference signal pulse or said signal pulse to be compared, a second signal pulse is received, which second signal pulse is from another source than said first signal pulse, a control voltage is generated for controlling a voltage controlled oscillator in response to a phase difference between said first received and said second received signal pulses. At a time instant between the reception of said first and said second signal pulses, a constant voltage is added to said control voltage on receiving additionally one signal pulse, which is the same type as said first signal pulse. After receiving said second signal pulse, said constant voltage is removed from said control voltage on receiving at least one signal pulse, which is the same type as said second signal pulse.

Abstract: A frequency-adjustable oscillator suitable for digital signal clock synchronization comprises a crystal oscillator circuit for generating a driving signal and having a voltage-variable control input for adjusting a frequency of the driving signal, a phase detector circuit for generating a phase offset signal, a filter which operates on the phase offset signal to produce a VCO control signal, a voltage controlled oscillator circuit operably linked to the filter and responsive to the VCO control signal for generating an analog controlled-frequency signal, a frequency divider circuit for generating a reduced frequency feedback signal in response to the controlled-frequency signal, and a sinewave-to-logic level translator circuit for generating a digital output signal having substantially the same frequency as the controlled-frequency signal. The crystal oscillator circuit includes a discrete varactor responsive to the control input and a fundamental mode AT-cut quartz resonator.

Abstract: A high-resolution apparatus and method provide direct digital measurement of electrical properties such as resistance, capacitance or inductance. An excitation signal derived from a high-frequency source is applied to a network containing an unknown device to produce a network output signal with an amplitude that corresponds to the electrical property to be measured. Amplitude variations in the network output signal are converted to corresponding phase variations in a third signal by adding the network output signal to a reference signal that is phase shifted by 90-degrees with respect to the excitation. The third signal is then applied to a phaselocked loop that employs the above-mentioned high-frequency source in combination with a pulse delete circuit to produce an output that multiplies phase information contained in the third signal by orders of magnitude.

Abstract: A frequency synchronous apparatus includes a switch, frequency division circuit, phase comparison circuit, frequency adjustment and calculation circuit, memory, conversion circuit, and voltage-controlled oscillator. The switch selects either one of a highly stable clock output and a reference clock output in accordance with a mode switching signal. The frequency division circuit divides the frequency of the synchronous clock. The phase comparison circuit detects the phase difference between an output clock from the frequency division circuit and an output clock from the switch, and outputs a phase difference value. The frequency adjustment and calculation circuit performs synchronous control so as to adjust the phase difference value output from the phase comparison circuit to 0, and outputs a synchronous control value at this time. The memory holds the synchronous control value output from the frequency adjustment and calculation circuit.

Abstract: A PLL circuit produces first to n-th (n being an integer equal to or greater than 2) reference signals. A first variable frequency divider divides the frequency of an output of a voltage-controlled oscillator to produce a first feedback signal. A second variable frequency divider divides the output of the voltage-controlled oscillator to produce second to n-th feedback signals. A phase comparator compares the phases of the first to the n-th reference signals with the phases of the first to the n-th feedback signals to produce first to n-th error signals. A controller produces a control signal from the error signals. The PLL circuit synchronizes the first reference signal with the first feedback signal in phase after the phase difference between at least one of the first to n-th reference signals and a corresponding feedback signal becomes smaller than a predetermined value. The frequency-division ratio of the second variable frequency divider is 1/n that of the first variable frequency divider.

Abstract: A receiver uses an adaptive algorithm to tune a low-cost crystal oscillator according to a temperature compensation profile so as to produce a precision master reference frequency despite temperature, initial tolerance, and aging effects. An automatic frequency control system also tunes the crystal oscillator. The adaptive algorithm adjusts the temperature compensation profile for the crystal oscillator according to the adjustments made by the automatic frequency control should a received signal's quality factor exceed that associated with the temperature compensation profile.

Abstract: A direct digital frequency synthesizer and a hybrid frequency synthesizer combining the direct digital frequency synthesizer and a phase locked loop is provided. The direct digital frequency synthesizer includes a phase accumulator that is configured to generate a discrete phase signal. Spurious phase modulation in the discrete phase signal is reduced by a noise shaper, and the output of the noise shaper is then used to address a phase-to-amplitude translator. The phase-to-amplitude translator generates a discrete waveform which is converted to a continuous waveform by a digital to analog converter. The hybrid frequency synthesizer uses a mixer to combine a reference frequency generated by a reference source and a DDFS output signal generated by a direct digital frequency synthesizer. The output from the mixer is then coupled to the input of a phase locked loop which multiplies the mixer output to generate the frequency synthesizer output.

Abstract: An oscillator 10 with a noise reduction function has a memory 80 that memorizes modulation data DM for performing the spread spectrum modulation input from an output terminal fout, a modulation signal output circuit 60 that generates a modulation signal SM from the modulation data DM memorized in the memory 80, and a mixer 53 that overlays the modulation signal SM on the control voltage VC of a voltage control oscillator (VCO) 54 of a PLL circuit 50, and it becomes possible to output a spread spectrum modulated output signal CLv under a specification desired by a user by memorizing in the memory 80 the modulation data DM that corresponds to the spread spectrum modulation the user tries to set.

Abstract: An oscillating circuit (10) includes a quartz crystal oscillator (12) for generating a clock signal (20). The clock signal is synchronized to a master signal (19) during the lock-in periods when the oscillating circuit (10) has access to the master signal (19). During the holdover periods when the oscillating circuit (10) loses access to the master signal (19), an oscillation frequency function predicts the crystal oscillation frequency in terms the physical parameters, e.g., time and temperature, that may affect the crystal oscillation frequency. The predicted frequency is compared with a standard frequency to generate an error signal. In response to the error signal, a fraction handler block (28) determines whether adding cycles to or deleting cycles from the clock signal, thereby calibrating the oscillation signal (13) of the oscillating circuit (10).

Abstract: The present invention relates to a frequency synthesis system and device using a phase locked loop.

Abstract: A polyphase, noise-shaping, fractional-N frequency synthesizer utilizes multiple, parallel fractional-N divider channels to deliberately decorrelate noise and improve spectral purity. The synthesizer comprises a voltage controlled oscillator (VCO), a reference signal source to produce a plurality of different reference signals, a loop integrator, a plurality of desynchronized divider channels and a signal summer. Each divider channel comprises a frequency divider, a fractional-N control logic and a phase detector. Each divider channel divides an output signal from the VCO by a variable division factor and compares the divided signal to a different reference signal to produce an error signal. The signal summer combines the error signals from the desynchronized divider channels into a combined error signal. The loop integrator integrates the combined error signal to produce a control voltage that is applied to the VCO.

Abstract: A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.

Abstract: A frequency synthesizer (500) includes a DDFS (502) and a PLL loop (526). The oscillator frequency signal (516) is used to create the DDFS clock signal (514), fCLK that acts as a system clock for the DDFS (502). With the phase/frequency state of the DDFS being adjusted based on a comparison of the DDFS system clock signal (514) with a frequency reference signal (520), fREF. The DDFS system clock signal (514) is further divided by a divider (512) to establish an update clock signal (528), fupdate. The output of the DDFS and the update clock signal (528) are compared by a phase/frequency detector (504). The output signal of the PFD (504) is preferably filtered by a loop filter (506) before using it as a tuning signal (522) for the DCO (508). The principle of bootstraping ensures that the synthesizer (500) is synchronous and every clock is derived from the same source.

Abstract: A precision oven-controlled crystal oscillator (OCXO) uses an adjustment feedback signal that, when mixed with a reference signal from a stable reference oscillator, accurately controls the generation of an output signal from a voltage controlled crystal oscillator (VCXO). An OCXO according to the invention has high stability and high accuracy. The digital OXCO can be manufactured at low cost, and is particularly beneficial for Code Division Multiple Access (CDMA) base station applications in cellular communication networks an the like.

Abstract: The invention relates to a phase-locked loop, comprising: an oscillator OSC intended to produce an output signal Vlo, a frequency divider DIV intended to receive the output signal Vlo from the oscillator OSC, and a phase/frequency detector PD intended to compare the frequency FDIV of the output signal Vdiv of the divider DIV with the frequency of a comparison signal Vcomp, and to supply a tuning signal Vtun to the oscillator, which tuning signal defines the oscillation frequency of the oscillator, A phase-locked loop in accordance with the invention is provided with correction means PMOD intended to detect a parasitic phase modulation applied to the output signal Vlo of the oscillator OSC, and to apply a phase modulation, which is similar to said parasitic phase modulation, to the comparison signal Vcomp.

Abstract: An arrangement for generating a first alternating signal and a second alternating signal that is in a predetermined, fixed frequency relation to the first signal. The arrangement may be used as a time based generator for a level meter that operates according to the radar principle and whose measuring system is based on the time domain reflectometry (TDR) measuring principle.

Abstract: A signal generator includes an oscillator, a phase locked loop and a fractional divider. The oscillator is configured to provide an output signal. The phase locked loop is configured to receive the output signal and to provide a tuning signal to the oscillator. The phase locked loop has a phase detector configured to receive the output signal, to compare the output signal to a reference signal, and to provide the tuning signal to the oscillator based on the comparison. The fractional divider is outside of the phase locked loop and is configured to generate the reference signal.

Abstract: A digital processing PLL circuit includes a phase difference computing unit for comparing a first clock signal inputted from.a reference clock generator and a second clock signal fedback from a VCO and computing a phase difference value during a calculation time unit; a control unit for controlling a manner that a phase difference correcting value corresponding to the phase difference value is read from a predetermined look-up table and the output clock signal of the VCO is synchronized with the first clock signal; and a memory unit for storing the look-up table. The value of the phase difference between the reference clock and the output clock for the calculation unit is computed with hardware by using an adder and a buffer. The CPU reads the corresponding phase difference compensation value directly from the look-up table and performs synchronous controlling.

Abstract: A system and method for programming a digitally tunable oscillator is provided. A desired output frequency is received. A tuning effect of a set of digital tuning words on a crystal resonant frequency is determined, and valid parameters of an algorithm for translating and tuning the crystal resonant frequency to a value within an error tolerance of the desired frequency, based on the determined tuning effect are calculated. Valid parameters are preferably calculated based on an intermediate tuning value, sorted by ascending divide parameter of the algorithm, and then evaluated in sorted order for ability of a tuning effect to null frequency error to within the error tolerance. The valid set of calculated parameters are then programmed into a nonvolatile memory. The oscillator control parameters may remain unprogrammed until all necessary parameters are defined.

Abstract: A signal generator (100) receives an input clock signal (X1) at a first frequency (F1) and derives an output clock signal (Y) at a second frequency (FY). An arrangement (110) using a first intermediate signal (Z) receives the input clock signal (X1) and provides a second intermediate signal (X2) by selectively providing transitions (119) of the second intermediate signal (X2) at time intervals (T2(n)) that are determined by a variable number (A+P(n)) of periods (TZ) of the first intermediate signal (Z). The second intermediate signal (X2) has a frequency (F2) that is in average (F′2) higher than the first frequency (F1). A phase-looked loop (PLL) circuit (180) locks at this average frequency (F′2) and provides the output clock signal (Y).

Abstract: An improved clock generation circuit is provided that operates with a single input clock frequency, and includes a Phase Locked Loop circuit (PLL) with a digital accumulator in the feedback loop, in which either the Most Significant Bit or the Carry Bit of the binary adder is used as the modulated feedback clock to the phase/frequency detector of the PLL. In one embodiment, a fixed add/phase amount is used to drive one of the inputs of the binary adder to generate a fixed output frequency. If it is desired to modulate the output frequency, then an Add Amount Modulator circuit can be provided that presents a varying numeric value to one of the inputs of the binary adder. The MSB or Carry Bit is communicated to an address look-up table, which then outputs an address to a memory circuit, which in turn presents a different add amount to the binary adder.

Abstract: A method and apparatus are disclosed for numerically controlling a ring oscillator. The disclosed programmable period ring oscillator selectively switches pairs of inverters into or out of the ring oscillator to provide a desired frequency. In one implementation, a programmable period ring oscillator provides a range of five to nine inverters that may selectively be included in the ring oscillator in increments of two inverters. A frequency synthesizer is disclosed that aligns the phase of the programmable ring oscillator with a reference signal. The frequency synthesizer generates a phase difference signal that is that is representative of the phase difference between the reference signal and the ring oscillator output. The phase difference signal is utilized to correct the frequency of the ring oscillator, so that the mean phase of the ring oscillator corresponds to the mean phase of the reference signal.

Abstract: A frequency reference is employed to correct a frequency error in a signal synthesizer. The frequency reference provides a reference frequency with a parts per million deviation from the reference's nominal frequency. The reference frequency parts per million deviation is equal in magnitude to the parts per million deviation of the frequency error from a desired signal synthesizer output frequency. The deviation in the reference frequency offsets the deviation from the desired output frequency to significantly reduce the frequency error. The frequency reference includes a voltage controlled oscillator, programmable voltage generator, and voltage control engine. The reference frequency is set by the voltage controlled oscillator in response to a frequency setting voltage from the programmable voltage generator. The voltage control engine is coupled to the programmable voltage generator to provide a voltage setting value that controls the frequency setting voltage.

Abstract: Methods and systems are disclosed for eliminating a phase transient of a controlled frequency oscillator, caused by replacing a first reference signal by a second reference signal when the first reference signal becomes corrupted or otherwise unavailable, and for running a controlled frequency oscillator in a frequency-controlled holdover mode. The contradictory requirements of using a relatively low-cost controlled frequency oscillator tunable over a relatively wide frequency range and achieving high stability of its frequency in holdover mode are satisfied.

Abstract: A phase-lock loop (PLL) is formed by a voltage-controlled oscillator (51), a local optical pulse source (2), an optical branching device (12) for branching the locally generated optical pulse stream from the local optical pulse source (52), a harmonic component local generation part (30) for locally generating harmonic component electrical signal from the one of two branched locally generated optical pulse streams, and a phase comparison part (40) for comparing the phases of the locally generated harmonic component electrical signal and an incoming signal component electrical signal generated from an incoming optical signal pulse stream and for supplying the voltage-controlled oscillator (51) with a control voltage corresponding to the phase difference between the two input electrical signal. The other branched output from the optical branching device (12) is output as a locally generated optical pulse stream bit-phase synchronized with the incoming optical signal pulse stream.

Abstract: The invention relates to: An electronic circuit for controlling the output frequency from a frequency synthesizer, said output frequency being based on a reference frequency from a voltage controlled crystal oscillator (VCXO), the latter being regulated by a D/A converter controlled by a processing circuit that monitors a frequency error. The invention further relates to a method and a computer program, a computer readable medium and a dual mode mobile telephone. The object of the present invention is to provide a simple and economic scheme for overcoming the temperature limitations of a VCXO based frequency synthesizer.

Abstract: A method and apparatus of an integrated frequency hopping/GPS receiver and a corresponding frequency synthesizer are described.

Abstract: The high frequency oscillator comprises a reference oscillator, a phase-locked loop circuit with a phase frequency detector, a charge pump, a ring oscillator and a divider, the reference oscillator being coupled to the phase frequency detector for frequency control. The ring oscillator is a symmetrical delay cell oscillator containing two amplifiers with a dual output stage for providing I/Q output signal generation. The reference oscillator works in the range of 1,25-1,5 GHz and is a Colpitts type digital controlled frequency synthesizer with an external tank circuit for providing a low phase noise, and the dividing factor of the divider is four for providing a tuned output range of 5 to 6 GHz. The phase-locked loop circuit is integrated together with the reference oscillator into an integrated circuit, using advantageously a BICMOS Silicon/Germanium process, which is well suited for RF applications.

Abstract: A cut-off state of a carrier signal or a carrier signal outside an effective range of a frequency is detected by a carrier detector, and a signal switching circuit inputs a clock 2 from an external device into a phase comparator in place of the carrier signal, with which a locked state is maintained in a PLL comprising the phase comparator, a charge pump, a loop filter, a voltage control oscillator, and a 1/N divider, so that a high-speed locking operation is realized to another appropriate carrier signal.

Abstract: A direct digital frequency synthesizer and a hybrid frequency synthesizer combining the direct digital frequency synthesizer and a phase locked loop is provided. The direct digital frequency synthesizer includes a phase accumulator that is configured to generate a discrete phase signal. Spurious phase modulation in the discrete phase signal is reduced by a noise shaper, and the output of the noise shaper is then used to address a phase-to-amplitude translator. The phase-to-amplitude translator generates a discrete waveform which is converted to a continuous waveform by a digital to analog converter. The hybrid frequency synthesizer uses a mixer to combine a reference frequency generated by a reference source and a DDFS output signal generated by a direct digital frequency synthesizer. The output from the mixer is then coupled to the input of a phase locked loop which multiplies the mixer output to generate the frequency synthesizer output.

Abstract: A cut-off state of a carrier signal or a carrier signal outside an effective range of a frequency is detected by a carrier detector, and a signal switching circuit inputs a clock 2 from an external device into a phase comparator in place of the carrier signal, with which a locked state is maintained in a PLL comprising the phase comparator, a charge pump, a loop filter, a voltage control oscillator, and a 1/N divider, so that a high-speed locking operation is realized to another appropriate carrier signal.

Abstract: A reference frequency signal switching circuit of the invention comprises: a internal oscillator for generating an internal reference frequency signal; an external reference frequency signal input terminal to which an external reference frequency signal is supplied; and a signal switching circuit for selectively outputting the internal reference frequency signal and the external reference frequency signal. Since an output level adjusting circuit for setting the external reference frequency signal outputted to a reference frequency signal output terminal so as to be at a predetermined level is provided, the output level can be made constant.

Abstract: A frequency synthesizer architecture naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase-domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information.

Abstract: A generator (50) able to be fitted to a clockwork system including a crystal (51a) used as a time base, includes a first oscillator (51) able to supply a first frequency (f1), a second oscillator (56) able to supply a second frequency (f2), a divider (60) able to supply a third frequency (f3) from the second frequency, a comparator (52) able to compare the third and first frequencies, and a control loop including a filter (54) connected to the comparator and able to control the second oscillator. The generator is characterised in that it includes a component (58) able to provide an indicator (LCK) containing the state of the loop, and in that the filter (54) can receive the indicator (LCK) and, in response, have a narrow (or respectively wide) band, when the loop is (or respectively is not) locked.

Abstract: This invention is a remotely controllable clock circuit embodied in a single integrated circuit device. The clock circuit includes at least one externally writable clock control register, a reference clock input, a controllable oscillator circuit, a pre-scalar circuit and a comparison circuit. The comparison circuit controlling the frequency of the controllable oscillator circuit to achieve a frequency match between a pre-scaled reference clock signal and a pre-scaled oscillator clock signal. The pre-scale divide factors are stored in respective fields in the clock control register. The clock control register may be memory mapped into a device memory space, accessed via an indirect access register or accessed via a serial scan chain.

Abstract: A method and lock detector for detecting lock between a reference signal and a feedback signal of a PLL circuit. A number of clock cycles of the feedback signal is counted during consecutive test intervals defined by the reference signal. A feedback comparator determines whether the number of clock cycles of the feedback signal during a given test interval is within an expected range. Before lock has been indicated, a qualification counter is either incremented or reset after each test interval in accordance with the expected range determination. A lock indication signal indicating that lock has been achieved is provided if said qualification counter exceeds a qualification threshold.

Abstract: A phase locked loop (PLL) circuit is provided having: (1) a phase detector coupled to a reference clock signal and a feedback signal for generating positive and negative phase detection signals corresponding to the phase difference between the reference clock signal and the feedback signal; (2) an integrator coupled to the positive and negative phase detection signals for generating an output voltage proportional to the pulse width of either the positive or negative phase detection signals, the integrator including an operational amplifier having positive and negative inputs; (3) a voltage controlled oscillator coupled to the output voltage of the integrator for generating a local oscillator signal with an oscillation frequency proportional to the output voltage of the integrator; (4) a feedback circuit coupled to the local oscillator signal for generating the feedback signal; and (5) an analog holdover circuit for generating an input to the integrator when the phase detector stops receiving the reference clo

Abstract: A frequency synthesizer (500) includes a DDFS (502) and a PLL loop (526). The oscillator frequency signal (516) is used to create the DDFS clock signal (514), fCLK that acts as a system clock for the DDFS (502). With the phase/frequency state of the DDFS being adjusted based on a comparison of the DDFS system clock signal (514) with a frequency reference signal (520), fREF. The DDFS system clock signal (514) is further divided by a divider (512) to establish an update clock signal (528), fupdate. The output of the DDFS and the update clock signal (528) are compared by a phase/frequency detector (504). The output signal of the PFD (504) is preferably filtered by a loop filter (506) before using it as a tuning signal (522) for the DCO (508). The principle of bootstraping ensures that the synthesizer (500) is synchronous and every clock is derived from the same source.

Abstract: The invention relates to a phase-locked loop, comprising:

Abstract: A shape modulation transmit loop with digital frequency control permits spectral shaping of a digital pulse stream (12) by controlling the slew rate of the transition signal (16) between successive pulses. The loop is formed when the digital data stream is fed into an up/down counter (152) whose output is coupled to a programmable memory means (154), such as RAM, EEPROM, flash memory or similar electronic storage means. The output (108) of the programmable memory (154) forms a first input to an adder (112) which drives an accumulator (52) with specified steps. Values corresponding to the desired waveform (70) are stored in a lookup table (60) which is coupled to a digital-to-analog conversion circuit (64) which uses the values in the lookup table (60) to construct a sine wave output signal (70) corresponding to the frequency set by the current specified step of the up/down counter (152).

Abstract: A frequency generation device (100) comprises a cascade of two phase-locked loops (104 and 108). The first PLL (104) is a frequency synthesizer while the second PLL, or offset loop (108), comprises a phase detector (208 or 306), loop filter (210 or 310), VCO (212 or 312) and a divider with near-unity modulus (204 or 308). In the case of a negative offset design, the near-unity divider (204) is placed in the offset loop feedback path. In a positive offset design, the near-unity divider (308) is placed in the path between the synthesizer VCO and the offset loop phase detector. Unlike existing art, there is no offset signal input to the second or offset loop (108).