Abstract: A PLL circuit includes a phase comparator that compares an external synchronizing signal and an internal synchronizing signal to detect a phase difference therebetween, and a voltage-controlled oscillator that generates the internal synchronizing signal by oscillation thereof. The frequency of the voltage-controlled oscillator is controlled depending upon the phase difference, so that the internal synchronizing signal becomes in phase with the external synchronizing signal. A limiting device is provided, which limits the phase of the external synchronizing signal supplied to the phase comparator to be within a predetermined window period that includes the timing of generation of the internal synchronizing signal.

Abstract: A universal synchronizer for use in a variety of telecommunications systems based on direct digital phase synthesis (DDPS) include digital and analog PLLs. The synchronizer may be used for wireless, optical, or wireline transmission systems and for a wide ranges of data rates. Digital phase detectors are used in the digital PLLs for comparing the phase of the local clock f.sub.L with the phase of a respective digital reference clock, and provides a respective phase error signal. A digital phase synthesis unit receives the phase error signal and a target phase error and produces a first and a second set of control signals for driving an error driver. The error driver generates the control voltage for adjusting the frequency of a VCXO that is used for all PLLs, to lock the respective PLL. The first set of control signal generates the control voltage for the digital PLLs, and the second set of control signals generates the control voltage for the analog PLLs and for the acquisition mode of operation of all PLLs.

Abstract: A phase-locked loop (PLL) system including a voltage-controlled oscillator, a divider, a phase detector, and a low-pass filter. The voltage-controlled oscillator has two control input terminals S and L and generates a pulse signal having an oscillation frequency fout2. The divider generates a pulse signal having a frequency fout2/N2 from the output signal of the oscillator. The phase detector detects the phase difference between the pulse signal output from the divider and the a pulse signal having a reference frequency fref and generates an error signal corresponding to the phase difference detected. The low-pass filter integrates the error signal. The output signal of the low-pass filter is input to the control input terminal S of the oscillator. A control signal is input to the control input terminal L of the oscillator to control the free-running frequency of the oscillator.

Abstract: A numerically controlled oscillator including an RTS value producing circuit which produces a series of residual time stamp (RTS) values indicative of a relation between the setting value and an actual oscillation frequency. A pulse train generator generates a pulse train in a period corresponding to the produced series of RTS values and a phase synchronous oscillator oscillates at a frequency in synchronism with the pulse train output from the pulse train generator. Preferably, the pulse train generated by the pulse train generator is supplied to the RTS value producing circuit as a signal indicative of the actual oscillation frequency.

Abstract: An optical PLL circuit with high precision that has its simplified configuration. An optical-intensity modulator creates difference frequency information (N.times..DELTA.f) by modulating a received optical signal formed of signal optical pulses of a repetitive frequency (N.times.f0) with a reference signal of a frequency (f0+.DELTA.f) and implementing an AND operation of them. The signal is converted into an electric signal by a photo diode. A band-pass filter extracts only the low frequency component (N.times..DELTA.f). A frequency divider produces a frequency component .DELTA.f by dividing the extracted component by N. A multiplier receives the reference signal and the output signal f of a voltage-controlled oscillator and then creates the difference frequency component ((f0+.DELTA.f)-f). A phase comparator compares the low frequency component .DELTA.f with the difference frequency component ((f0+.DELTA.f)-f) and controls the voltage-controlled oscillator to set the phase difference between them to zero.

Abstract: A phase locked loop comprises a voltage controlled oscillator, a 1/n frequency demultiplier, a phase comparator, and a modulation circuit. The phase comparator is supplied with a first signal which varies according to a reference clock signal and a second signal which varies according to a feedback signal supplied from the 1/n frequency demultiplier, executes phase comparison between the two signals, and controls the oscillation frequency of the voltage controlled oscillator by varying a control voltage by outputting an up-control signal or a down-control signal depending on phase difference between the signals. The modulation circuit generates the first signal by periodically modulating the reference clock signal with a shift width which is larger than the dead zone width of the phase comparator, and supplies the phase comparator with the first signal.

Abstract: Apparatus, and an associated method, for calibrating a device responsive to values of a reference signal. The reference signal may be subject to short-term disturbances. In one implementation, a cellular radio base station utilizes a Stratum-2 oscillator to which to phase-lock a base station VCO. Compensation is made for the aging of the Stratum-2 oscillator, thereby to provide a regulation signal causing the VCO to exhibit acceptable short-term and long-term frequency stability characteristics.

Abstract: A frequency synthesizer having reduced spurious components for use in a receiving and transmitting apparatus. The frequency synthesizer includes a direct digital synthesizer (DDS) for generating a first signal having a first frequency determined by channel setting data. The first signal is applied to a frequency divider to generate a divided signal having a divided frequency. The divided signal is applied to a frequency converter for shifting the divided frequency by a shift frequency interval to provide a reference signal having a reference frequency. The reference signal is applied to a phase locked loop (PLL) for generating a final signal having a predetermined frequency characteristic.

Abstract: A frequency synthesizer operating according to fractional frequency synthesis, has a phase-controlled oscillator, a phase detector that controls this oscillator, a loop filter arranged in a control line between the phase detector and the oscillator, a reference frequency source and a frequency divider arranged between this reference frequency source and one input of the phase detector, which frequency divider can be adjusted to whole-number division ratios. The frequency synthesizer also has an adjustment device that operates with multiple integration, by which the whole-number division ratio of the frequency divider is controlled such that a fractional division ratio corresponding to a desired fractional rational division ratio is simulated. The other input of the phase detector is connected with the output of the oscillator via a mixer, wherein a difference is formed of the output frequency of the oscillator and the reference frequency of the reference frequency source.

Abstract: An A/D converter performs sampling of a reproduced signal from a reading device in synchronism with a clock signal from a PLL circuit and outputs the sampled value to a binary circuit and a phase comparator. The phase comparator detects a change from a positive sampled value to a negative one or from the negative sampled value to a positive one (zero-cross) and outputs a phase error signal corresponding to the zero-cross to a frequency comparator. The frequency comparator outputs a frequency error sensed in reference to a variation of the phase error signal to a switch through a low pass filter. The switch outputs the frequency error to an adder only when the PLL is not in a lock state. The adder outputs a sum of the frequency error and the phase error to a VCO through a loop filter. The VCO generates the clock signal with a frequency corresponding to the sum and supplies it to the A/D converter.

Abstract: A data and clock recovery arrangement, for a high speed fiber optic digital communication system in which a serial digital bit stream is pre-scramble encoded by interleaving complementary pairs of overhead bits between successive groups of data bits, and then scrambled and transmitted to a receive site, comprises a data rate independent variable bit rate synchronizer, a descrambler and a decoder. The data rate independent variable bit synchronizer processes the received scrambled and encoded digital bit stream to derive a variable data rate synchronization clock signal. The synchronizer is capable of accepting any data rate within the operational data clock signal range of the system, and automatically tunes itself to the data clock signal embedded in the received scrambled and encoded serial data stream, so as to output respective scrambled and encoded serial data and clock signals.

Abstract: A phase-locked loop implemented in all-digital components uses a stochastic approach to detect errors in phase position and relative velocity. Using a history circuit and an adjustment-intensity selection circuit appropriate corrections in phase and frequency are made. The history circuit keeps a running record of a series of binary results (0 or 1) as received from a phase comparator. History components collected include the number of consecutive oscillator periods in which the phase offset (0 or 1) has remained the same and the number of oscillator periods in which the phase offset count has not exceeded 1.

Abstract: An improvement on the phase-locked loop (PLL) circuit, in which an amplifier is disposed at the modulating signal input end of the PLL, and the output end of the amplifier is connected in series to a resistor and an inductor, followed by a resistor connected to a higher DC bias as well as a variable capacitance diode connected to ground. In such a way, the variable capacitance diode is under the higher bias and thus has a smaller capacitance change, while having its Q-value property opposite to the resonance curve formed by the crystal unit of an oscillator which is associated in parallel with the variable capacitance diode, thereby forming in a good compensation for the linearity of the circuit architecture and achieving an ideal frequency deviation and a reduced distortion caused by the modulation.

Abstract: A transceiver signal processor for a digital cordless communication apparatus adopts a heterodyning loop in order to improve the transmitting circuit and power efficiency. The transceiver signal processor adopts an orthogonal demodulation method for a first intermediate frequency, thereby allowing a single reference loop. Since the reference loop itself need not be switched, a frequency drift problem is fundamentally removed.

Abstract: A phase lock loop wherein the reference clock is divided by a variable divider which is capable of dividing the reference clock by a divider ratio of 2, 3, 4, . . . or M depending on the value of a control signal. The control signal is generated from a divider controller in response to a controller input. The noise shaping characteristics of the divider controller results in dithering of the variable divider ratios such that the average frequency of the divided reference clock is at the desired comparison frequency but the quantization noise from the fractional divide is pushed from low frequency to high frequency where it is more easily filtered. The noise shaper can be implemented with many bits of resolution to allow for a wide frequency control range and high frequency accuracy. A dither circuit to prevent limit cycling at the output of the noise shaper.

Abstract: A synthesized oscillation circuit that can relax a limitation of the maximum operational frequency. A mixer (MX), a bandpass filter (BPF), an amplitude limiting amplifier (LIM), a phase detector (PD), a low-pass filter (LPF), and a voltage-controlled oscillator (VCO) are serially connected between a signal input terminal (IN) and a signal output terminal (OUT). The signal output terminal (OUT) is connected the mixer (MX) and the phase detector (PD). The bandpass filter (BPF) has a filtering characteristic which blocks the sum frequency component of the frequency component of an input signal from the signal input terminal (IN) to the mixer (MX) and the frequency component of an output signal from the voltage-controlled oscillator (VCO) to the mixer (MX), but which passes the difference frequency component between them.

Abstract: A communication device (104) comprises a receiver circuit (108) receiving a modulated receive signal. A reference oscillator (132) generates a first clock signal at a first frequency, the first clock signal having harmonics. Circuitry (130) coupled to the reference oscillator and to the receiver responds to the first clock signal to produce a signal used by the receiver to reduce the frequency of the modulating signal. A frequency spreading circuit (134) is also coupled to the reference oscillator to modulate the first clock signal with a frequency spreading signal to produce a modulated clock signal including modulated harmonic frequency components. The frequency spreading circuit selectively combines the frequency spreading signal and the first clock signal. A control circuit (114) controls the frequency spreading circuit to modulate first clock signal with the frequency spreading signal when the selected received signal includes a harmonic of the first clock signal.

Abstract: A power management system is disclosed. The system includes an oscillator interface for use in a power management system, a power recycle circuit for use in a power management system, a pad clock and self test for use in a power management system, a clock enable circuit for use in a power management system, a power level detect circuit for use in a power management system, an internal source clock generation circuit for use in a power management system, and a power-save mode change detection circuit for use in a power management system. The oscillator interface includes an interface circuit for interfacing with an external oscillator used as a source of oscillations. A clock stabilization filter masks out spurious crystal frequencies in the oscillations during start-up of the power management system following an enabling of a feedback loop. The clock stabilization filter has circuitry which provides that the oscillations will start with a rising transition after filtering.

Abstract: A variable divider in which a dividing number setting parameter can be set is provided in a reference oscillator. When a frequency setting parameter is selected so that a DDS will not output a spurious at a specified level or at a level higher than the specified level within an output band of an PLL in response to an output frequency from the PLL, both a conversion function setting parameter for a variable divider in the PLL and a dividing number setting parameter for a variable divider in the reference oscillator are adjusted so that the output frequency and the selected frequency setting parameter are satisfied.

Abstract: Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-locked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency jitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual jitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.

Abstract: A phase-locked loop (PLL) frequency synthesizer is described that both reduces frequency channel spacing and accelerates convergence, and moreover, suppresses the occurrence of spurious noise. A frequency dividing circuit of the PLL frequency synthesizer is composed of a plurality of frequency dividers. By means of a timing generation circuit that is operated by frequency signals from an external oscillation circuit, each of frequency dividers are sequentially delayed by each cycle, and the output of these frequency dividers is taken as feedback signals of the phase comparator of the phase-locked loop.

Abstract: A PLL circuit includes a sampling pulse generator and a loop circuit using a sample and hold circuit as a phase detector. The sampling pulse generator generates a sampling pulse signal at each level transition of an NRZ input signal. The sample and hold circuit samples a clock signal and hold a voltage signal corresponding to a voltage of the clock signal according to the sampling pulse signal. A voltage-controlled oscillator included in the loop circuit generates the clock signal whose frequency is controlled based on tho voltage signal received from the sample and hold circuit through a loop filter. The voltage signal remains at an appropriate level even when the NRZ input signal remains at the same level for a relatively long time. The sampling pulse generator includes a delay circuit for delaying the NRZ input signal and an exclusive-OR circuit receiving the NRZ input signal and the delayed signal.

Abstract: A frequency synthesizer which uses a direct digital synthesizer (DDS) to generate a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. The DDS output signal is bandpass filtered utilizing a clean-up phase lock loop (PLL) to produce a spectrally pure reference signal and promote overall fast settling time. A second or primary phase lock loop, having a much faster settling time than the first PLL, adjusts the frequency of the reference signal generated by the clean-up PLL. In one embodiment, the DDS frequency synthesizer has a digital to analog (DAC) converter coupled to the clean-up PLL. Another embodiment uses a modified DDS (without a DAC or lookup table) and feeds the most significant bit (MSB) or overflow bit from the DAC accumulator into the "clean-up" PLL. In both embodiments, the resulting synthesizer has high spectral purity, fine frequency resolution and a fast settling time.

Abstract: According to the preferred embodiment of the present invention, a phase-locked loop is provided that overcomes the limitations of the prior art by facilitating fast locking on transition to a different output frequency. The phase-locked loop comprises an oscillator that provides a phase-locked loop output signal at various selected frequencies; a feedback divider; a phase comparator; a memory storage mechanism for storing phase-locked loop control information corresponding to selected output frequencies; and a digital circuit mechanism that receives the control information from the memory storage mechanism on transition to a different output frequency. The control information includes a digital counter value corresponding to the last recorded phase difference of the output signal at the different output frequency. On transition, this information is loaded directly to the digital circuit mechanism, reducing the need and time required for the phase comparator operation to drive the PLL to lock.

Abstract: A signal generator has a variable reference oscillator, a variable oscillator and a phase locked loop for generating an output having jitter and wander. The variable reference oscillator generates a reference having a varying phase offset over a first phase modulation frequency interval and a constant output over a second phase modulation frequency interval. The variable oscillator generates a constant output over the first phase modulation frequency interval and a variable output over the second phase modulation frequency interval. The phase locked loop includes a phase detector, a phase summing node and oscillator with the phase detector coupled to receive the outputs of the variable reference oscillator and the oscillator, and phase summing node coupled to receive the outputs of the variable oscillator and the phase detector.

Abstract: An automatic frequency control loop structure utilizes a dual selection automatic frequency control unit which is coupled to a differential phase unit and a coherent phase unit to provide a frequency corrected received signal output for efficient tracking of frequency offset drift; and a much lower probability of loss of automatic frequency control loop lock. Thus, a signal from a coherent carrier recovery process provides additional benefit by utilization in adjusting frequency offset tracking performance.

Abstract: Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-locked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency jitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual jitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.

Abstract: A voltage-controlled crystal oscillator circuit with an extended range is presented. The circuit has a crystal oscillator circuit, a phase-locked loop (PLL), and a look-up table. The crystal oscillator circuit generates a signal having a frequency f.sub.ref at its output node responsive to a voltage at its input terminal. The PLL has its input node connected to the crystal oscillator output node and generates a signal at the PLL output node having a frequency f.sub.o. A first divider circuit of the PLL divides the f.sub.ref frequency by a first variable integer M and a second PLL divider circuit divides the f.sub.o frequency by a second variable integer N. The look-up table, which has comparators connected to the input terminal, a counter connected to the comparators and a memory responsive to the counter and storing M and N values, varies M and N responsive to the input terminal voltage so that the voltage-controlled crystal oscillator circuit has an increased frequency range.

Abstract: The clock multiplying phase locked loop includes components for selectively setting a center frequency of a voltage controlled oscillator (VCO) to bias the VCO for operation within a selected range of input frequencies. To this end, the VCO is configured to output a signal at a selected center frequency based upon a tuning current provided to the VCO. Initially, a voltage input of the VCO is set to a reference voltage and a feedback signal is generated. The feedback signal, perhaps divided by N, is input to a phase-frequency detector. The phase-frequency detector also receives a reference frequency signal having a frequency at the selected center frequency. The detector outputs an UP or DOWN signal indicating whether the feedback signal is greater or less than the reference frequency signal.

Abstract: A phase locked loop includes a voltage controlled oscillator (VCO) for generating output VCO pulses. A frequency divider divides the VCO pulses by a variable number to produce frequency divided pulses whose phase is compared with that of input reference pulses by a phase detector. An update pulse is produced by the phase comparator having a pulsewidth corresponding to the detected phase difference. A pulse generator generates a train of update pulses having a combined pulsewidth equal to the pulsewidth of the update pulse, with the update pulses being substantially equally distributed within each period of the reference pulses to produce low output ripple. The update pulses are integrated by a loop filter to produce a D.C. control voltage that controls the VCO to vary the frequency of the VCO pulses such that the phase difference is adjusted toward zero. The frequency divider comprises a binary counter and a controller that enable the frequency divider to divide by a number N that is not a power of 2.

Abstract: A programmable phase shift clock generator is disclosed including a phase comparator, an up-down counter, a ring oscillator, and an adjustable delay line for determining a digital signature of an input clock and precisely generating a phase shifted clock signal.

Abstract: A drive voltage is supplied to a piezoelectric oscillator from an A.C. drive power source. Attached to an electrode of the piezoelectric oscillator is a loop circuit in which an amplifier having a (N+1) voltage amplification factor and an electrostatic capacitor are connected in series. When the electrostatic capacity is set to 1/N of a damping capacity of the piezoelectric oscillator, the current flowing through the damping capacity is replaced and shared by current from the electrostatic capacity, thus the drive current will not be consumed by the damping capacity. Therefore, a condition where the damping capacity is minimized depends on a capacity value of the electrostatic capacity and amplification factor of the amplifier only and does not depend on the frequency.

Abstract: A frequency synthesizer includes a phase adder, a read only memory, a D/A converter, a bandpass filter, a low-pass filter, a phase comparator, a loop filter, a voltage controlled oscillator, and a frequency divider. The phase adder adds frequency setting data and output data of a plurality of bits every input clock to set the addition result as new output data. The read only memory outputs sine wave data on the basis of the output data from the phase adder. The D/A converter D/A-converts the sine wave data from the read only memory. The bandpass filter (particularly a switched capacitor filter) receives an output from the D/A converter and has a pass frequency which changes in accordance with the reference frequency of an output sine wave signal. The low-pass filter removes a high-frequency component from an output from the bandpass filter. The phase comparator compares the phase of an output from the low-pass filter with the phase of a frequency-divided output of the sine wave signal.

Abstract: A clock recovery circuit comprises first and second voltage-controlled oscillators having identical characteristics. The first oscillator is incorporated into a frequency synthesis loop in such a way as to oscillate, in response to a first control voltage, at a frequency equal to a reference frequency multiplied by a number N. The second voltage-controlled oscillator is incorporated into a phase tracking loop which, when activated, locks its oscillation phase relative to that of the received data signal. The second oscillator delivers the recovered clock signal. A comparator determines whether the frequency of the second oscillator, divided by N, satisfies the condition of not deviating from the reference frequency by more than a predetermined limit value. The phase tracking loop is activated only when the latter condition is satisfied, and the first control voltage is fed to the control input of the second oscillator when the condition is not satisfied.

Abstract: A frequency oscillator and a frequency multiplier multiplying the signals from the oscillator contain inherent phase noise. A phase noise canceller removes phase noise, due to both the oscillator and the multiplier, by inserting a delay in one path and comparing phases of the delayed signal and the undelayed signal. This comparison may be either fed back to the tuning port of the oscillator or fed forward to a phase shifter which shakes off the phase noise. The delay may include a delay line, a cavity or any other suitable device which produces a phase shift. The phase noise canceller may also be designed to remove the total phase noise of the system, including additive phase noise from sources other than the oscillator and multiplier. The canceller may be calibrated and may be designed to reduce periodic response thereof.

Abstract: A hybrid frequency synthesizer combining a direct frequency synthesizer and a PLL synthesizer are disclosed. The direct frequency synthesizer includes a first and second phase accumulator, the second phase accumulator inputting K/N phase data and operating at M times faster than the first phase accumulator, a 360 degree detector adding the outputs of the first and second phase accumulators and detecting a point in time at which the added values become 360 degrees, which point in time is provided to the initialization circuit. The initialization circuit initializes the state of the first and second phase accumulators and controls the output timing of the first phase accumulator so as to synthesize the next period of the output frequency at the initialized time. Accordingly, the present invention simplifies the construction, and is economical.

Abstract: A frequency standard generator includes a voltage controlled crystal oscillator for generating high stability output signal to be used as a standard frequency signal, a satellite wave receiver which receives a radio wave from a satellite which includes a highly accurate satellite time signal and reproduces the satellite time signal to be used as a reference for the voltage controlled crystal oscillator, a frequency divider which divides the output signal of the voltage controlled crystal oscillator by a dividing ratio arranged to generate a crystal time signal which is identical in frequency to the satellite time signal, a time interval measuring circuit which measures a time interval which is a phase difference between the satellite time signal and the crystal time signal and generates a digital signal indicating the phase difference, a frequency control processor which arithmetically determines control data based on the digital signal from the time interval measuring circuit such that the phase difference m

Abstract: The invention relates to a transmission system comprising a phase-locked loop (12) which includes a phase comparator (15) for comparing an oscillator signal with a reference signal and for generating a comparison signal, and an oscillator which is provided for receiving a control signal derived from the comparison signal. The oscillator arranged as a ring oscillator (14) comprises at least one delay element (27 to 31) included in a closed circuit. At least one delay element (27 to 30) has at least two different adjustable delay times. A controller (19) is provided for setting the delay times of at least one delay element (27 to 30) in dependence on the comparison signal.

Abstract: A system and method for fast frequency locking are provided in which the phase difference between first and second synchronization signals is measured (22). The frequency difference between the two signals is then determined (24). The frequency of the second synchronization signal is then set to that of the first synchronization signal (26). Thereafter, the feedback loop of a phase-locked loop circuit is closed, with an error signal representative of the phase difference between the first and second synchronization signals being offset by an amount equal to an error signal generated when the frequency of the second synchronization signal is set to that of the first synchronization signal.

Abstract: A phase-locked loop (PLL) circuit which receives a signal at a reference frequency to generate a spread spectrum clock signal. A first divider circuit in the PLL and connected to the PLL input terminal generates an output signal at the reference frequency divided by a first variable integer M. A second divider circuit connected to the PLL output terminal generating an output signal at the output frequency divided by a second variable integer N. The PLL also has a circuit which periodically varies the first variable integer M and the second variable integer N. This permits the frequency of the output signal to vary precisely between two predetermined frequencies to spread the spectrum of output frequencies.

Abstract: An instrument is provided for measuring the temperature of an object from infrared radiation emitted by the object. The instrument includes a radiation detector, a temperature indicating device connected to the detector, and a modulator disposed in a path of a radiation beam from the object for converting the beam into a series of pulses when the modulator is vibrated in and out of the path. The modulator includes a primary piezoelectric element adapted to vibrate when subjected to driving signals at a frequency related to the resonant frequency of the modulator, and a secondary piezoelectric element connected with and driven by the primary piezoelectric element. The secondary piezoelectric element is electrically insulated from the primary piezoelectric element. The modulator also includes a blocking element connected with the secondary piezoelectric element and disposed to move in and out of the path of the beam.

Abstract: Each of primary and secondary random-walk filters has longer and shorter time constants. A multi-valued phase comparator generates a start signal if a phase error generated when an abrupt frequency change occurs exceeds a given value. In response to the start signal, the primary and secondary random-walk filters are set to the shorter time constants. A timer is started by the start signal, and upon elapse of a predetermined period of time, sets the primary and secondary random-walk filters to the longer time constants.

Abstract: A frequency synthesizer (200) with temperature compensation and frequently multiplication. The synthesizer (200) having a temperature uncompensated frequency oscillator (202) coupled to a phase locked loop (206) including at least one temperature compensating and frequency multiplication element (208). The element (208) preferably being a multi-modulus divider. The element (208) is programmed by a control circuit (210) to vary as a function of temperature and to vary as a function of a fractional frequency multiplication factor. The element (208) also may provide adjustment of the nominal frequency of the frequency oscillator (202). The frequency oscillator (202) and preferably all the elements of the synthesizer (200) are temperature compensated by the element (208) to produce a temperature stable multiplied output frequency (238).

Abstract: A processor (PR) is connected to the output of a phase comparator (PK) in a phase-locked loop. The processor (PR) calculates the phase shift of an input signal (f.sub.E) within an observation time span (for example, .DELTA.t=0-T) from the phase difference (.DELTA..phi.) at the output of the phase comparator (PK) and the parameters of the phase-locked loop (FT1, PK, FI, VCO, FT2).

Abstract: A clock signal generation circuit performs a stable operation with respect to both a high frequency input clock signal and a sufficient low frequency testing clock signal.

Abstract: A method and a device for changing the phase of a generated signal by a predetermined value in a device for frequency generation. In the device for frequency generation, the generated signal is phase-locked to a reference signal where non-integer multiples of the frequency of the generated signal may be phase-locked to the reference signal by changing the phase of each of the periods of the reference signal by a value which determines the frequency of the generated signal. The phase is changed by a phase-shifter. The change of the phase of the generated signal is made by controlling the phase-shifter so that no change of the phase of the reference signal is made during at least one period of the reference signal.

Abstract: A frequency synthesizer circuit for the front end of an RF system. The frequency synthesizer uses two pulse-swallow phase-locked loops in a synthesizer architecture that produces an output frequency that is a function of the two reference frequencies used as inputs into the two phase-locked loops. As a result, the frequency synthesizer can be incremented in steps equal to the differential of the reference frequencies of the two phase-locked loops, while the frequency outputs of each of the phase-locked loops can be incremented in much larger steps. This enables the two phase-locked loops to employ relatively large bandwidths, thereby achieving a faster signal lock as well as a better suppression of the voltage controlled oscillator (VCO) phase noise in each loop. The use of a dual loop synthesizer architecture allows for feedback correction of the VCO phase noise outside the loop bandwidth.

Abstract: In order to program the output frequency of a synthesizer such as that of a two-way radio, first the reference oscillator is warped or tuned substantially to one limit of its tuning range. The "N" divisor of the synthesizer dividor is then selected to produce a loop output close to the desired loop output frequency. The reference oscillator is then tuned to provide the desired loop output frequency.

Abstract: A single reliable clock source that can be shared by all cards in a multiple card assembly. The clock delivers synchronous clock signals, so that there is no longer a need to provide crystal oscillators on each card, instead, a single non-interruptable clock source is shared by all cards. The clock is an Application Specific Integrated Circuit (ASIC), where single sources of failure have been removed by using redundant connection and majority logic. Thus, a plurality of selection means are redundantly coupled to receivers for selecting an oscillator signal to provide to phase-locked oscillators. Further, majority logic voters are redundantly coupled to the phase-locked oscillator to provide a clock output signal reflecting the state of the majority of the phase-locked oscillator signals. The clock includes three independent crystal oscillators, one clock ASIC, the wire and connectors which deliver the signals, and a 2.times.3 AND-OR majority logic on the receiving card.

Abstract: A clock distribution network for synchronously coupled electronic communication systems that includes a clock distribution device having a phase locked loop for synchronizing the external clock signals provided to each semiconductive device with each other. The clock distribution device distributes a low speed clock to a large number of clocked semiconductor devices where those devices then internally generate high speed clocks in phase with the low speed clock. The low speed clocks are phase shifted with respect to each other to reduce radiated energy. The ratio of internal to external clock speed is also communicated to each chip so that the chips can be programmed to operate with a variety of external clock speeds. The phase shifting of the external clock to different chips is provided so that the chips can still communicate synchronously at the high speed internal clock.