Abstract: A transceiver (10) includes a dual port phase and magnitude balanced synthesizer modulator (60). The modulator (60) couples a modulation input to a voltage controlled oscillator (40) and to a reference oscillator (42) that are coupled together in a phase locked loop (44). The modulator 60 includes a magnitude balancing circuit (64) that divides a modulation input representing data or the like into a first modulation input signal applied to the reference oscillator (42) and a second modulation input signal for the voltage controlled oscillator (40). A phase balancing circuit (68) induces a negative phase shift in the second modulation input signal that is coupled to the voltage controlled oscillator (40) in order to compensate for the phase lag of the reference oscillator loop (44).

Abstract: A method for automatically compensating for accuracy degradation of the reference oscillator (170) is provided for a communication device (100). The communication device (100) is programmed with a first frequency value to detect a target carrier signal (310), and is reprogrammed with a second frequency value that is offset from the first frequency value by a particular offset factor, when the target carrier signal is not detected (320, 410). An available carrier signal is subsequently detected and its relative location information determined (420, 430, 440). The communication device is automatically adjusted to detect the target carrier signal using information derived from the relative location information and the particular offset factor (450, 460, 470, 480).

Abstract: A method and apparatus determine an instantaneous phase difference (207) between a reference signal (103) and a controlled signal (120). The reference signal (103) is derived by frequency dividing a first signal by a counter (106) including an output (107) having K sequential states, wherein K is an integer value equal to the frequency of the first signal (103) divided by the frequency of the desired reference signal, and wherein the output (107) changes by no more than one bit between any adjacent states of the K sequential states. The output (107) of the counter (106) is recorded (206) at a time concurrent with a first predetermined event occurring in the controlled signal (120), thereby generating a recorded count value that is free from metastability induced errors. The recorded count value is decoded (208) to produce a sequential state number S.sub.E corresponding to the first predetermined event. The instantaneous phase difference (207) is then calculated (210) from S.sub.

Abstract: A phase-locked loop wherein the output signal is effectively sampled at an increased rate from conventional phase-locked loops, allowing for a greater increase in the ratio of the output frequency to the input frequency while reducing the possibility of jitter or failure to lock. Multiple differently phased reference signals and correspondingly phased feedback signals are produced. The comparison of the feedback signals and the reference signals produce multiple error signals which are combined to adjust the oscillation frequency of the voltage-controlled oscillator.

Abstract: A phase comparator, a loop filter and a VCO compose a PLL. In the phase comparator, a CMI code defined by a CMI data is synchronized with a VCO clock generated in the VCO and an inverted clock of the VCO clock, respectively, to provide first and second synchronized CMI codes. The first synchronized CMI code is delayed to provide a delayed CMI code by a predetermined time dependent on a period of the VCO clock. The first and second synchronized CMI codes are subject to an exclusive OR logic calculation, thereby generating a phase difference signal. The delayed CMI code and the first synchronized CMI code are subject to an exclusive OR logic calculation, and a result of this exclusive OR logic calculation and the VCO clock are subject to an AND logic calculation to provide an enable signal. Only when the enable signal is high, the phase difference signal is sampled to be used as a phase difference signal in the PLL.

Abstract: A frequency synthesizer includes a voltage-controlled oscillator, frequency dividing circuits, a signal source, phase comparing circuits, an adding circuit, a converting circuit and a control circuit. The frequency dividing circuits divide an output supplied thereto from the voltage-controlled oscillator with frequency-dividing ratios of 1/N and 1/(N+1) where N is an arbitrary integer. The signal source outputs a reference frequency signal. The phase comparing circuits phase-compare a signal divided by N supplied thereto from one frequency dividing circuit and a signal divided by (N+1) supplied thereto from another frequency dividing circuit and the reference frequency signal from the signal source.

Abstract: The PLL circuit provides both the advantages of analog phase control, in which a good C/N ratio can be realized, and the advantages of digital phase control, in which broad-band lock can be performed. A multi-channel FM receiving method and apparatus are able to utilize the PLL circuit to reduce the influence of the leakage occurring among input signals and suppress image disturbance.

Abstract: A frequency synthesizer with very short acquisition times. With a single loop there is associated a direct digital synthesizer whose signal is injected into the loop by means of a mixer. The adjustment of the loop is done on Np.Fr and the adjustment of the digital synthesis is done on (Ns+)Fr with Np, Ns, K and M as integers, Np being greater than Ns, 0.ltoreq.K<M, M as a fixed value and where Fr is a reference frequency. The mixture makes it possible to obtain, as a synthesis frequency, (Ns+Np+)Fr. The acquisition time of the digital synthesis is negligible and that of the loop is greatly reduced since it synthesizes steps that are multiples of Fr and not of as with a standard single loop.

Abstract: An apparatus (500) for generating first and second output signals having predetermined frequency shifts relative to a frequency provided by a reference signal is included in a system comprising a phase-locked loop (206) coupled to the reference signal for generating the first and second output signals. The apparatus (500) includes pulse deletion circuitry (204) coupled to the reference signal and the phase-locked loop (206) for deleting pulses from the reference signal at a first deletion rate to generate the first output signal and for deleting pulses from the reference signal at a second deletion rate to generate the second output signal.

Abstract: An oscillator capable of setting a desired frequency by using only two resonators without setting up any additional adjustment processes, and a synthesizer tuner circuit with an AM synchronous detect circuit.

Abstract: A phase-lock loop (FIG. 1) is initialized at power-up by an oscillator (14) control signal (28) that has previously been stored by a processor (20) in a non-volatile memory (27). The stored control signal is generated by the phase-lock loop's controller (12) in response to receipt of a calibrated reference input signal, as part of manufacturing of the phase-lock loop and occasionally thereafter during normal operation. Being stored in non-volatile memory, the control signal is not lost upon removal of power from the phase-lock loop. The stored control signal is then used to control the oscillator instead of the controller's output upon power-up and until the later one of (a) receipt by the phase-lock loop of a valid reference signal and (b) receipt of a directive for the controller to take over control of the oscillator.

Abstract: For digital transitions from one binary logic level to another by frequency or phase shift of an electric carrier wave the modulation sidebands are reduced by performing each transition by means of several phase steps at small intervals. Equal phase steps at varying intervals are preferred over equal intervals between varying phase steps although both procedures can provide a low-bandwidth transition. This procedure is readily incorporated at low cost in frequency synthesizers. The use of a higher-frequency master oscillator (16) followed by a fixed-ratio frequency divider (17) ahead of a variable-ratio frequency divider (18) makes it easy to shift phase or frequency digitally by small quick steps. Another variable-ratio frequency divider (13) is desirable but not essential in the final PLL between a ultimately controlled oscillator (10) and a loop filter (12) connected to a phase discriminator (11).

Abstract: A programmable crystal oscillator that generates a wide range of possible frequencies with high stability is disclosed. The programmable crystal clock oscillator includes an industry standard oscillator package, a programmable storage, a crystal and a phase lock loop (PLL) circuit coupled to the crystal and the programmable storage. The industry standard package does not contain any dedicated programming connections. A programmable storage, contained within the package, stores parameters representing a desired output frequency for the crystal oscillator. The crystal is enclosed within the package and provides a source frequency. The PLL circuit, also enclosed in the package, receives the source frequency, and produces the desired output frequency, within the wide range of possible frequencies, based on the parameters.

Abstract: A frequency synthesizer which comprises a voltage controlled oscillator; a unit for outputting a value corresponding to a differential phase of a reference signal at a predetermined frequency as a first differential phase; a unit for sampling an oscillating signal corresponding to an output of the voltage controlled oscillator K times per period of a repeating frequency f.sub.r (f.sub.

Abstract: A phase-locked-loop (PLL) with stable phase discrimination includes a charge pump with a current source and current sink to control a VCO, and a phase discriminator to compare the VCO's signal to a stable reference signal for controlling the charge pump. The phase discriminator includes a resettable D-flipflop to provide the current source control signal and a resettable D-flipflop to provide the current sink control signal. The reset signal keeps both sink and source temporarily alive to avoid a dead zone region. The reset signal is produced under the combined control of the sink and source control signals and, in addition, of the reference signal to enhance stability.

Abstract: A direct digital synthesizer which can be switched at a high speed and generates signals having a relatively high frequency with low power consumption; including a clock generator, a frequency setting circuit in which phase increment for unit clock can be programmed, a phase accumulator in which phase increment is accumulated, a ROM which outputs a digital signal corresponding to cumulative phase output, a D/A convertor which inverts polarity of output in each clock time, and a band-pass filter. The output of the band pass filter may be used as a reference input to a phase locked loop.

Abstract: According to an output from a voltage-controlled oscillator, there are generated by a fractional divider a high-frequency division signal and a low-frequency division number. A phase comparison is conducted between the high-frequency division signal and a high-frequency reference signal by a phase comparator. A phase comparison is carried out between the low-frequency division signal and a low-frequency reference signal by a phase comparator. Either one of the outputs from the phase comparators is selected by a selector to be fed to a filter, thereby producing a control voltage for the voltage-controlled oscillator. A high-resolution division is achieved by the fractional division; consequently, disturbance of the oscillation frequency due to a change-over of the selector is suppressed. There is obtained a PLL frequency synthesizer developing a high-speed lock-up and a highly stable oscillation.

Abstract: A phase lock loop (PLL) circuit for controlling an oscillator includes a phase comparator, a loop filter, a reference converter and a feedback converter whose performance characteristics are dynamically controlled so as to provide a phase-locked output signal with both high frequency stepping resolution and low phase locking time. The phase comparator compares the relative phases of the reference and feedback signals, and outputs a phase difference signal representing such phase comparison. The loop filter, in accordance with a filter bandwidth dynamically selected by a filter control signal, filters the phase difference signal to provide a frequency control signal for a voltage controlled oscillator (VCO). The reference converter is a programmable frequency divider which, in accordance with a reference proportionality factor dynamically selected by a reference control signal, reduces the frequency of the PLL reference signal frequency used by the phase comparator.

Abstract: A phase lock loop circuit (PLL) is manufactured as a part of each very large scale integrated circuit (VLSI) that might need clock pulses. When these VLSI chips are mounted on a printed circuit board (PC), three crystal oscillators are also mounted on the PC in order to provide redundancy. In order to identify crystal oscillators that are less desirable from the standpoint of operation and accuracy, a circuit is mounted on the PC for comparing oscillator frequencies and detecting when lack of frequency agreement is noted. A gating circuit receives the output of the detecting circuit for selecting and passing clock pulses only from a properly functioning crystal oscillator to the rest of the PC. Programmable counters are provided in the PLLs to allow local generation within each VLSI of clock pulses at a frequency that is a ratio of the frequency of the crystal-generated clock pulses that are circulated throughout the PC.

Abstract: A low phase noise third order phase lock loop which can track and eliminate microphonic disturbances and phase hits. The PLL utilizes a third order loop filter which incorporates two integrators. These two integrators, when coupled with the integration which occurs at the voltage control input of the voltage controlled oscillator within the PLL yield an open loop transfer function with a --18 dB/octave rolloff over a band of frequencies which at least encompasses the spectral content of the microphonic or phase hit phase noise disturbance to be eliminated. The open loop gain of the phase lock loop must be set high enough such that the phase lock loop does not oscillate and such that the loop converges and locks. The integrators are implemented with operational amplifiers with RC feedback networks. The values of the components in the RC feedback networks set the frequencies of two zeroes in the transfer function.

Abstract: A synthesizer for use in a transmitter/receiver effectively eliminates spurious signals contained in an output signal. The synthesizer has a direct digital synthesizer for producing an output signal having a frequency corresponding to oscillation frequency data, and a voltage-controlled variable bandpass filter to which the output signal from the direct digital synthesizer is supplied. The oscillation frequency data is also supplied to a ROM, from which control voltage data corresponding to the supplied oscillation frequency data is read. The control voltage data from the ROM is supplied to a D/A converter which applies a control voltage to the voltage-controlled variable bandpass filter. The center frequency of the passband of the voltage-controlled variable bandpass filter is controlled by the applied control voltage in conformity with the frequency of the output signal from the direct digital synthesizer.

Abstract: A high speed clock recovery system that provides a precise 90.degree. phase shift at the incoming NRZ data rate by using a series of differential inverters and controlling their delays in accordance with the corresponding delays of differential inverters of a ring oscillator that is part of a phase-locked loop. More particularly, the incoming NRZ data and the phase shifted data are fed to an exclusive OR that provides an output signal including a frequency component of the originating clock of the NRZ data. The phase-locked loop further includes a phase detector which is responsive to the output of the exclusive OR and the ring oscillator. Thus, once the loop locks, the ring oscillator is synchronized to the frequency of the originating clock for the NRZ data. By slaving the differential inverters of the phase shifter and the ring oscillator to the same delays, the phase shifter provides a dynamically adjusted delay of precisely 90.degree. at the originating clock frequency of the incoming NRZ data.

Abstract: A radio apparatus with a phase locked loop is disclosed. The apparatus contains a phase detector with first and second inputs, where the first input receiving a reference frequency signal and the second input receives a controllable frequency signal that is controlled by a tuning voltage. Also included is, a loop filter for filtering the output of the phase detector, circuitry for decoding when a phase difference at the inputs of the phase detector exceeds a predetermined value, and a filter bypass circuit. This circuit bypasses operation of the loop filter when the difference at the inputs of the phase detector exceeds a predetermined value, allowing fast voltage changes of the tuning voltage, and providing a short lock time for the phase locked loop.

Abstract: A method and apparatus for controlling the phase of a system clock, in which one of a first clock signal and a second clock signal is selected and output to a system as a system clock signal, the first clock signal being generated by a frequency synthesizer synchronized with an external clock signal supplied from a reference clock signal oscillator provided externally of the system, and the second clock signal being supplied from another reference clock signal oscillator provided internally of the system, and the phases of the first and second clock signals are controlled, prior to switching between the first and second clock signals and supplying the switched clock signal to the system as the system clock signal. The switching is delayed for a period while there is a phase shift between the first and second clock signal , when the system clock signal is switched between the first and second clock signal.

Abstract: A phase locked loop frequency synthesizer in which the output frequency is changed in a series of steps in order to reach a final frequency value. The steps are computed and stored in a memory in a control unit. The steps are chosen to approximately cancel the poles of the transfer function of the synthesizer. The phase locked loop provides increased switching speed.

Abstract: A phase locked loop PLL circuitry for use in a radio pager. A power source applies a voltage to a charge pump circuit. A power supply control circuit controls the application of the voltage.

Abstract: A PLL has at least two attenuators supplying output signals, and a phase detector comparing the output signals of the at least two attenuators. The phase detector has an input and an output stage supplying an output variable being dependent on a phase difference at the input to the phase detector and being influenceable by a further electrical variable. A change in the attenuator ratios of the at least two attenuators takes place synchronously with the existing phase difference. A method for adjusting PLL parameters in the PLL includes synchronously varying the further variable determining the output variable of the phase detector, upon a change in the attenuator ratios.

Abstract: A frequency synthesizer is composed of a reference oscillator, the first and the second integrators, a binary adder, a low pass filter and VCO forming a Phase Locked Loop (PLL). The first integrator, driven by the timing of a reference oscillator, integrates an externally supplied value K and generates the input signal. The second integrator, driven by the output signal of the VCO of the PLL, integrates an externally supplied value L. The binary adder detects the difference between the outputs of the first and the second integrators functioning as a phase comparator. The output of the phase comparator is converted into an analog voltage which is filtered to control the VCO to achieve frequency synthesis by the phase lock function of the loop.

Abstract: The circuit arrangement of the invention presents an oscillator, whose frequency can be linearly varied within a wide control range, without affecting the oscillator's stability. The frequency of a fixed frequency generator (1) is divided to the desired frequency by a frequency divider (2), whose divider ratio can be varied in very small steps, and the resulting jitter is filtered out by a very simple phase control circuit (3). Improved short-term stability and holdover performance are also achieved. The oscillator can be universally used as clock generator in all digital circuit arrangements.

Abstract: A phase locked loop includes a linear phase detector responsive to a first signal having a predetermined range of frequencies and a second signal for comparing the relative phase of the first signal and the second signal, and a loop gain stabilization circuit coupled between the source of the first signal and the linear phase detector for reducing the magnitude of variations in the loop gain of the phase locked loop over the predetermined range of frequencies of the first signal source. An embodiment of the linear phase detector comprises a harmonic sampler/presteer circuit. The construction and operation of the loop gain stabilization circuit depends on whether the phase locked loop is being used in a frequency multiplying or dividing circuit.

Abstract: A one-shot control mechanism for ensuring close tracking of one-shot period to VCO period. The one-shot control mechanism provides immunity to data jitter and other spurious phenomena as well as stable and accurate tracking of one-shot period even when the VCO frequency varies from the center frequency of the VCO. The present invention includes a data capture PLL circuit and a frequency reference PLL circuit. The frequency reference PLL circuit provides a control signal to one or more one-shots to control their output pulse duration. Since the frequency reference PLL circuit operates at the expected frequency of data input, a relatively constant relationship may be maintained between the output pulse duration of the one-shots and the period of the VCO output.

Abstract: A frequency synthesizer having a comb frequency generator, comb line selection filter, and phase locked loop for filtering out spurious signal components and for offsetting the synthesizer output frequency from the frequency of a signal which is output by the comb line selection filter. A reference signal source generates a reference signal having a reference frequency and outputs the reference signal to the comb frequency generator. The comb frequency generator outputs a plurality of comb spectrum signals having frequencies which are respective integer multiples of the reference frequency. An input mixer connected to the comb frequency generator and to a coarse tuning signal source translates the frequencies of the comb spectrum signals to place one selected signal of the comb spectrum signals within a pass band of the comb line selection filter, which outputs the selected signal to the phase locked loop.

Abstract: A data transmitter (100) operating at a transmit frequency provides a modulated data signal (114) by adjusting a reference frequency signal (108). The method of modulating an N-level data signal (102) inputted to the transmitter (100) provides for inputting, to a signal processor (201), a frequency deviation value. Using the frequency deviation value, the signal processor (201) then determines a maximum rate of enabling the frequency adjustment. Further, a deviation ratio corresponding to one of the N-levels is determined, and an increment value is then calculated (302) using this deviation ratio. Lastly, the frequency adjustment is enabled (312, 320) using the calculated increment value.

Abstract: An embodiment of the present invention is a single-chip GPS receiver front-end comprising a radio frequency amplifier, a voltage-controlled oscillator operating at a first local oscillator frequency, a divide by seven and one-half counter for deriving a second local oscillator frequency from the first and a first and second mixer. The local oscillator frequency is mid-way between two carrier frequencies of interest that may be received by the radio frequency amplifier and the first mixer produces a first intermediate frequency. The second local oscillator frequency is then beat with the first intermediate frequency in the second mixer to produce a second intermediate frequency. A dual-conversion super heterodyne configuration is therefore employed in which the first and second local oscillator frequencies are derived from a single oscillator and the first local oscillator frequency is seven and one-half times the second local oscillator frequency.

Abstract: A circuit for producing an output signal representative of the phase angle of a single phase input signal includes a phase shift generator for receiving a single phase input signal and for generating a quadrature signal and a direct signal in response to the single phase input signal, and a phase locked loop coupled to the phase shift generator for generating an output signal in response to the quadrature and direct signals such that the output signal is phase locked with the single phase input signal. A method is also provided for producing an output signal representative of the phase angle of a single phase input signal, comprising the steps of: receiving a single phase input signal; generating a quadrature signal and a direct signal in response to the single phase input signal; and generating an output signal in response to the direct and quadrature signals, such that the output signal is phase locked with the single phase input signal.

Abstract: A phase lock loop monitors the frequency of redundant input clock signals and switches back and forth therebetween should one or the other become invalid. Thus, the PLL may continue normal operation even with a failure of one input clock signal. If both the input clock signals fail, an internal reference signal maintains the PLL at a nominal operating frequency until one of the input clock signals is restored whereby the loop can quickly re-establish phase lock. To determined validity, the input clock signals are sampled and stored by the reference signal in a predetermined manner. The input clock signal is valid if the samples of the input clock signal each have the same logic state after the sampling period; otherwise, the input clock signal is invalid if the samples of the input clock signal have at least one different logic state after the sampling period.

Abstract: The digital sample and hold phase detector to compare the phase relationship between input pulses and a high frequency reference clock comprises a digital counter arrangement coupled to count the high frequency reference clock to produce a digital ramp signal and a digital sampling arrangement coupled to at least the input pulses and an output of the counter arrangement to enable the input pulses to sample the digital ramp signal and produce a digital phase difference signal.

Abstract: A signal generator having a switching function includes a first oscillation circuit, a second oscillation circuit, a frequency-division circuit and a combination circuit. The first oscillation circuit outputs a first frequency signal having a first frequency and a reset signal synchronized with the first frequency signal. The second oscillation circuit outputs a second frequency signal having a second frequency which is N times higher than the first frequency. The frequency-division circuit frequency-divides the second frequency signal by N, resets a value for frequency-division based on the reset signal and generates a divided second frequency signal. The combination circuit combines the first frequency signal and the divided second frequency signal and outputs a combined signal.

Abstract: Certain operational characteristics of a crystal (104) are measured during a testing and grading process. Once determined, information representing these operational characteristics are stored in memory (120) and utilized by a controller (122) to increment a phase increment register (114) upon determining the crystals ambient temperature via a temperature sensing circuit (124). The value stored in the phase increment register (114) is then sent to a phase accumulator (116) where successive phase increments are summed together. This summed value is in turn sent to a sine lookup table (118) where the instantaneous phase value is converted into sine amplitude. Finally, a digital to analog converter (126) converts the amplitude bit stream into an analog signal for use as a reference oscillator frequency having extremely high frequency resolution.

Abstract: A phase lock loop for a sector servo system. A servo phase lock loop oscillator provides the control timing function of the servo. Initially, the PLO is locked in frequency to a frequency reference obtained from a counter/timer in a digital signal processor (DSP) used to control the servo system. Subsequent to acquisition of the nominal operation frequency, the PLO is caused to lock in turn to gap and frame character markers derived from the digital information encoded into the servo burst. Transition between PLO reference sources is commanded by the microprogram running in the DSP, based upon microprogram assessment of servo PLO status. The PLO outputs timing control tags to the servo control logic and PES demodulator, a reference clock to the file read/write channel, and interrupt pulses to the DSP to synchronize DSP operation with the servo hardware, and initiate periodic DSP computation of the control algorithm.

Abstract: An analog switch is provided in a phase-locked loop (PLL) synthesizer using direct digital synthesizer (DDS) circuitry, for opening a PLL. The PLL is closed to make operative the DDS circuitry and a fixed frequency divider within an idle time slot of each time-division multiplexing (TDM) frame. For the rest of the frame, the voltage-controlled oscillator within the PLL is held in a "hold state".

Abstract: A frequency source (1) in, for example, a remote unit in a mobile communications system, is controlled to maintain a stable frequency signal. In normal operation, the frequency source (1) is frequency locked to an external reference frequency (10). A temperature detecting device (2) monitors the temperature of the frequency source, and information relating to temperature is stored in a storage device (7) together with information relating to control signals (6) applied to the frequency source (1). In the absence of the reference frequency (10), the temperature of the frequency source (1) is detected and the stored information is used to generate a control signal (6) to control the output frequency of the frequency source (1) in accordance with the detected temperature.

Abstract: A PLL synthesizer circuit includes a lowpass filter including capacitors for restricting an output voltage of the lowpass filter, a charge pump circuit for controlling the output voltage of the lowpass filter by charging or discharging the capacitors of the lowpass filter, a voltage controlled oscillator for outputting an output signal having a frequency which is controlled by the output voltage of the lowpass filter, a frequency divider for frequency-dividing the output signal of the voltage controlled oscillator to output a comparison signal and having a variable frequency dividing ratio, a phase comparator for comparing a phase of a reference signal having a predetermined frequency and a phase of the comparison signal output from the frequency divider to output phase error information which indicates a phase lead and a phase lag of the comparison signal with respect to the reference signal, and a charge pump control circuit for forming control information based on the phase error information when switching

Abstract: A method to speed up the training of the output frequency signal (Out) of a frequency synthesizer circuit. The circuit comprises a voltage controlled oscillator (7) controlled by a filtered (6) feedback signal (Fb) output by a phase detector circuit (5) having a first input signal (Rs), which is produced by a reference counter (3) dividing an external reference signal produced by a reference oscillator (2), and a second input signal (Cs) produced by a programmable counter (4) dividing an output signal (Vs) from the voltage controlled oscillator (7). When the training process is started, the internal reference frequency of the first and second input signals (Rs, Cs) is simultaneously increased by a predetermined amount for a predetermined time.

Abstract: A phase detector for a phase locked loop frequency synthesizer, in which frequency-divided signals from a variable frequency oscillator and a reference oscillator are used to trigger respective ramp waveform generators, and a sample pulse generator is arranged to be responsive to the reference ramp waveform to provide sample pulses centered at the mid-point of that ramp waveform to respective sample and hold circuits, the relative phases of the ramp waveforms being determined from the sampled and held voltages.

Abstract: A clock generator (30) dynamically generates a system clock in response to a high or a low frequency oscillator. An amplified oscillator input is provided to a first input of a multiplexor (62), a divider (56), and a comparator circuit (58, 60). Divider (56) divides an oscillator input frequency to provide a divided input to a second input of multiplexor (62). Comparator circuit (58,60) compares the input frequency with a reference frequency to determine whether the input frequency is high or low. If the input frequency is low, multiplexor (62) is enabled to provide the oscillator input as the system clock. If the input frequency is high, multiplexor (62) provides the divided input as the system clock. Additionally, comparator circuit (58,60) provides a control signal to enable an amplifier (50) to amplify the oscillator input using a high or low gain factor in accordance with the input frequency.

Abstract: A frequency synthesizer is described which operates over a wide frequency range at high resolution and variable step size without trading off between spurious frequency rejection and phase noise suppression. The synthesizer includes a magnetically-turned YIG oscillator which generates a desired output frequency from a received tuning signal. The output signal is fed back into a phase locked loop which generates the tuning signal. The phase locked loop includes a harmonic mixer for mixing the output signal with a reference frequency F.sub.2. The mixer receives a base frequency signal and a harmonic select signal resulting in the generation of the reference signal, F.sub.2. The mixed signal is input to a programmable divider, then to a phase detector which receives another reference signal, F.sub.1. The phase detector output is the tuning signal which is coupled to the YIG oscillator. Both reference frequencies, F.sub.1 and F.sub.2, are derived from a common base frequency.

Abstract: A phase locked loop utilizing digital techniques to control the closed loop bandwidth of the RF carrier phase locked loop in a receiver provides high sensitivity and a wide dynamic range for signal reception. After analog to digital conversion, a digital phase locked loop bandwidth controller provides phase error detection with automatic RF carrier closed loop tracking bandwidth control to accommodate several modes of transmission.

Abstract: A phase lock loop (PLL) reduces output phase jitter by averaging an input clock signal and a delayed input clock signal. A control signal selects between the input clock signal and the delayed input clock signal for providing a reference clock signal for the phase lock loop. The output oscillator signal of the PLL is divided by a predetermined integer value for providing the control signal to select between the input clock signal and the delayed input clock signal. The PLL establishes phase lock to the input clock signal during a first state of the control signal. The PLL next establishes phase lock to the delayed input clock signal during a second state of the control signal such that the average value of the output clock signal of the PLL is substantially constant.

Abstract: A SAW stabilized oscillator includes a phase locking circuit which is phase locked to a lower frequency reference signal having an odd order difference with respect to the fundamental frequency of the SAW oscillator. A mixer is disposed in the phase locking circuitry and is used as a sub-harmonic phase detector by mixing the fundamental with an odd harmonic of the reference signal.