Abstract: The invention relates to a method for adjusting an oscillator (44), a packet switched network (21) locating between the oscillator and a specified time source (31), which knows a clock time with a specified accuracy. In the method, a clock (42), which is on the same side of the packet switched network (21) as the adjustable oscillator (44), is updated over the packet switched network (21) on the basis of the clock time known to said time source (31). Said clock (42) is used in the adjustment of the oscillator (44) for making the oscillator (44) to oscillate at a desired frequency. The invention also relates to an apparatus and computer software for adjusting the oscillator.

Abstract: A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. Additional parameters are used to program the output frequency of a phase locked loop circuit coupled to receive the adjusted source frequency. A further parameter can also be used to divide the output frequency of the phase locked loop circuit to supply a specified output frequency. The oscillators can be manufactured as generic programmable crystal oscillators without regard for output frequency and then quickly programmed to produce customer-specified output frequencies with a high degree of accuracy.

Abstract: Methods and systems are disclosed for eliminating a phase transient of a controlled frequency oscillator. caused by replacing a first reference signal by a second reference signal when the first reference signal becomes corrupted or otherwise unavailable, and for running a controlled frequency oscillator in a frequency-controlled holdover mode. The contradictory requirements of using a relatively low-cost controlled frequency oscillator tunable over a relatively wide frequency range and achieving high stability of its frequency in holdover mode are satisfied.

Abstract: A method and apparatus for timing recovery in modem receivers. The timing recovery circuit includes a voltage controlled oscillator for controlling the voltage controlled sampling frequency of an analog-to-digital converter. The oscillator generates a timing clock that is dependent on an average phase error signal calculated from Nyquist signals of the input signal. A phase detector circuit is used for generating an instantaneous phase error signal of the in-phase and quadrature-phase signals. A digital loop filter receives the instantaneous phase error signal over time to generate the average phase error signal. The average phase error signal is conditioned further (after conversion to analog) by an analog loop filter such that the average phase error signal adjusts the timing clock generated by the oscillator. The low pass filter provides control of the acquisition and steady state operations by changing the gain and pole parameters of the filter.

Abstract: A signal generator and a method of generating a signal are disclosed that offsets phase and frequency of the output signal relative to the input signal by small increments, providing high resolution. The signal generator utilizes numerically controlled oscillators to instantly and independently offset phase and/or frequency.

Abstract: Methods and systems are disclosed for eliminating a phase transient of a controlled frequency oscillator caused by replacing a first reference signal by a second reference signal when the first reference signal becomes corrupted or otherwise unavailable, and for running a controlled frequency oscillator in a frequency-controlled holdover mode. The contradictory requirements of using a relatively low-cost controlled frequency oscillator tunable over a relatively wide frequency range and achieving high stability of its frequency in holdover mode are satisfied.

Abstract: An extended play radio video cassette recorder (EPRVCR) capable of receiving and recording audio and video signals transmitted over a radio frequency channel is provided. The EPRVCR includes a videocassette recorder (VCR) and a tuner capable of receiving of radio frequency signals and television frequency signals electrically connected to the VCR. Method for broadcasting and receiving a composite video and audio signal over a radio frequency for subsequent recording by an extended play radio video cassette recorder is also provided. The method includes the steps of providing a VCR having a tuner capable of receiving radio frequency signals; broadcasting audio on a preselected baseband radio frequency; broadcasting a visual image on a subcarrier sideband of the preselected baseband frequency; and receiving the audio and visual image using the tuner of the VCR. The VCR is also capable of recording the audio and video image simultaneously onto a single video cassette.

Abstract: A frequency synthesizer using a multiphase reference signal source consists of three portions: a basic phase locked loop including a variable frequency oscillator, a loop filter, a phase detector, and a frequency divider; a generating circuit including a multiphase reference signal source for providing a reference signal to the basic phase locked loop; and a frequency discriminator and phase modulator. The frequency discriminator facilitates detection of whether the main loop of the frequency synthesizer is approaching a phase locking state for a proper change of the loop bandwidth. The phase modulator is employed to change the output phase of the reference signal source in order to speed up phase locking and make it applicable to creating signals with a rapid frequency switching speed, frequency tuning capability, and fine channel resolution.

Abstract: A method of controlling a frequency synthesizer and a frequency synthesizer having a controllable output signal frequency and including a direct digital synthesizer whose output signal is coupled to the input of a phase-locked loop. To reduce the settling time of the synthesizer, the direct digital synthesizer includes a control circuit for controlling the frequency of the direct digital synthesizer from a first frequency to a second frequency in accordance with predetermined frequency steps.

Abstract: A control circuit for causing a phase lock loop (PLL) frequency synthesizer to achieve a fast phase lock time while also providing improved loop performance during normal phase locked operation. The phase locking time of the PLL is minimized by initially configuring the PLL to operate in a fractional mode with high frequency signals presented to the inputs of the loop phase detector, thereby producing a fast phase lock time. Once the PLL has achieved phase lock, its operation mode is transitioned to either an integer mode or an open loop mode without loss of phase lock, thus causing lower frequency signals or no signals, respectively, to be presented to the inputs of the loop phase detector and thereby significantly reducing spurious signal tones.

Abstract: A fractional synthesis approach and arrangement are presented which achieve fine frequency resolution with low phase noise while at the same time retaining a high phase comparison frequency/fast frequency changing speed. An output signal having a desired output frequency is generated by a voltage controlled oscillator (VCO). An output divider divides the output frequency by an output divisor N to produce an output pulse train. The output divisor N may be equal to an output integer N or the output integer plus one N+1, for example, and may change during the generation of a single output frequency. For different desired output frequencies, the value of the output integer N may be varied. A reference divider divides a reference frequency by a reference divisor M to produce a reference pulse train. The reference divisor M may be equal to a reference integer M or the reference integer plus one M+1, for example, and may change during the generation of a single output frequency.

Abstract: A destuff circuit using a complete secondary system DPLL enables a DPLL circuit applicable to PDH low speed signal interface unit of a transmission communication apparatus to be shared. A switching signal from a selector causes a primary random walk filter, a secondary random walk filter, and counter number of a Q counter to be changed, and also causes the rate length of a rate multiplier to be changed, thereby providing a required DPLL circuit for a respective PDH low speed signal interface.

Abstract: A multiband PLL frequency synthesizer is disclosed which includes: a reference signal generation circuit for generating a reference signal of which frequency is controlled; a phase comparator for generating a phase difference signal; a low-pass filter circuit for low-pass-filtering the phase difference signal with one of a plurality of cutoff frequencies selected; a VCO for generating and outputting a LO signal according to an output of the low-pass filter; a frequency dividing circuit having an integer frequency dividing mode and a fraction frequency dividing mode to supply the frequency-divided signal to the phase comparator; and a control circuit for supplying the reference frequency control signal to the reference signal generation circuit, a filter control signal to the low-pass filter circuit, and frequency dividing control signal (data) to the frequency dividing circuit in accordance with a frequency command signal.

Abstract: A circuit (70) includes a reset stage (72) and a Phase-Locked Loop (PLL) device (73). The PLL device (73) includes a phase detector (74), a charge pump (75), a filter (76), and a Voltage-Controlled Oscillator (77). The reset stage (72) receives a reference signal and is connected to the phase detector (74). The phase detector (74) receives the reference signal and a feedback signal. When the reference signal switches from a first clock signal to a second clock signal, the reset stage (72) places the phase detector (74) in an inactive state until the reset stage (72) detects a falling edge in the reference signal.

Abstract: A phase-locked loop includes a phase/frequency detector, a charge pump, a loop filter, an oscillator and a feedback circuit coupled between the oscillator and the phase/frequency detector. The loop filter includes a first temperature-variable well resistor and has a gain directly related to resistance of the first resistor. An oscillator coupled to the loop filter includes a voltage-to-current converter that generates a reference current based on the loop filter voltage, and a current-controlled oscillator that generates the output clock based on the value of the reference current. The voltage-to-current converter includes a first transistor that receives the loop filter voltage at a gate and a second temperature-variable well resistor coupled to the source of the first transistor. The oscillator gain is indirectly related to the resistance of the second resistor. The second well resistor and first well resistor have substantially equal resistances and substantially equal temperature coefficients.

Abstract: An apparatus for limiting intermediate frequency variation in a multiple conversion phase locked loop includes a reference oscillator and a voltage controlled oscillator (VCO). The reference oscillator generates a first reference frequency, while the VCO generates an output frequency. The output frequency is divided by a first VCO divider and mixed with the first reference frequency to generate a first intermediate frequency. A second VCO divider also divides the output frequency and mixes it with the first intermediate frequency to generate a second intermediate frequency, which is filtered and used to control the VCO. An algorithm processor generates the division constants of the first and second VCO dividers as a function of the reference frequency and the output frequency to limit intermediate frequency variation.

Abstract: A digital phase locked loop (PLL) frequency synthesizer having the conventional voltage controlled oscillator (VCO) divider in the feedback loop to the phase detector replaced with a direct digital synthesizer (DDS) divider. In accordance with the principles of the present invention, the reference divider in the input path may also be replaced with a DDS divider. Moreover, a new architecture for the phase detector and current digital-to-analog converter (DAC) which operate on the instantaneous phase of each DDS is provided. Thus, in accordance with the principles of the present invention, the update rate of the digital PLL frequency synthesizer is not based on the frequency signal output from the reference divider in the input path (as in conventional digital PLL frequency synthesizer architectures). Rather, the update rate is based on fixed clock signals output from the clock generator, which utilizes the master clock and the output frequency, in accordance with the principles of the present invention.

Abstract: A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. Additional parameters are used to program the output frequency of a phase locked loop circuit coupled to receive the adjusted source frequency. A further parameter can also be used to divide the output frequency of the phase locked loop circuit to supply a specified output frequency. The oscillators can be manufactured as generic programmable crystal oscillators without regard for output frequency and then quickly programmed to produce customer-specified output frequencies with a high degree of accuracy.

Abstract: A dual-mode multiple signal source/local oscillator module is capable of operating in either an independent offset mode or a common offset mode. The module includes first and second coarse frequency sources, a first signal generator coupled to the first coarse frequency source, a second signal generator, and an offset switch coupled to the second signal generator. The offset switch connects the second signal generator to either the first coarse frequency source in the common offset mode, or the second coarse frequency source in the independent offset mode. Operation of the sources in the common offset mode provides the benefits of dynamic tracking which include reduction of receiver IF phase noise and spurious signal content, improved receiver IF settling speed, and higher measurement accuracy.

Abstract: The present invention is a timebase calibration system having a phase locked loop configuration. The system includes a phase detector having a first input receiving an output of an oscillator, and a second input which can be coupled to a frequency reference. The output of the phase detector is provided through a switch to a first input of a summer, while a second input of the summer is connected to a digital to analog (D/A) converter. The output of the summer is provided to a voltage control input of the timebase oscillator. The system further includes a digital voltmeter with an input connected to the output of the phase detector. With such a system, the output of the digital voltmeter provides a voltage proportional to the frequency error between the timebase oscillator and the frequency reference standard.

Abstract: A phase locked loop (PLL) oscillating circuit includes a first oscillating circuit, a lock detector and a reference oscillating circuit. The first oscillating circuit generates an oscillation signal with a first frequency, and controls the first frequency based on a reference signal. The lock detector detects phase lock between the oscillation signal and the reference signal to a lock detection signal. The reference oscillating circuit includes a crystal oscillation element, and generates the reference signal. An oscillation state of the reference oscillating circuit is controlled based on the lock detection signal.

Abstract: A circuit (70) includes a reset stage (72) and a Phase-Locked Loop (PLL) device (73). The PLL device (73) includes a phase detector (74), a charge pump (75), a filter (76), and a Voltage-Controlled Oscillator (77). The reset stage (72) receives a reference signal and is connected to the phase detector (74). The phase detector (74) receives the reference signal and a feedback signal. When the reference signal switches from a first clock signal to a second clock signal, the reset stage (72) places the phase detector (74) in an inactive state until the reset stage (72) detects a falling edge in the reference signal.

Abstract: A programmable dividing circuit comprises a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages being configured so that when an output of the last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated which has one cycle for every N cycles of a clock signal applied to the transistor stages.

Abstract: The object of the invention is to provide a lock-in process and device for a YIG-tuned oscillator which takes into account ageing and hysteresis of the YIG-tuned oscillator. This object is attained in that during a predetermined frequency change, the frequency of the YIG-tuned oscillator (1) is preset by means of a microprocessor (17) that progressively changes the current (I.sub.SP) in the main tuning coil (13) of the YIG-tuned oscillator (1) by an iterative capture routine, until the capture range (.DELTA.FM) of the switched-on frequency-locked loop, which changes with the coil current (I.sub.SP), includes the new operating frequency (f.sub.SET). The switched-on frequency-locked loop then pulls the oscillator frequency into the capture range of the PLL and the PLL locks-in the oscillator frequency to the new operating frequency (f.sub.SET). The microprocessor (17) interrupts the capture routine when a PLL-LOCK detector (11) announces to the microprocessor (17) that the new operating frequency (f.sub.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an output signal having a first frequency in response to (i) an input having a second frequency and (ii) a first control signal. The second circuit may be configured to generate the second frequency in response to (i) a plurality of third clock signals and (ii) a second control signal. The third circuit may be configured to present the first and second control signals in response to one of said plurality of third clock signals.

Abstract: An integrated circuit device and method for synthesis of a signal having a desired frequency and low noise. The integrated circuit embodiment of the invention generally includes a phase locked loop (PLL) circuit used in conjunction with a frequency multiplier. Specifically, the integrated circuit embodiment includes a frequency multiplier connected to a first input of a phase detector, a low pass filter connected between the output of the phase detector and the input of a voltage controlled oscillator (VCO), and a frequency divider connected between the output of the VCO and a second input to the phase detector. The frequency multiplier produces a signal having a frequency that is a multiple of the frequency of a reference signal which is connected to the input of the frequency multiplier. For any desired output frequency, use of the multiplier results in a smaller divider ratio "n" in the PLL, thereby reducing the closed loop noise inside the PLL loop bandwidth.

Abstract: The present invention is directed to apparatus and methods for reducing transient signals in phase locked loop (PLL) circuits of central processing units. One aspect of the present invention is directed to a method and apparatus that disables a charge pump circuit in a phase locked loop circuit when a frequency change in the output signal of the PLL circuit is implemented to limit transient signals generated by the PLL. Another aspect of the present invention is directed to a method and apparatus for coordinating a change in divider values for frequency dividers in a PLL of a CPU to limit transient signals from the PLL.

Abstract: A circuit for automatic frequency control includes an oscillator and a digital synthesis device to which a first frequency of the oscillator is supplied as a clock frequency and which generates an output signal having a second frequency. A frequency comparison device determines a frequency difference between the second frequency and a reference frequency and generates a digital output signal reproducing the frequency difference. The digital output signal is then supplied as an addition value to the digital synthesis device. The circuit for automatic frequency control generates a highly accurate and temperature-compensated output signal with the second frequency.

Abstract: A method and an apparatus for controlling a radar oscillator for use in the traffic field, in particular for a car radar, for generating a linear frequency sweep. A phase-locked linearization loop generates a linear frequency sweep controlling a phase-locked oscillator loop, which has a considerably broader bandwidth than the linearization loop.

Abstract: A circuit for reducing phase noise in a transmitted radio signal includes a first phase-locked loop circuit including a first controlled oscillator generating a first output signal at a first desired frequency, and a first phase comparator developing a first phase error signal to control the first controlled oscillator, the first error signal representative of phase differences between the first output signal and the first desired frequency. A second phase-locked loop circuit includes a second controlled oscillator generating a second output signal at a desired frequency of transmission related to the first desired frequency, and a second phase comparator developing a second phase error signal representative of phase differences between the first output signal and the desired frequency of transmission.

Abstract: A phase locking method and apparatus use an applied drive signal to acquire and maintain phase lock, and to prevent false locking in the presence of spurious signals. Locking signal and spurious signal components of a feedback signal within the feedback path of a phase locked loop are filtered and summed with the drive signal having a frequency offset from the loop's reference signal and an amplitude less than that of the locking signal and greater than that of the spurious signals. The summed signals are limited so that the overall phase of the limited signal is determined by the signal of highest amplitude. When the drive signal amplitude exceeds the amplitude of the filtered locking signal, the phase of the limited signal is determined by the drive signal. When the amplitude of the filtered locking signal exceeds the drive signal amplitude, the phase of the limited signal is determined by the locking signal.

Abstract: A frequency standard generator for generating a high accuracy reference frequency by synchronizing a high accuracy atomic frequency standard or equivalent thereof and minimizing a phase difference between the generated reference frequency and the received atomic frequency standard.

Abstract: A frequency synthesizer module with temperature compensation of a crystal oscillator circuit frequency controlled by a varactor. A module memory contains information characterizing a temperature dependency of a crystal which is applied to the varactor to temperature compensate the crystal in response to a temperature sensor signal. The module includes at least one locked loop circuit including a loop filter, at least one associated frequency divider, and a switchable dual band voltage controlled oscillator. The crystal oscillator is coupled to the at least one locked loop circuit and the frequency of the crystal is controlled by the memory via the varactor such that a temperature compensated output frequency is provided by the module.

Abstract: A phase locked loop circuit includes a reset signal generating circuit for generating a reference clock signal and a reset signal from an input clock signal. A phase locked loop section generates an output clock signal based on the reference clock signal such that a phase of the output clock signal is locked in that of the reference clock signal. Also, the phase locked loop section is reset in response to the reset signal such that the phase of the output clock signal is locked in an initial value.

Abstract: A phase interpolated frequency synthesizer with on chip tuning includes a voltage controlled oscillator, a fractional-N divider, phase compensation and on chip tuning circuits, a phase detector, and a loop filter. The phase compensation and on chip tuning circuits compensate for the phase lag from the fractional-N divider. The phase compensation circuit can include a series of voltage controlled delay elements with the tuning circuit providing a control voltage.

Abstract: A phase-locked-loop-stabilized voltage controlled oscillator relies on a sampling of the analog-frequency-control voltage of a voltage-controlled oscillator in a phase-locked-loop circuit to act as a reference voltage for a second free-running voltage-controlled oscillator. A vernier-adjustment voltage is injected into the control input of the second voltage-controlled oscillator to produce a finely variable derivative frequency not otherwise producible by a conventional phase-locked-loop circuit.

Abstract: A power management system is disclosed. The system includes an oscillator interface for use in a power management system, a power recycle circuit for use in a power management system, a pad clock and self test for use in a power management system, a clock enable circuit for use in a power management system, a power level detect circuit for use in a power management system, an internal source clock generation circuit for use in a power management system, and a power-save mode change detection circuit for use in a power management system. The oscillator interface includes an interle circuit for interfacing with an external oscillator used as a source of oscillations. A clock stabilization filter masks out spurious crystal frequencies in the oscillations during start-up of the power management system following an enabling of a feedback loop. The clock stabilization filter has circuitry which provides that the oscillations will start with a rising transition after filtering.

Abstract: An image data processing apparatus is described that prevents the period of a horizontal timing signal from being shifted. The apparatus includes a separator, a phase-locked loop, a detector, a compensator and a timing signal generator. The detector delays a reference clock signal in a shorter period than the period of the reference clock signal, in a step-like manner, to produce a plurality of delayed timing signals having step-like phase differences. The detector further contrasts the plurality of delayed timing signals with a horizontal sync signal and the reference clock signal to measure the phase difference and the period of the horizontal sync signal. The compensator sets a ratio for combining consecutive luminance data in accordance with the phase difference and the period of the reference clock signal and combines consecutive luminance data in accordance with the ratio to generate compensated luminance data.

Abstract: A high speed frequency generator is disclosed. The frequency generator includes a frequency oscillator producing an output signal of a predetermined frequency, a first frequency divider frequency-dividing the first frequency oscillator's output signal, and a second frequency divider frequency-dividing an input signal by a predetermined factor. A flip-flop receives a signal generated from the second frequency divider and produces an output signal in accordance with an input clock signal. A pulse-width detector detects a width of the output signal of the flip-flop. A comparing part compares an output signal of the pulse-width detector with a reference value to control a counter that counts to a prescribed digital value that corresponds to a desired frequency. A digital-analog converter converts an output digital value from the counter into an analog value.

Abstract: A method for increasing a working speed in a synchronous digital system, which includes a plurality of separate system parts, and for permitting communication between at least two of the system parts. A common reference signal having a reference frequency is distributed to all system parts. An internal signal clock oscillator of each system part is phase locked to the reference signal. Data is communicated between the at least two system parts by relating the reference signal with the internal clock signal of each of the two system parts by adjusting a phase position of the internal clock signal of a second of the two system parts dependent upon a time delay of the data communicated from the first system part to the second system part so that the phase positions of the internal clock signals correspond.

Abstract: A digital phase lock detector and phase lock loop filter selector circuit implemented in hardware that dynamically selects a phase lock loop filter of appropriate bandwidth for the instant phase error condition. Phase error is primarily determined by an XOR gate receiving the PLL reference signal and the oscillator feedback signal coupled to a counter that is clocked by a high frequency signal.

Abstract: A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. Additional parameters are used to program the output frequency of a phase locked loop circuit coupled to receive the adjusted source frequency. A further parameter can also be used to divide the output frequency of the phase locked loop circuit to supply a specified output frequency. The oscillators can be manufactured as generic programmable crystal oscillators without regard for output frequency and then quickly programmed to produce customer-specified output frequencies with a high degree of accuracy.

Abstract: A digitally-controlled frequency synthesizer circuit is provided. The synthesizer circuit has a synthesizer that provides as an output a signal that is based on a reference frequency supplied from a resonator circuit. The reference frequency of the resonator circuit can be tuned by varying the control voltage applied to a voltage variable capacitor that is coupled to the resonator circuit. The voltage variable capacitor is located on the synthesizer. A digital-to-analog converter is also located on the synthesizer. The digital-to-analog converter provides the analog control voltage for the voltage variable capacitor based on digital voltage control data.

Abstract: A frequency synthesizer is supplied with an input signal of frequency .function..sub.i to provide an output signal .function..sub.o where .function..sub.o=.function..sub.i M/N and M and N are integers. The input signal is first applied to a divider circuit for division by M/K where K is an integer and the resultant is applied as inputs to a phase locked loop. The phase locked loop includes a ring oscillator of frequency .function..sub.i N/M, a frequency multiplier circuit for multiplying by K, and a frequency divider circuit for dividing by N. The ring oscillator uses a combinational logic circuit that combines the outputs of four differential delay elements to produce a frequency multiplication of four.

Abstract: Phase locked loops include a controlled oscillator that is responsive to a control signal, to generate an output signal, the frequency of which is a function of the control signal. A phase detector is responsive to a reference frequency input signal and to the output signal, to produce an error signal. A loop filter filters the error signal, to thereby produce the control signal. A bandpass filter is responsive to the error signal, to produce a filtered error signal at twice the frequency of the reference frequency, and an envelope detector is responsive to the filtered error signal to sense the amplitude of the filtered error signal. A variable attenuation circuit is responsive to the envelope detector output, to variably attenuate a phase locked loop input signal based on the amplitude of the filtered error signal, and thereby produce the reference frequency input signal.

Abstract: A method and apparatus for reducing power consumption in a communication device. In a standby mode, a relatively high power clock with a high degree of accuracy is powered down and a lower power, low frequency clock is used to maintain system synchronization. Synchronization means are provided to improve the accuracy of the low frequency clock during the standby mode.

Abstract: A global positioning system (GPS) receiver and high accuracy low power time source (HAL) are disclosed. The HAL provides a time source having an accuracy which is high enough for the receiver to achieve fast direct Y-code acquisition. The HAL includes an oscillator adapted to provide an uncompensated frequency signal at a desired frequency. Frequency conversion circuitry receives the uncompensated frequency signal and a control signal as inputs, and provides as an output a compensated frequency signal having an average compensated frequency which is closer to the desired frequency than is the average uncompensated frequency. A temperature sensor provides an output indicative of a temperature of the oscillator. Frequency error determining circuitry determines an error value, as a function of the temperature sensor output, which is indicative of a quantity of frequency error over time in the uncompensated frequency signal.

Abstract: An oscillation circuit stops the oscillation of an external oscillator to reduce the current consumed when a frequency lower than the inherent frequency of the external oscillator is supplied to a microcomputer. A PLL circuit 37 generates a second clock 45 from a first clock 23 output by an oscillation circuit 1. A PLL lock signal 47 is changed from a first level to a second level when the second clock 45 is generated. A selector 39 outputs the second clock 45 as an internal clock 13 when the PLL lock signal 47 is at the second level. The operation of an oscillator 9 is stopped when the PLL lock signal 47 is at the second level.

Abstract: A self-tuning clock recovery phase-locked loop (PLL) includes a programmable divide-by-M, a phase-frequency detector, a programmable voltage-controlled oscillator (VCO), a programmable divide-by-N, and a PLL tuning circuit, which in normal mode operation, perform as a conventional PLL. When the frequency of an input clock signal to the PLL changes by more than a threshold value, however, the PLL tuning circuit causes the PLL to be retuned for the new frequency by adjusting offset and gain parameters in the PLL such that the input voltage to the VCO is mid-way in its input voltage range when the output clock frequency of the PLL is approximately equal to the input clock frequency multiplied by a closed loop gain of the PLL, so that the VCO is operating in a linear region having wide dynamic frequency range.

Abstract: A method and apparatus for controlling frequency synchronization in a frequency correction feedback loop of a radio telephone. A processor in a frequency update controller ascertains increment/decrement values pro-proportionally related to confidence levels representing a ratio that a likelihood probability of estimated offset frequecies of an input carrier signal are accurate in proportion to a likelihood probability that the estimated offset frequencies are inaccurate. The processor adds or subtracts the value to a counter depending on its sign. When the counter reaches a certain predefined positive number, the counter is decremented by this number and the processor increases the frequency of a reference oscillator frequency. When the counter reaches a certain predefined negative number, the counter is incremented by the absolute value of the negative number and the processor decreases the frequency of the reference oscillator frequency.