Abstract: Realizing ZVS and ZCS in a CCM Boost Converter with BCM control with a single switch. Embodiments disclosed herein relate to continuous conduction mode (CCM) boost converters and more particularly to continuous conduction mode (CCM) boost converters with boundary control mode. The embodiments herein achieve a scheme to achieve complete soft switching of all the switching elements of a boost converter, without incorporating any additional auxiliary switch, wherein total soft switching is achieved by inserting a fly back transformer in series with a normal boost converter operating in a continuous conduction mode, and adopting boundary control mode.

Abstract: A Delta-Sigma modulator architecture is disclosed that uses interleaving and dynamic matching algorithms to address the needs of multi-mode, multi-band high bandwidth transmitters. The proposed architecture also supports a novel software defined transmitter architecture based on an interleaved Delta-Sigma modulator to generate RF signals. The proposed architecture leverages interleaving concepts to relax subcomponent clock rates without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies. The DEM algorithm helps to randomize mismatch errors across all interleaved paths and improves substantially the signal-to-noise ratio. Additionally, a tunable bandpass filter can be added to reject out-of-band emissions.

Abstract: To achieve both response speed and accuracy required for a flow rate measuring device without sacrificing the simplicity and inexpensiveness of a PWM type D/A converter, the flow rate measuring device includes an analog conversion part adapted to convert a digital signal indicating a measured flow rate value to an analog signal. In addition, the analog conversion part includes: a PWM signal generating circuit that can output three or more specified voltages is configured to, on the basis of the measured flow rate value indicated by the digital signal, select two adjacent voltages, as well as on the basis of the measured flow rate value indicated by the digital signal, set a duty ratio to generate a PWM signal of which a high level and a low level are the two selected voltages, respectively; and a conversion circuit that smooths the PWM signal to convert to the analog signal.

Abstract: Power consumption of a successive-approximation type analog to digital converter is reduced. A system is provided with an analog to digital converter and a power-supply voltage generation unit. In the system provided with the analog to digital converter and the power-supply voltage generation unit, the analog to digital converter compares an analog signal with a reference signal and outputs frequency information indicating the number of times of comparison. Also, in the system, the power-supply voltage generation unit generates power-supply voltage on the basis of the frequency information output by the analog to digital converter and supplies the same to the analog to digital converter.

Abstract: A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

Abstract: Techniques that allow application of noise-shaped dither without applying dither at sampling, resulting in the analog-to-digital converter (ADC) circuit advantageously being balanced during acquisition. Balancing the ADC circuit at acquisition can reduce the risk of sampling digital interferences that can couple in through the references or substrates.

Abstract: A differential sampling circuit includes: a first switching element having a first terminal receiving a first signal of a differential signal pair, a second switching element having a first terminal receiving a second signal of the differential signal pair, a first sampling capacitor connected between two second terminals of the first and the second switching elements, a third switching element connected between the second terminal of the second switching element and a reference voltage, a fourth switching element having a first terminal receiving the second signal, a fifth switching element having a first terminal receiving the first signal, a second sampling capacitor connected between two second terminals of the fourth and the fifth switching elements, and a sixth switching element connected between the second terminal of the fifth switching element and the reference voltage.

Abstract: An interleaved DAC utilizes a set of positive sub-DACs and a set of negative sub-DACs for converting digital inputs in parallel without return to zero. For each digital input, a positive sub-DAC performs conversion and drives its analog output for a duration of N/fs; and a negative sub-DAC performs conversion and drives its analog output for a duration of (N?1)/fs, and by a delay of 1/fs. The positive sub-DAC and the negative sub-DAC start the conversion at the same time. By combining the outputs from the two sets of sub-DACs, the output from the positive sub-DAC is effectively removed when it is no longer needed at the combined output. As a result, the combined analog signal has each data point valid only for a duration of T, thereby achieving the desired data conversion speed of fs.

Abstract: A semiconductor device includes a first mode signal generation circuit suitable for generating a first mode signal in response to a command, the first mode signal being enabled in the case where a first period determined depending on a current characteristic of a first MOS transistor is longer than a second period determined by a first passive element; and a second mode signal generation circuit suitable for generating a second mode signal in response to the command, the second mode signal being enabled in the case where a third period determined by a second passive element is longer than a fourth period determined depending on a current characteristic of a second MOS transistor.

Abstract: Embodiments of the present disclosure relate to a digital-to-analog conversion circuit and method, a source driver, and a display apparatus. The digital-to-analog conversion circuit includes a first digital-to-analog converter corresponding to m high bits of (m+n)-bit digital signal and a second digital-to-analog converter corresponding to n low bits, where m and n are integers greater than 0. The first digital-to-analog converter comprises a voltage division module configured to generate 2m reference voltages at equal intervals in voltage; a first voltage selection module configured to select, from the 2m reference voltages, a first voltage corresponding to the m bits; and an operation module configured to generate a second voltage higher than the first voltage by the interval in voltage based on two adjacent reference voltages of the 2m reference voltages and the first voltage.

Abstract: Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit.

Abstract: A semiconductor device includes a transistor including a first gate (front gate) and a second gate (back gate) overlapping with each other with a semiconductor film therebetween, and a display element. The transistor and the display element are electrically connected to each other. The first gate is supplied with one of 2N?k potentials. The second gate is supplied with one of 2k potentials. One of 2N?k potentials and one of 2k potentials are obtained in such a manner that N-bit digital data is divided into (N?k)-bit digital data and k-bit digital data and they are subjected to D/A conversion. At this time, the total number of gray level power supply lines used for D/A conversion is equal to the sum of 2N?k and 2k. This is smaller than 2N, which the total number of the gray level power supply lines usually needed for D/A conversion of N-bit digital data.

Abstract: Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

Abstract: A method and apparatus for implementing FIR filters in a processor includes a plurality of execution units executing instructions of an instruction set. The execution units include a number of FIR filter circuits, each of which is associated with a corresponding one of a number FIR filter instructions. Furthermore, each of the FIR filter circuits is and dedicated exclusively to executing its corresponding one of the FIR filter instructions. Each FIR filter execution unit receives input data and provides filtered output data.

Abstract: A digital to analog converter (DAC) that provides an output that is iteratively stepped as the DAC increments or decrements from its digital input to analog output. The DAC has configurable registers to store a timer count value, an iteration value, and the input value. A state machine compares the iteration value to current DAC values, and adds or subtracts the iteration value until the final output is reached.

Abstract: Embodiments of the present application provide a digital-to-analog conversion circuit, a method thereof and a display apparatus. The digital-to-analog conversion circuit comprises a voltage dividing sub-circuit, having 2m of voltage dividing signal terminals and 2n-m?1 of sub-voltage dividing signal terminals; a first voltage selecting sub-circuit, configured to receive the first bit to the (n?m)th bit of the digital signal, and convert it into a first analog signal; a second voltage selecting sub-circuit, configured to receive the (n-m+1)th bit to the nth bit of the digital signal and to convert it into a second analog signal; and a buffering sub-circuit, configured to generate an analog signal based on the first analog signal, the second analog signal and the signal from the ith voltage dividing signal terminal and to output the analog signal to an analog signal outputting terminal of the digital-to-analog conversion circuit.

Abstract: A method for approximating a first signal having a first oscillation period within a quantized time interval using a second signal is provided. The second signal has a second oscillation period. The method includes calculating a phase offset of the first signal at at least one position within the quantized time interval. Further, the method comprises shifting the second signal within the quantized time interval until a phase offset of the second signal at the at least one position satisfies a quality criterion related to the phase offset of the first signal.

Abstract: Provided are a source driver for receiving a digital signal and providing a grayscale signal corresponding to the digital signal and a display device for displaying content. The source driver includes an amplifier configured to provide a grayscale signal, a second driving switch configured to provide the grayscale signal provided by the amplifier to an output node or block the grayscale signal, and a first driving unit including a first switch whose one end is connected to a first voltage and whose other end is connected to the output node and a second switch whose one end is connected to a second voltage and whose other end is connected to the output node, and configured to first drive the output node. The output node is first driven by the first driving unit and then second driven by the amplifier with the grayscale signal.

Abstract: Converter circuits and methods herein describe mechanisms for converting a digital input signal to an analog output signal using a series of transmission lines. The circuits and methods described herein convert to analog signal using very little power, due to inter-coupling of wave propagation media.

Abstract: A timing controller including a memory unit configured to store image data with respect to p*q sub-pixels defined using p numbers of data lines and q numbers of gate lines, a reception unit configured to receive, from a host, (n+m)-bit image data with respect to each of two or more of the sub-pixels, a controller configured to generate pseudo control data corresponding to m-bit image data of the two or more of the sub-pixels, and an output unit configured to output n-bit image data with respect to each of the sub-pixels to a digital unit of a data driving unit, and output the pseudo control data to an analog unit of the data driving unit.

Abstract: A subscriber station for a bus system and a method for reducing wire-bound emissions in a bus system are provided. The subscriber station includes a digital-analog converter for converting a digital signal into an analog signal, and an analog-digital converter, the digital-analog converter and the analog-digital converter being connected for a balancing of the dominant bus state of the bus system.

Abstract: In a general aspect, an apparatus can include a signal analyzer configured to analyze a signal associated with a processing pipeline, and a dynamic element matching (DEM) selection module configured to select a DEM algorithm from a plurality of DEM algorithms based on the analysis performed by the signal analyzer. The apparatus can include a set of circuit elements where each circuit element from the set of circuit elements has the same logical configuration, and a circuit element selection module configured to select a subset of the set of circuit elements based on the selected DEM algorithm.

Abstract: A method for operating a magnetic resonance tomograph having at least one receiving antenna, at least one converter device for analog/digital conversion and a programmable computing device is provided. The method includes generating, with the converter device, digital measured values by digitizing the analog reception signal from the receiving antenna and/or at least one analog signal derived from the reception signal. A time-coding device adds an item of time information that describes the recording time of the measured values to each of the digital measured values or to groups of measured values including a plurality of the digital measured values in order to generate a time-coded data stream. The programmable computing device processes the time-coded data stream further.

Abstract: A keeper based switch driver can generate overlapping differential signals and increase a crossing point of the overlapping differential signals a first predetermined amount. Additionally, the keeper based switch driver can further increase the crossing point of the overlapping differential signals a second predetermined amount and limit signal swing to an absolute value of a drain-source voltage. A microprocessor can also be electrically connected to a DAC cell with keeper based switch driver through a performance detection circuit. The microprocessor can be configured to receive information from a performance detection circuit and control a current of a variable current source in a keeper bias circuit accordingly.

Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

Abstract: The present disclosure relates to an apparatus for use in a transition-minimized differential signaling link (“TMDS”) receiver. The apparatus may include an integrated circuit electrically connected with a voltage supply. The integrated circuit may include a first transistor, a second transistor, and a resistor arranged in a cascaded configuration along a termination path. The first transistor may include calibration code control configured to adjust an output impedence.

Abstract: A computational sensing array includes an array of sensing elements. In each sensing element, a first signal is generated from a transducer. A second signal is produced by a collection unit in response to receiving the first signal. The second signal may be modified, in a conditioning unit. A sensing element preprocessing unit generates a word representing the value of the modified second signal, and may produce an indication of change of the first signal. A current value of the word may be stored in a state holding element local to the sensing element, and a previous value of the word may be retained in a further state holding element local to the sensing element.

Abstract: An optical transmitter multiplexes multiple optical channels for transmission over an optical communication medium. The spectrum of modulated signal in each optical channel is lowpass filtered in the electrical (digital) domain at half the channel baud rate such that super Nyquist signal multiplexing can be achieved in the optical domain without having to perform optical filtering. An optical coupler may be used to multiplex the multiple optical channels.

Abstract: The disclosure relates to a predistortion device for a non-linear PA device, comprising: an input terminal for receiving an input signal; a predistortion filter, connected between the input terminal and the non-linear PA device; a first delay element, coupled to the input terminal, and configured to delay the input signal by a time delay D to provide a delayed input signal; and an adaptive filter unit, comprising an adaptive filter having adjustable filter weights, and configured to filter the delayed input signal, and an adjusting unit, wherein the adjusting unit is configured to process an adaptive algorithm, based on the delayed input signal, to adjust the filter weights of the adaptive filter, and to provide both the adaptive filter and the predistortion filter with the same adjusted filter weights.

Abstract: Disclosed is a correcting device of successive approximation analog-to-digital conversion. The correcting device includes a successive approximation register analog-to-digital converter (SAR ADC) and a digital circuit. The SAR ADC is configured to generate a digital output. The digital circuit is configured to determine whether the digital output conforms to a metastable output, and correct the digital output when the digital output conforms to the metastable output. The metastable output is related with a metastable binary comparison-results sequence including successive K comparison results such as 110000 or 001111. The K comparison results include a first comparison result, a second comparison result and successive M comparison results in turn. The first comparison result and the second comparison result are the same; the M comparison results are the same; each of the first comparison result and the second comparison result is different from any of the M comparison results.

Abstract: A DA converter has a first DA conversion unit that converts a first bit string signal corresponding to a MSB side string of a digital input signal into a first analog value, a second DA conversion unit that converts a second bit string signal corresponding to an LSB side string of the digital input signal into a second analog value, a third DA conversion unit that has identical circuitry configuration and identical circuitry area as the second DA conversion unit and converts a first digital signal into a third analog value, an analog calculator that calculates a value obtained by subtracting the third analog value from a value obtained by adding the second analog value to the first analog value, a quantizer that outputs a second digital signal obtained by quantizing an output value of the analog calculator, and a control logic unit that generates the first digital signal.

Abstract: An N bit digital-to-analog converter DAC is based on a first stage including a first set of resistors corresponding to higher order bits of the digital input, and a second stage including a second set of resistors corresponding to lower order bits of the digital input. A plurality of pass transistors is arrange to connect a first subset of the first set of resistors in the first stage selected in response to a digital input to a second subset of the second set of resistors in the second stage selected in response to the digital input. A means for reducing variations in a sum of on-resistances RON of the pass transistors in the plurality of pass transistors selected in response to a digital input is provided, resulting in more uniform steps in output voltage of the DAC over a wider range.

Abstract: A switching digital-to-analog converter (DAC) includes a logic gate for receiving a digital input signal having rising and falling edges defining an input pulse width, and outputting an offset input signal having rising and falling edges defining a mismatched pulse width different from the input pulse width due to relative movement of the rising and falling edges in response to a voltage offset introduced by the logic gate. A DC voltage source provides a direct current (DC) calibration signal, and a summer adds the DC calibration signal and the offset input signal to compensate for the voltage offset introduced by the logic gate, and to provide a corrected input signal. A unit DAC receives the corrected input signal, and selectively switches current to an output of the switching DAC in response to voltage values of the corrected input signal to provide an analog output.

Abstract: A node of a full duplex wireless transmission system may include cancellation signal generation elements. The cancellation signal generation elements may extract a waveform from received signals, for example signals transmitted from the node, and use the waveform to generate a prefilter or cancellation signal to apply to further received signals. The cancellation signal may cancel interference in received signals caused by signals transmitted from the node.

Abstract: A digital to analog converter (DAC) includes a first sub-DAC configured to convert most significant bits (MSBs) of digital input data, the first sub-DAC including a first array of resistors, a second sub-DAC configured to convert at least some least significant bits (LSBs) of the digital input data, the second sub-DAC including a second array of resistors, and a first scaling resistor connected between the first and second sub-DACs, wherein the first scaling resistor has a resistance value that is based on the number of resistors in the second sub-DAC.

Abstract: A digital to analog converter (DAC) circuit is disclosed which employs isolation providing cascode devices to reduce data dependent signal distortion. A DAC circuit configured according to an embodiment includes a current source associated with each bit of a digital word that is to be converted. Each current source is coupled to a current switch that is controlled by the associated bit. The DAC also includes a cascode device coupled to each of the current switches through a feed line. The DAC further includes a summing junction configured to generate an analog output signal corresponding to the digital word based on a sum of currents provided by the current sources, through the current switches and the feed lines. The cascode devices provide impedance matching and isolation between the feed lines and the summing junction to reduce signal reflections between the current switches and the summing junction to improve conversion performance.

Abstract: An interfacing circuit adaptable to an analog-to-digital converter (ADC) includes a sample and hold (S/H) circuit; an input switch; an input capacitor with a first end connected to an input end of a comparator of the ADC via the S/H circuit, and with a second end connected to receive an input signal via the input switch; a hold switch connected between the second end of the input capacitor and an original common-mode voltage; a reset switch connected between the input end of the comparator and a target common-mode voltage; and a front switch connected between the first end of the input capacitor and the target common-mode voltage.

Abstract: A voltage generating circuit includes: a first output voltage generator to receive an input voltage, to output a first output voltage, to compare the input voltage with a first reference voltage, and to stop the output of the first output voltage according to the comparison; and a second output voltage generator to receive the input voltage, to output a second output voltage, to compare the input voltage with a second reference voltage, and to stop the output of the second output voltage according to the comparison. The first output voltage generator is to compare first reference voltage data with second reference voltage data, and to change the first reference voltage according to the comparison. The second output voltage generator is to compare the first reference voltage data with the second reference voltage data, and to change the second reference voltage according to the comparison.

Abstract: An apparatus for controlling an automated installation has a first controller and a second controller that are connected to one another via a communication network. The first and second controllers each have a local clock and execute control tasks. The first and second controllers each further have a synchronization service that is used to synchronize the respective local clocks to a common reference clock. A timer repeatedly sends a trigger message to the first and second controllers. Each of the two controllers, on receiving the trigger message, determines a local time. The controllers interchange the respective local time and each compute a difference between their own local time and the local time obtained from the other controller. On the basis of the difference, each of the two controllers controls a local actuator.

Abstract: Methods and systems for a baseband cross-bar may comprise receiving one or more radio frequency (RF) signals in a wireless communication device via antennas coupled to a plurality of receiver paths in the wireless device. The received RF signals may be converted to baseband frequencies. One or more of the down-converted signals may be coupled to receiver paths utilizing a baseband cross-bar. The baseband cross-bar may comprise a plurality of switches, which may comprise CMOS transistors. In-phase and quadrature signals may be processed in the one or more of the plurality of receiver paths. The one or more RF signals comprise cellular signals and/or global navigation satellite signals. A single-ended received RF signal may be converted to a differential signal in one or more of the plurality of receiver paths. The baseband cross-bar may be controlled utilizing a reduced instruction set computing (RISC) processor.

Abstract: A duty cycle adjustment circuit includes: a delay circuit to delay an input clock signal to produce a delayed clock signal having a rising edge partially overlapping the rising edge of the input clock signal, the input clock signal oscillating between first and second values about a midpoint value; a blender circuit to blend the input clock signal and the delayed clock signal to produce a blended clock signal; a buffer circuit to buffer the input clock signal for an amount of time comparable to the blender circuit, to produce a buffered clock signal; and a combiner circuit to combine the buffered and the blended clock signals to produce an output clock signal that transitions to or remains at the first value when both the buffered and blended clock signals are on the first value side of the midpoint value, and otherwise transitions to or remains at the second value.

Abstract: Advanced detectors for vector signaling codes are disclosed which utilize multi-input comparators, generalized on-level slicing, reference generation based on maximum swing, and reference generation based on recent values. Vector signaling codes communicate information as groups of symbols which, when transmitted over multiple communications channels, may be received as mixed sets of symbols from different transmission groups due to propagation time variations between channels. Systems and methods are disclosed which compensate receivers and transmitters for these effects and/or utilize codes having increased immunity to such variations, and circuits are described that efficiently implement their component functions.

Abstract: During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.

Abstract: A sigma-delta modulator arrangement includes a continuous-time sigma-delta modulator with at least one modulator stage, a digital integrator and a given number of switches. The switches are arranged and configured to convert the continuous-time sigma-delta modulator into a first order incremental sigma-delta analog-to-digital converter comprising the digital integrator. At least a first modulator stage of the continuous-time sigma-delta-modulator, which is coupled with an input of the continuous-time sigma-delta modulator, includes at least one tuning element for adjusting an input signal and/or a feedback signal which are supplied to the first modulator stage.

Abstract: Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

Abstract: Provided is an optical receiver module which includes a conversion unit which converts an input optical signal to an electrical signal, an amplification unit which amplifies the electrical signal and outputs an amplified signal, a reception unit which directly or indirectly receives the amplified signal, and an offsetting unit which offsets the electrical signal such that a difference between a center of an intensity width of the electrical signal and a center of an intensity range of a signal capable of being received by the reception unit becomes small.

Abstract: A digital-to-analog converter (DAC) includes a plurality of resistive elements connected together in series to form a ring of resistive elements. A node is formed by each of the connections of adjacent resistive elements of the ring. Groups of parallel-connected switches are coupled to each node. A first switch of the group of switches is for selectively coupling a first power supply voltage terminal to the node. A second switch of the group of switches is for selectively coupling a second power supply voltage to the node. A third switch of the group of switches is for selectively coupling an output terminal to the node. A differential or single-ended analog output may be provided. Mismatch induced error is removed using a mismatch error shaping technique that shapes the errors outside a pass-band.

Abstract: Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit.

Abstract: An input system includes an input pen for interfacing with a touchscreen of a display panel. The input pen includes a conductive tip. A switching unit of the pen connects the conductive tip to a receiving unit and a driving unit. The receiving unit receives touchscreen driving signals from the touchscreen through the conductive tip. The driving unit generates pen driving signals transferred to the touchscreen through the conductive tip. The input pen also include a signal processing unit to calibrate timing of the pen driving signal by synchronizing the pen driving signal with the touchscreen driving signal. To enable touch detection, the conductive tip is positioned to contact or approach the touchscreen, the touchscreen driving signal is received from the touchscreen via the conductive tip. The pen driving signal is generated and transferred to the touchscreen via the conductive tip.

Abstract: A decision feedback equalizer includes a comparator configured to output a constant voltage in a reset period and to output a differential voltage corresponding to differential input signals in an evaluation period, a latch circuit configured to hold the differential voltage in the evaluation period, and an adjuster configured to adjust a logical threshold of the latch circuit closer to the output voltage in the reset period.