Abstract: A digital to analog converter that includes a delta sigma modulator coupled to receive a digital data. The delta sigma modulator supplies a multi-bit resistor digital to analog converter (DAC). The multi-bit resistor digital to analog converter supplies an amplifier with an analog signal corresponding to the digital data. A first low pass filter is coupled between the multi-bit digital to analog converter and the amplifier stage and filters out shaped quantization noise before it reaches the amplifier. A second low pass filter is coupled to an output of the amplifier stage and filters out residual quantization noise and chopping artifacts from the amplifier stage.

Abstract: Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications.

Abstract: A voltage mode signal transmitter includes a front-end signal processor and a signal transformer. The front-end signal processor receives a first and second data signal, and delays and inverts the data signals to generate a third and fourth data signal. The front-end signal processor selects two of the first data signal to the fourth data signal to generate a plurality of signal pairs according to a first control signal. The signal transformer selects one data signal of each of the signal pairs to generate input voltages according to a second control signal, and generates an output voltage according to the input voltages. A working frequency of the first control signal is lower than a working frequency of the second control signal.

Abstract: A radiation hardened, digital to analog converter includes first and second serial communication circuits, a common bus interface configured to connect the first and second serial communication circuits to first and second digital serial communication buses, respectively, and a digital to analog converter circuit, where the first and second serial communication circuits are configured to receive data over the first and second digital serial communication buses, respectively, for use by the digital to analog converter circuit.

Abstract: An analog-to-digital converter (ADC) includes a capacitive digital-to-analog converter (CDAC), a comparator, and a successive approximation register (SAR) control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an output of the comparator and to an input of the CDAC. The SAR control circuit includes a flip-flop. The flip-flop includes a clock input terminal, a data input terminal, and an output. The clock input terminal is coupled to the output of the comparator. The data input terminal coupled to a constant voltage source. The flip-flop can include an enable input terminal coupled to a SAR state circuit. The output is coupled to the CDAC.

Abstract: An apparatus is described. The apparatus according to an embodiment includes a voltage dividing resistor circuit formed on a semiconductor substrate and including first and second resistors and first and second selector switches. The first and second resistors and the first and second selector switches are arranged with one of first and second layouts. The first layout is such that the first and second selector switches are placed between the first and second resistors. The second layout is such that the first and second resistors are placed between the first and second selector switches.

Abstract: A DA conversion device includes a level determiner determining whether a level of the digital signal or the analog signal is higher than a predetermined threshold value; a DA converter including plural capacitors, an operational amplifier which generates the analog signal, and a plurality of transistors which connects each of the plural capacitors to a first or a second reference voltage according to the digital signal in a first connection state and connects the plural capacitors between an input terminal and an output terminal of the operational amplifier in a second connection state; and a setting part which receives a clock signal and sets gate-source voltages of the plurality of transistors such that the plurality of transistors is in the first connection state in a first period of the clock signal and the plurality of transistors is in the second connection state in a second period of the clock signal.

Abstract: A mapping circuit (300) for selecting cells of a multi core hybrid I/Q digital to analog converter includes a first sub-mapping circuit (310a) configured to define a first group of cores for each data symbol to be transmitted and to select cells of the first group of cores for an I-code of the data symbol to be transmitted. The mapping circuit (310b) further includes a second sub-mapping circuit configured to define a second group of cores for each data symbol and to select cells of the second group of cores for a Q-code of the data symbol.

Abstract: An image sensor may contain an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to an analog-to-digital converter for converting analog imaging signals from the pixels to digital signals. The analog-to-digital converter may be implemented as a split successive approximation register (SAR) analog-to-digital converter (ADC). The split SAR ADC may include a coarse section and a fine section. During a reset sampling phase, a reset level is sampled with a predetermined pedestal value is applied to the coarse and fine sections. During reset conversion, a reset code is obtained. During a signal sampling phase, a signal level is sampled using inverted bits of the reset code for only the fine section. During signal conversion, a signal code is obtained. Operated in this way, differential non-linearity of the ADC is minimized.

Abstract: In certain aspects, a clock generator includes a ring oscillator including an input and an output. The clock generator also includes a count circuit including an input and an output, wherein the input of the count circuit is coupled to the output of the ring oscillator. The clock generator also includes a comparator including a first input, a second input, and an output, wherein the first input of the comparator is configured to receive a first count value, and the second input of the comparator is coupled to the output of the count circuit. The clock generator further includes a shift register including a shift control input and an output, wherein the shift control input is coupled to the output of the comparator, and the output of the shift register is coupled to the input of the ring oscillator.

Abstract: Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications.

Abstract: A semiconductor device in which an increase of circuit area is prevented is provided. A semiconductor device including a control circuit with a plurality of scan chain circuits, a DA converter electrically connected to the control circuit, and a plurality of potential holding units electrically connected to the DA converter is provided. The plurality of potential holding units each include a transistor including an oxide semiconductor in a channel formation region and a capacitor electrically connected to the transistor. In accordance with digital data held in any one of the plurality of scan chain circuits, an output potential output from the DA converter is held in any one of the plurality of potential holding units.

Abstract: A digital to analog converter receives a digital input consisting of first least significant bits, second most significant bits, and third middle significant bits. The digital to analog converter includes first, second, and third sub-DACs. The first sub-DAC receives the first least significant bits, and includes first resistors each contributing a respective voltage, to provide a first output. The second sub-DAC receives the second most significant bits, and includes second resistors each contributing a respective voltage, to provide a second output as an output of the digital to analog converter. The third sub-DAC is connected to the first sub-DAC to receive the first output, and receives the third middle significant bits, and includes third resistors each contributing a respective voltage, to provide a third output to the second sub-DAC. The first and third resistors each has a physical area less than an area of each second resistor.

Abstract: A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

Abstract: An analog-to-digital converter includes: a first to an (m+1)-th capacitive element each of which has a first end connected to a first terminal of a comparison circuit and have a predetermined capacitance ratio; and selection circuits which are connected to second ends of the capacitive elements, respectively. Each of the capacitive elements includes: a first electrode disposed in a semiconductor substrate and electrically connected to the second end; a third electrode disposed above the semiconductor substrate to oppose the first electrode and electrically connected to the second end; a second electrode disposed between the first electrode and the third electrode, above the semiconductor substrate, and electrically connected to the first end; a first insulation film disposed between the first and second electrodes; and a second insulation film disposed between the third and second electrodes.

Abstract: A method may include receiving a stream of serial pulse-density modulation (PDM) data representing a first channel of data synchronized with a rising edge of a clock associated with the serial PDM data and a second channel of data synchronized with a falling edge of the clock, wherein each of the first channel of data and the second channel of data include encoded datagrams wherein each encoded datagram comprises more than one digital bit, detecting an invalid state associated with the stream, and responsive to detecting the invalid state, determining boundaries of each encoded datagram of the stream based on where within the stream the invalid state occurred.

Abstract: An analog signal processor includes a sampling unit configured to (i) filter, in the frequency domain, a received time domain analog signal into a low-frequency end of a corresponding frequency spectrum, (ii) sample the filtered analog signal at a frequency substantially higher than the low-frequency end, and (iii) spread quantization noise over an expanded Nyquist zone of the corresponding frequency spectrum. The processor further includes a noise shaping unit configured to shape the spread quantization noise out of the low-frequency end of the corresponding frequency spectrum such that the filtered analog signal and the shaped quantization noise are substantially separated in the frequency domain, and a quantization unit configured to apply delta-sigma modulation to the filtered analog signal using at least one quantization bit, and output a digitized bit stream that substantially follows the amplitude of the received time domain analog signal.

Abstract: A dynamic capacitor circuit having a first passive capacitor, a second passive capacitor, a first terminal of the first passive capacitor and a first terminal of the second passive capacitor connected together to receive an input signal through a resistor. The input signal includes a noise signal component. An alternating current (AC) coupled inverting amplifier has an input connecting a second terminal of the second passive capacitor, the second capacitor coupling the input signal to the AC coupled inverting amplifier input. A conductive path couples an output of the AC coupled inverting amplifier to a second terminal of the first passive capacitor to balance out any noise signal component of the input AC signal at the connection. The dynamic capacitor achieves an amount of noise reduction in a reduced space without applying deep trench capacitors (DTCAP) where the DTCAP is a capacitance formed in a plane perpendicular to the substrate.

Abstract: A digitally controlled voltage controlled oscillator comprising an Nbit digital to analogue convertor arranged to receive a frequency change demand signal as a digital Nbit word, and having an output provided via an integrator to a voltage controlled oscillator configured to provide a frequency output.

Abstract: A data driver includes a first and second data voltage generator and a third data voltage generator. The first and second data voltage generator generates a first data voltage corresponding to a first grayscale value and a second data voltage corresponding to a second grayscale value lower than the first grayscale value based on a reference voltage. The third data voltage generator generates a third data voltage corresponding to a third grayscale value lower than the second grayscale value based on a voltage level difference between the first data voltage and the second data voltage.

Abstract: Described herein are apparatus and methods for realization of time interleaved digital-to-analog converters (DACs) by detecting and aligning phase mismatches. In an implementation, a N-time interleaved DAC includes N DACs and N replica DACs, where a first set of N/2 DACs operate at a clock A and a second set of N/2 DACs operate at a clock B, and where N is at least two. The phase detector generates a phase detection output by comparing outputs of the first and second set of N/2 replica DACs with a multiplexor (MUX) clock, where the MUX clock is a multiple of a frequency of the clock A or the clock B. The clock A and the clock B are aligned with the MUX clock by advancing a phase of the clock A and the clock B until the phase detection output achieves a zero crossing.

Abstract: Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

Abstract: A voltage-mode digital-to-analog converter (DAC) includes input circuitry and an array of output impedance units disposed in parallel. The input circuitry receives a digital word of N bits. A selectable number of the output impedance units are activated to produce a desired aggregate output impedance. The selectable number is free to be a number different than N.

Abstract: An input system includes an input pen for interfacing with a touchscreen of a display panel. The input pen includes a conductive tip. A switching unit of the pen connects the conductive tip to a receiving unit and a driving unit. The receiving unit receives touchscreen driving signals from the touchscreen through the conductive tip. The driving unit generates pen driving signals transferred to the touchscreen through the conductive tip. The input pen also include a signal processing unit to calibrate timing of the pen driving signal by synchronizing the pen driving signal with the touchscreen driving signal. To enable touch detection, the conductive tip is positioned to contact or approach the touchscreen, the touchscreen driving signal is received from the touchscreen via the conductive tip. The pen driving signal is generated and transferred to the touchscreen via the conductive tip.

Abstract: A circuit for digital-to-analog conversion using a plurality of 3-level cells includes a circuit for digital-to-analog conversion using a plurality of 3-level cells mutually independently providing positive electricity, providing negative electricity, or floating. The circuit including a preprocess circuit and a shift circuit. The preprocess circuit is configured to receive thermometer code data generated from signed binary data and generate a shift count for shifting a cell pointer pointing to one of the plurality of 3-level cells for dynamic element matching (DEM) from the thermometer code data. The shift circuit is configured to store the cell pointer and shift the stored cell pointer according to the shift count. The shifted cell pointer is shifted in proportion to an absolute value of the binary data in a direction depending on a sign of the binary data.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) and a method of operating the SAR ADC are provided. The SAR ADC converts an analog input signal into a digital code and includes a switch-capacitor digital-to-analog converter (DAC), and the switch-capacitor DAC includes multiple capacitors. The method includes the steps of: switching terminal voltage(s) of at least one target capacitor among the capacitors according to a data in a sampling phase; sampling the analog input signal in the sampling phase; switching the terminal voltage(s) of the at least one target capacitor after the sampling phase; comparing the outputs of the switch-capacitor DAC to obtain multiple comparison results that constitute the digital code; and switching the terminal voltages of a part of the capacitors according to the comparison results.

Abstract: Adaptive toggle number compensation techniques for reducing data dependent supply noise in DACs are disclosed. Various embodiments are based on setting a certain target toggle number for a plurality of DAC units used to convert at least a portion of a digital data sample and then applying various adaptive techniques to try to achieve the target toggle number in converting the data sample from digital to analog domain. Adaptive toggle number compensation techniques described herein try to reduce data dependent supply noise by deliberately limiting, to a certain target number, the number of DAC units that undergo a switch from the digital input of 1 to 0 or from 0 to 1 in converting a digital data sample. Compared to the conventional dummy signal generation approach, such adaptive toggle number compensation techniques may provide significant savings in terms of power consumption of a DAC.

Abstract: A solid-state imaging apparatus includes a pixel array, a column processor, and a test signal generating circuit that generates a first digital signal for testing purposes. The test signal generating circuit generates the first digital signal within one horizontal scanning period. The column processor converts a first analog signal, that is converted from the first digital signal, to a second digital signal within the one horizontal scanning period.

Abstract: An analog-to-digital converter (ADC) is provided. The ADC may include an input terminal configured to receive input signals, a digital-to-analog converter (DAC), a first switch configured to control a connection between the DAC and the input terminal, a comparator, a second switch configured to control a connection between the DAC and the comparator, and a controller configured to control the first switch, the second switch, the DAC and the comparator.

Abstract: The n-bit decoder circuit includes 2n base circuits each outputting, as the output signal OA, ‘0’, ‘1’ or the input signal IA depending on setting of selection signals S<1:0>; and the (n?1)-bit decoder circuit. The (n?1)-bit decoder circuit includes 2(n-1) base circuits and an (n?2)-bit decoder circuit in cases of n?3, and includes the 1-bit decoder circuit in cases of n=2. The 1-bit decoder circuit outputs ‘00’ in cases of the binary input BIN<0>=‘0’ and outputs ‘01’ in cases of the binary input BIN<0>=‘1’ as thermometer outputs THM(1)<1:0>.

Abstract: A method for simulating and optimizing a digital to analog converter is disclosed. The method may include receiving a plurality of digital words. The method may also include determining an effective number of bits, a respective amplitude and a first amplitude correction amount for each digital word. Further, the first amplitude correction amount may be applied to each respective amplitude to generate respective first corrected amplitudes. A timing uncertainty may be determined which may be used to determine a second amplitude correction for each digital word. The second amplitude correction may be applied to each of the respective first corrected amplitudes to generate respective second corrected amplitudes. Next, a representation of an analog signal may be generated based in part on the second corrected amplitudes. Finally, a filter may be applied to the representation of the analog signal and then the representation of the analog signal is outputted.

Abstract: A multi-path dual-switch DAC refers to implementing multiple paths in a switch driver and only two switches in a DAC stack of a DAC unit. In addition to multiple paths configured to improve the driving ability of the input signals, the switch driver of a multi-path dual-switch DAC unit includes two or more logic gates configured to act as multiplexers combining some of the output signals from different paths. The use of such logic gates enables using only two switches in the DAC stack unit to receive the data. Furthermore, optionally, additional logic gates may be used to combine some other output signals from different paths to generate dummy signals, thus providing internal dummy logic. The multi-path dual-switch DACs described herein may advantageously use half-clock rate and reduce or eliminate supply modulation issues, while also reducing power consumption and improving linearity compared to traditional DAC architectures.

Abstract: Local oscillator (LO) leakage and Image are common and undesirable effects in typical transmitters. Typically, fairly complex hardware and algorithms are used to calibrate and reduce these impairments. A single transistor that draws essentially no dc current and occupies a very small area detects the LO leakage and Image signals. The single transistor operating as a square-law device is used to mix the signals at the input and output ports of a power amplifier. The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.

Abstract: A digital-to-analog conversion device and a compensation circuit are provided. A digital-to-analog conversion device includes an R2R digital-to-analog converter and a compensation circuit. The R2R digital-to-analog converter is configured to receive a digital code with a plurality of bits and receive a reference voltage, and convert the digital code into an analog output signal according to the reference voltage. The compensation circuit is configured to receive the digital code, decode the digital code to generate a compensation code with a plurality of bits, and compensate the current value of the reference current according to the compensation code to generate a compensated reference current. The compensated reference current has a constant current value corresponding to different digital codes to make the reference voltage constant.

Abstract: An electronic device includes an array of image pixels, with the array of image pixels having inputs coupled to control lines and outputs coupled to output lines, and at least one array of dummy pixels, with the at least one array of dummy pixels having inputs coupled to the control lines. Each dummy pixel of the at least one array of dummy pixels is configured to provide a certain output signal in an absence of a fault with at least one of the control lines or of a fault with at least one of the output lines, such that a lack of output of the certain output signal by one or more of the dummy pixels of the at least one array of dummy pixels indicates the fault.

Abstract: A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.

Abstract: A system and computer-implemented method for improving controlling the operation of an alternating current electric motor using programmable multiplexed tap input logic. Programmed bit patterns and corresponding tap numbers are stored in a look-up table in a non-volatile electronic read-write memory element. Input channels are monitored for tap input signals, and an input bit pattern is formed based on the tap input signals. The input bit pattern is compared to the programmed bit patterns, and if the input bit pattern matches a particular programmed bit pattern, then a control signal is transmitted to activate the particular tap number which corresponds to the particular programmed bit pattern, thereby controlling the operation of the motor. If there is no active tap, then the motor is turned off. The programmed bit patterns and/or the corresponding tap numbers may be changed by writing to the look-up table in the non-volatile electronic read-write memory element.

Abstract: Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.

Abstract: Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.

Abstract: Various background calibration techniques to calibrate inter-stage gain, e.g., in pipelined ADCs, are described to allow open loop amplifier circuits to be used as residue amplifiers for better power efficiency. Using various techniques, a well-controlled perturbation can be injected between two conversions and the actual perturbation after a residue amplifier can be measured. By comparing the actual measurement against an expected value, the gain information of the residue amplifier can be estimated and then calibration can be applied.

Abstract: The disclosure relates to data driver and organic light emitting display device. The data driver includes: an input unit configured to receive an input data; a compensation data generator configured to generate a compensation data by applying a compensation value to the input data; a converter unit configured to convert the input data into an image data voltage and to convert the compensation data into a compensation data voltage; and an output unit configured to separately output the image data voltage and the compensation data voltage to a data line of the organic light emitting display.

Abstract: Measurement apparatuses and methods are described. A measurement input is coupled with a first terminal of a capacitance via a first switch, and a reference voltage is coupled with the first terminal of the capacitance via a second switch. A measurement circuit is coupled to a second terminal of said capacitance.

Abstract: Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.

Abstract: A display driver includes a first digital-to-analog (D/A) converter circuit configured to convert upper-bit data of display data into a gradation voltage corresponding to the upper-bit data, a second digital-to-analog (D/A) converter circuit configured to output a reference voltage that is varied in accordance with lower-bit data of the display data, and an inverting amplifier circuit configured to amplify the gradation voltage with reference to the reference voltage and to drive a data line of an electro-optical panel.

Abstract: A segmented resistor string type digital to analog converter comprises: a most significant bit (MSB) resistor string (104) comprising a high level resistor string, an intermediate level resistor string and a ground level resistor string; a decoding circuit (101), configured to decode an n-bit code of the MSB resistor string (104) and output 2n decoded codes; a logic sequential generation circuit (102), connected to the decoding circuit (101) and configured to perform a logic operation on a middle-position code among the 2n decoded codes and a refresh clock signal in non-overlapping sequences, and output two groups of control signals with completely complementary high level durations; a control signal bootstrap circuit (103), connected to the logic sequential generation circuit (102) and configured to perform bootstrap processing on the control signal, and increase the high level of the control signal to a sum of a power supply voltage and a threshold voltage; and a first switch group (106), connected to the c

Abstract: A direct digital synthesizer (DDS) is controlled by a suitably configured programmable logic device (PLD). The DDS includes a digital analog converter (DAC), and a coupled driver/buffer configured to drive relatively high capacitive loads with substantially rail to rail sinusoidal driver output signals and with little to no waveform distortion. The DAC includes a PMOS and NMOS DACs, and a switch configured to select the PMOS DAC for negative portions and the NMOS DAC for positive portions of an output analog signal generated by the DAC. The driver includes a pair of input differential amplifiers, PMOS and NMOS structures, which may be variable, and a pair of variable current sources. The PLD controls variable elements of the DDS to adjust the achievable positive and negative slew rates of the DDS, independently of one another, to reduce or eliminate risk of signal distortion while maintaining substantially stable rail to rail output.

Abstract: A pixel driving circuit for a display apparatus. The pixel driving circuit may include a first gate line, a second gate line, a data line, a first thin-film transistor, and a second thin-film transistor. A gate of the first thin-film transistor may be coupled to the first gate line. A source of the first thin-film transistor may be coupled to the data line. A drain of the first thin-film transistor may be coupled to a source of the second thin-film transistor. A gate of the second thin-film transistor may be coupled to the second gate line. A drain of the second thin-film transistor may be coupled to a pixel electrode.

Abstract: An electronic circuit providing a linear keypad and an apparatus comprising such electronic circuit are provided. Methods for detecting that a button of a linear keypad is being pressed and for determining which button is being pressed are also provided. A method for calibrating an apparatus comprising a linear keypad to enable the subsequent determination by the apparatus of which button of the linear keypad is being pressed is also provided.

Abstract: A method for reducing data-dependent loading on a voltage reference pre-charges a capacitor of the capacitive digital-to-analog converter to configure the capacitor in a pre-charged state during a first interval. The method selectively discharges the capacitor from the pre-charged state according to a value of an input digital signal to configure the capacitor in a selectively discharged state during a second interval. The method holds an output node of the capacitive digital-to-analog converter at a reset voltage level during the first interval and the second interval. The output node is coupled to a first terminal of the capacitor. The method discharges any remaining charge on the capacitor and providing an output voltage signal to an output node of the capacitive digital-to-analog converter according to the selectively discharged state during a third interval. The output voltage signal has a voltage level corresponding to a value of the input digital signal.

Abstract: An ADC is disclosed. The ADC includes a SAR logic circuit, a DAC, a comparator, and a voltage generator. The voltage generator includes a first switch connected to the comparator configured to selectively connect a second input terminal of the comparator to a reference voltage, a capacitor connected to the second input terminal of the comparator, and a second switch connected to the capacitor and selectively connected to either of a ground voltage and the reference voltage. The second switch is configured to selectively connect the capacitor to either of the ground voltage and the reference voltage, and the SAR logic circuit is further configured to receive the comparator output voltage, and to generate a digital input word for the DAC based on one or more comparator output voltages received from the comparator.