Abstract: Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

Abstract: A digital-to-analog converter for converting digital values to an analog output signal includes a first converter section and a second converter section operating at different conversion rates. A first analog signal provided by the first converter section and a second analog signal provided by the second converter section are combined to obtain the analog output signal. The concept may be used in fields of DAC applications where the sample rate is much higher than the signal bandwidth. The limited signal bandwidth means that the maximum change between two neighboring samples is a small fraction of the whole DAC range. The first converter section may cover a large range of values, whereas for the second converter section a relatively small range of values may be sufficient.

Abstract: Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.

Abstract: Some examples relate to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and an array of cells. Respective cells in the array comprise respective capacitors. The DAC also includes a control circuit configured to, based on the multi-bit digital input signal, selectively induce one or more corresponding capacitors to discharge current to an output terminal of the DAC.

Abstract: A D/A conversion circuit includes: current generation circuits each including a constant current source configured to generate a current, a first MOSFET connected to the constant current source and configured to control a supply destination of the current, a first gate control section configured to exclusively supply a first voltage and a second voltage to a gate of the first MOSFET, and a first discharge switch connected to the first gate control section and the gate of the first MOSFET, controlled to be turned on at the same time as the first gate control section supplies the second voltage and controlled to be turned off before the first gate control section supplies the first voltage; a first current addition line; a discharge line; a first resistor connected to the first current addition line; and a voltage source configured to supply the second voltage to the first gate control sections.

Abstract: A digital to analog converter (DAC) includes: first and second nodes; a first switching device; a second switching device; and a switch control module. The switch control module selectively configures the first and second switching devices such that: in a first configuration, the first switching device connects a first current to the first node and the second switching device connects a second current to the second node; in a second configuration, the first switching device connects the first current to the second node and the second switching device connects the second current to the first node; and in a third configuration, the first and second switching devices disconnect the first current and the second current from the first and second nodes.

Abstract: The invention relates to digital-to-analog converters for converting current. The converter includes a pair of differential branches with two transistors controlled by a digital register activated at a clock frequency, and two resistive loads receiving the currents of the differential branches to produce a differential electrical signal representing the analog result of the conversion. The converter includes a dual switching circuit for the currents of the differential branches: a first switching circuit enables the transmission of the currents of the differential branches toward the loads for 70% to 95% of the clock period and shunts these currents outside the loads for the rest of the time; a second switching circuit alternately and symmetrically makes a direct link followed by a cross link between the differential branches and the loads.

Abstract: Various embodiments of the invention provide for cancellation of a residue amplifier output charging current at the reference voltage source of the reference buffer thereby preventing the charging current from altering the effective reference voltage of a reference buffer. In certain embodiments, current cancellation is accomplished by subtracting a current of the same magnitude.

Abstract: An example digital-to-analog converter includes a reference scaling circuit receiving a first reference current and generating a second reference current. A first plurality of current sources is coupled to a summing node with a current of a first one of the first plurality of current sources proportional to the first reference current. A current of a second one of the first plurality of current sources is substantially equal to twice the current of the first one of the first plurality of current sources. A second plurality of current sources is coupled to the summing node. A current of a first one of the second plurality of current sources is proportional to the second reference current. A current of a second one of the second plurality of current sources is substantially equal to twice the current of the first one of the second plurality of current sources.

Abstract: According to some embodiments, a digital to analog converter comprises an array of input data streams. An array of differential MOS switches are all biased by a common tail current source. A data stream combiner combines and selects at each clock cycle the correct bit. Only one transistor from the switches conducts current at any time. The duration during which a switch conducts current is independent upon the fronts of the bits from the input data streams, thus rendering the switching code independent.

Abstract: A digital-to-analog (D/A) converter includes D/A conversion circuits and an amplifier circuit coupled between the D/A conversion circuits. Each D/A conversion circuit includes an R-2R ladder type resistor network, first transistors coupled between the resistor network and a first wiring at a first voltage level, and second transistors coupled between the resistor network and a second wiring at a second voltage level. The sizes of the first transistors are set at a ratio of powers of 2. The sizes of second transistors are set at a ratio of powers of 2. The second transistors are respectively turned on and off complementarily to the first transistors according to the digital input signal.

Abstract: A digital-analog converter circuit includes sampling capacitive elements (111, 112, . . . , 11N) of which one ends are to be electrically connected to and disconnected from input terminals (D1, D2, . . . , DN), to which digital signals are input, via a switch unit (SWu10), an operational amplifier (501), a switch (301) capable of electrically connecting and disconnecting the other ends of the sampling capacitive elements (111, 112, . . . , 11N) and an inverting input terminal of the operational amplifier (501), and a switch unit (SWu40) that is disposed between nodes between the switch unit (SWu10) and the sampling capacitive elements (111, 112, . . . , 11N) and the output terminal of the operational amplifier (501) and capable of connecting and disconnecting them. An on-resistance value of a MOS transistor included in the switch (301) is set to be larger than an on-resistance value of a MOS transistor included in the switch unit (SWu40).

Abstract: Embodiments may comprise logic such as hardware and/or code for high-speed digital-to-analog conversion of signals. Many embodiments comprise a demultiplexer to distribute sets of bits to digital-to-analog converters, the digital-to-analog converters to receive the sets of bits and the operate concurrently to convert the sets of bits from digital representations of signal segments to output analog signal segments, and an interleaver to interleave the analog signal segments from each of digital-to-analog converters in the sequence to generate an analog signal. In many embodiments, the interleaver is adapted to interleave the analog signal segments by latching magnitudes of each of the analog signal segments to an interleaved output near ends of clock cycles to attenuate non-linearities in the magnitudes of each of the analog signal segments when the magnitudes are output.

Abstract: Provided first and second reference voltage set wherein the first reference voltage set includes a part or all of reference voltages of the second reference voltage set, and a decoder including first and second sub-decoder sections that select Q reference voltages from first and second reference voltage sets according to upper bits of the input digital signal and transfer the so selected reference voltages to the first to Qth nodes, and third and fourth sub-decoder sections that select first and second voltages from the Q reference voltages transferred to the first to Qth nodes according to lower bits of the input digital signal and transfer the so selected voltages to the first to Pth nodes. The first and third sub-decoder sections are made up of first conductivity type transistors, while the second and fourth sub-decoder sections are made up of second conductivity type transistors.

Abstract: An apparatus and method for digital-to-analog conversion. A digital-to-analog converter includes a sampler for resampling a digital signal and a DAC array. The DAC array includes a sequencer, a unit element activator, and an array of one-bit DACs (unit elements). The unit elements are activated in a cyclical sequence, based on the resampled digital signal. Unit elements in the sequence may be skipped, based on a disruption probability. The disruption probability may be determined randomly, or pseudo-randomly. Output signals of the unit elements are summed or averaged to form an analog signal. The converter may include a filter to filter the analog signal.

Abstract: A multi-rate sigma delta digital-to-analog converter may include a signal input and a signal output, and multiple modulators. A first of the modulator may convert a digital input signal on the signal input to an analog output signal on the signal output. Subsequent of the multiple modulators may shape and cancel quantization noise received from a proceeding modulator. One of the modulators may operate at a higher frequency than does another of the multiple modulation loops.

Abstract: A digital-to-analog converter (DAC) includes, in a segment of the DAC, a first switch and a second switch. The first switch includes a first pair of transistors having a first set of inputs and has a first output connected to an output of the DAC. The second switch includes second and third pairs of transistors having second and third sets of inputs, respectively, and has a second output that is connected to the output of the DAC. A driver module generates control signals to drive the first, second, and third sets of inputs based on data received by the DAC for conversion from digital to analog format at a conversion rate determined by a clock. The control signals toggle one of the first and second switches during each cycle of the clock.

Abstract: An integrated circuit device can include a plurality of analog blocks, including a plurality of programmable analog blocks configurable to provide different analog functions in response to configuration data, at least one programmable analog block including a programmable analog routing coupled to a plurality of external connections to the integrated circuit device; and a plurality of programmable digital blocks, at least one programmable digital block configurable into an analog block control circuit that configures the programmable analog routing.

Abstract: A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an NMOS and a PMOS switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second NMOS or PMOS transistor, a first or second resistor, and the other pair of transistors. The first and second resistors can have substantially equal resistance values. A ratio of width-to-length ratios of the second NMOS to PMOS transistors can be substantially equal to such a ratio of the switch circuit NMOS to PMOS transistors.

Abstract: An analog-to-digital converting circuit includes a first comparison circuit configured to compare a first analog signal associated with a first digital signal with an analog input signal and output a first selection signal based on a result of the comparison, a second comparison circuit configured to compare a second analog signal associated with a second digital signal with the analog input signal and output a second selection signal based on a result of the comparison, and a selection circuit configured to generate intermediate digital signals associated with the first digital signal and output one of the intermediate digital signals as the first digital signal and another of the intermediate digital signals as the second digital signal, based on the first selection signal and the second selection signal.

Abstract: According to an embodiment, a semiconductor circuit includes a substrate, a tunnel oxide film, a charge storage film, a blocking layer, and plural nodes. The substrate is made of a semiconductor in which two diffusion layers each serving as either a source or a drain are formed. The tunnel oxide film is formed on a region of the substrate between the diffusion layers. The charge storage film is formed on the tunnel oxide layer and stores charge. The blocking layer is formed between the charge storage film and a gate electrode and has layers of a first oxide film, a nitride film and a second oxide film to have a thickness of 5 nm or larger but 15 nm or smaller. The nodes allow external application of voltages so that the source and the drain are reversed and allow detection a gate voltage, a drain current and a substrate current.

Abstract: A multiplying analog-to-digital converter (“MDAC”) that reduces the power consumption of the MDAC by at least 2.3 times by improving the feedback factor. The amplifier may include a feed forward approach in which the input capacitor (also referred to as “sampling capacitor”) is buffered by a common gate amplifier to improve bandwidth by removing input and parasitic capacitance terms from the global feedback loss. THe amplifier may also use an alternate form of local compensation, for example, cascode compensation. The amplifier may also further include an alternate way to reduce parasitic capacitance with a buffer.

Abstract: A sample and hold circuit and the method thereof are disclosed. The sample and hold circuit may be applied in voltage regulators or other circuits. The sample and hold circuit comprises: an input terminal configured to receive an input signal; an output terminal configured to provide an output signal; a control circuit configured to receive the input signal and the output signal, and wherein based on the input signal and the output signal, the control circuit generates a digital signal, and wherein the digital signal increases when the output signal is lower than the input signal, and maintains when the output signal is larger than or equal to the input signal; a digital-to-analog converter (DAC) configured to convert the digital signal to the output signal.

Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b?1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.

Abstract: An RF-DAC cell is configured to generate an RF output signal based on a baseband signal, a first signal and a second signal. The first signal has a first duty cycle and toggles between first predefined amplitude values, and the second signal has a second duty cycle smaller than the first duty cycle and toggles between second predefined amplitude values.

Abstract: A driving circuit includes a plurality of reference voltage lines and a digital to analog converter. The reference voltage lines are configured for respectively transmitting different grayscale reference voltages, in which the grayscale reference voltages are divided into at least two groups, and the wire diameter/wire width of at least one reference voltage line among the reference voltage lines of a first voltage group among the at least two groups is different from the wire diameters/wire widths of the reference voltage lines of a second voltage group among the at least two groups. The digital to analog converter is coupled to the reference voltage lines to receive the grayscale reference voltages and is for converting a digital signal into a grayscale voltage according to the grayscale reference voltages.

Abstract: A modulator device for converting digital data into modulation of an optical signal includes an electronic input for receiving an input data word of N bits and an electrically controllable modulator for modulating the intensity of an optical signal, the modulator including M actuating electrodes where M?N. An electrode actuating device, most preferably a digital-to-digital converter, operates actuating electrodes so that at least one electrode is actuated as a function of values of more than one bit of the input data word. According to an alternative, or supplementary, aspect of the invention, the set of electrodes includes at least one electrode having an effective area which is not interrelated to others of the set by factors of two. In one preferred implementation, a Mach-Zehnder modulator also provides phase modulation to give QAM functionality. Another implementation employs a semiconductor laser.

Abstract: A processor and a circuit implementing a continuous-time deglitching technique for a digital-to-analog converter are disclosed. The circuit includes a digital-to-analog converter having a differential current output, an operational amplifier having an inverting input coupled to a first output of the differential current output and a non-inverting input coupled to a second output of the differential current output, and a transistor coupled to the second output and the output of the operational amplifier. The operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output.

Abstract: A system for converting a digital signal to an analog signal, the digital signal having a center frequency, includes: a multi-Nyquist DAC; a clock; and a controller configured to: control the clock to generate a clock signal such that the center frequency of the digital signal is an integer multiple of half the frequency of the clock signal, the clock being configured to supply the clock signal to the multi-Nyquist DAC and to the controller; and supply the digital signal to the multi-Nyquist DAC to generate an output signal.

Abstract: An audio downlink path is provided including a Dynamic Range Boost (DRB), a modified Digital-to-Analog Converter (DAC), and a modified audio driver gain control to produce a very high Dynamic Range (DR) while maintaining a limited scale and complexity of the components within the audio downlink path.

Abstract: Reference voltages of a reference voltage ensemble are classed into first to (z×S+1)th reference voltage groups, where S is a power of 2 inclusive of 1 and z is a power of 2 plus 1. A decoder includes first to (z×S+1)th sub-decoders provided in association with the first to (z×S+1)th reference voltage groups, and a (z×S+1) input and 2 output type sub-decoder. The first to (z×S+1)th sub-decoders select, from the reference voltage of the first to the (z×S+1)th reference voltage groups, those reference voltages allocated to columns in a two-dimensional array of the reference voltages associated with the values of a first bit group of an input digital signal. The (z×S+1) input and 2 output sub-decoder receives outputs of the first to (z×S+1)th sub-decoders to select the first and second voltages from the reference voltages selected by the first to (z×S+1)th sub-decoders in response to the value of a second bit group of the input digital signal.

Abstract: A processor and a circuit implementing a continuous-time deglitching technique for a digital-to-analog converter are disclosed. The circuit includes a digital-to-analog converter having a differential current output, an operational amplifier having an inverting input coupled to a first output of the differential current output and a non-inverting input coupled to a second output of the differential current output, and a transistor coupled to the second output and the output of the operational amplifier. The operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output.

Abstract: A digital to analog converter including a current steering source and a master replica bias network. The current steering source includes a data current source providing a source current to a source node, a switch circuit operative to steer the source current to a selected one of first and second control nodes based on a data bit, a buffer circuit that buffers the source current between the first control node and a first current output node or between the second control node and a second current output node, and an activation current source provides activation current to the buffer circuit via the first and second control nodes. The master replica bias network replicates biasing of the buffer circuit relative to a replica control node and drives the buffer circuit to maintain the first control node, the second control node and the replica control node at a common master control voltage.

Abstract: A continuous time input stage including a first digital-to-analog converter (DAC) including a first DAC code input, a second DAC including a second DAC code input, a first set of switches coupled to the output of the first DAC, a second set of switches coupled to the output of the second DAC, and an amplifier configured to receive the output of either the first DAC or the second DAC.

Abstract: A method and device for testing a digital-to-analog converter is provided. The method may include configuring a decoder to address an individual unit cell of a plurality of unit cells of a digital-to-analog converter. The configured decoder may select a particular unit cell of the plurality of unit cells for testing. The selected unit cell may have digital and analog circuitry. A bias current of the selected unit cell may be increased. The increased bias current of the selected unit cell may be greater during the testing than during normal operation. A test logic signal may be applied to the selected unit cell. In response to the test logic signal, an output signal may be output from the selected unit cell logic circuitry of the digital-to-analog converter. A device may include logic circuitry configured to select an individual unit cell for testing and a current generating circuitry.

Abstract: A method to reduce the integral non-linearity (INL) of a digital-to-analog converter (DAC) and a DAC implementing said method are disclosed. The method in this invention is a pseudo dynamic element matching (PDEM) method. Compared with a prior art, the method of this invention provides a better performance in glitch. Compared with another prior art, the method of this invention also guarantees that DEM will not fail even if the input digital code remains constant.

Abstract: A pipeline analog-to-digital converter (ADC) includes a first conversion stage of the pipeline ADC that receives an input signal and that comprises, in a first signal path, a first ADC that converts the input signal, a first digital-to-analog converter (DAC) that converts an output of the first ADC, a first subtractor that subtracts an output of the first DAC from the input signal, and a first amplifier that amplifies an output of the first subtractor and generates a first residue of the first conversion stage; and in a second signal path, a second DAC that converts the output of the first ADC, a second subtractor that subtracts an output of the second DAC from the input signal, and a second amplifier that amplifies an output of the second subtractor and generates a second residue of the first conversion stage. A control module selectively enables and disables the second path.

Abstract: Embodiments of a digital-to-analog conversion system that utilizes a specialized clock signal to reshape an analog impulse response of a digital-to-analog converter (DAC) are disclosed. Preferably, a shape of the specialized clock signal is such that Nyquist images resulting from digital-to-analog conversion are controlled in a desired manner. In one embodiment, the digital-to-analog conversion system includes a DAC that converts a digital input signal into an analog output signal. A specialized clock signal is applied to the analog output signal of the DAC such that an analog impulse response of the DAC is reshaped according to a shape of the specialized clock signal, thereby providing a modified analog output signal. The specialized clock signal reshapes the analog impulse response of the DAC such that Nyquist images resulting from digital-to-analog conversion are controlled in a desired manner.

Abstract: In a DAC device, a distortion correction function g1(x) of a harmonic obtained from a result of a frequency analysis on an analog output signal of a DAC circuit is obtained. A correction value is determined based on the correction function g1(x) in accordance with an input digital signal, and is previously stored in a memory. A nonlinear correction circuit reads a corresponding correction value from the memory in accordance with the value of a digital signal output from a digital filter, and transmits the correction value to a subtractor. The subtractor subtracts the correction value from the digital signal output from the digital filter.

Abstract: A system and method is disclosed for a digital to analog converter which includes an interpolation filter to up-sample a digital signal, a noise shaping modulator to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to a reconstruction filter which outputs the analog signal. The hybrid finite impulse response filter/digital to analog converter uses N-taps implemented digitally and N-tap weights implemented in analog using switched capacitors.

Abstract: A method and apparatus for interleaving high-speed, delta-sigma based over-sampled DACs. A delta-sigma modulator is decomposed into a parallel poly-phase block-filter running at a lower rate. The generated parallel digital data is then fed directly to the analog DAC output stage where it is directly combined to form the full-rate signal using a 1-hot-of-N output stage. By using a poly-phase implementation, the complexity of the high-speed parallel digital-analog timing interface is simplified, along with the timing requirements of the delta-sigma modulator which normally would have to run at the full-oversampled rate. The 1-hot-of-N signal encoding is directly generated from the parallel delta-sigma modulator, and efficiently encodes the data in such a way to minimize signal-dependent supply noise. The architecture disclosed is advantageous for the practical implementation of high-speed over-sampled DACs, such as those used in stringent wireless applications.

Abstract: Highly power efficient transmitter output stage designs are provided. In an embodiment, the probability density function (PDF) of an input signal is divided into a plurality of regions, and samples of the input signal are processed depending on the region of the PDF within which they fail. The PDF can be divided between an inner region corresponding to samples of the input signal that are within a predetermined amplitude range, and outer regions corresponding to samples of the input signal that are outside of the predetermined amplitude range. Samples of the input signal that fall in the inner region are processed by a class A biased amplifier and samples of the input signal that fall in the outer regions are processed by a class B biased amplifier. Output stage designs according to embodiments can be implemented as power amplifiers or power digital-to-analog converters (DACs).

Abstract: A delta-sigma modulation apparatus and a dynamic element-matching circuit thereof are disclosed. The dynamic element-matching circuit includes a data aligner, a logic operation circuit, and a delayer. The data aligner receives an input matching data and a pointer signal and shifts the input matching data according to the pointer signal to generate an output matching data. The logic operation circuit receives the output matching data and performs a logic operation on the output matching data to generate a preceding pointer signal. The delayer receives the preceding pointer signal and delays the preceding pointer signal according to a sample clock pulse to generate the pointer signal.

Abstract: A system and method is disclosed for a digital input Class D amplifier which includes an interpolation filter to up-sample a digital signal, a noise shaping modulator to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to an analog input Class D amplifier with digital pulse width modulation control loop. The hybrid finite impulse response filter/digital to analog converter uses N-taps implemented digitally and N-tap weights implemented in analog using resistors.

Abstract: A method and apparatus for performing modulation of a radio frequency, RF, signal within a digital-to-RF converter. The method includes determining a desired digital control word switching frequency value based at least partly on at least one parameter corresponding to a bandwidth of the RF signal to be modulated and at least one from a group including: at least one parameter corresponding to an RF channel frequency of the RF signal to be modulated; and at least one parameter corresponding to a power level of the RF signal to be modulated. The method further includes dynamically configuring at least one digital control module to output at least one digital control word signal in accordance with the desired digital control word switching frequency value, and performing modulation of the RF signal in accordance with the at least one digital control word signal output by the at least one digital control module.

Abstract: The disclosed device easily and precisely satisfies a requested output range, and is provided with: a ??-modulator (12) which converts a digital input signal to a pulse signal; an input comparison device (11) which compares an input value that corresponds to the digital input signal, and a pre-set threshold value; and a thinned output control unit (14) which, when the result of the comparison by the input comparison device (11) shows that the input value is less than the threshold value, reduces the output value corresponding to the input value in accordance with the size of the difference between the input value and the threshold value, and sets the output value to 0 when the input value is 0.

Abstract: A method to reduce the integral non-linearity (INL) of a digital-to-analog converter (DAC) and a DAC implementing said method are disclosed. The method in this invention is a pseudo dynamic element matching (PDEM) method. Compared with a prior art, the method of this invention provides a better performance in glitch. Compared with another prior art, the method of this invention also guarantees that DEM will not fail even if the input digital code remains constant.

Abstract: An apparatus and a method for digital-analog conversion are provided. The apparatus includes a first cell matrix for outputting a current of a signal corresponding to a number of Most Significant Bits (MSBs) of an input digital signal, a second cell matrix for outputting a current of a signal corresponding to a number of Least Significant Bits (LSBs) of the input digital signal, an amplifier for amplifying the output current of the second cell matrix at a preset amplification, and an adder for adding the output current of the first cell matrix and the output current of the amplifier.

Abstract: A digital-to-analog converter (DAC) includes, in a segment of the DAC, a first switch and a second switch. The first switch includes a first pair of transistors having a first set of inputs and has a first output connected to an output of the DAC. The second switch includes second and third pairs of transistors having second and third sets of inputs, respectively, and has a second output that is connected to the output of the DAC. A driver module generates control signals to drive the first, second, and third sets of inputs based on data received by the DAC for conversion from digital to analog format at a conversion rate determined by a clock. The control signals toggle one of the first and second switches during each cycle of the clock.

Abstract: Embodiments of the present invention may provide a multi-string DAC with leakage current cancellation. A leakage cancellation circuit may be coupled to output node(s) of the—multi-string DAC. The leakage cancellation circuit may replicate leakage current present at the coupled output node(s) and generate a corresponding complementary signal, a leakage cancellation signal. The leakage cancellation signal may be injected into the coupled output node(s) to cancel (or reduce) the net impact of the leakage current.