Abstract: Disclosed is a digital-analog converter including a current generation section, a current source transistor bias voltage keeping section, a cascade transistor group switch section, and a conversion section. The current generation section has at least one current source transistor group including a plurality of current source transistors and generates an output current based on a value of a digital input signal. The current source transistor bias voltage keeping section has a plurality of cascade transistor groups each including cascade transistors connected in series to the current source transistors and keeps bias voltages of the current source transistors constant. The cascade transistor group switch section selects one of the plurality of cascade transistor groups. The conversion section performs current-voltage conversion of the output current supplied via the selected cascade transistor group.

Abstract: Provided is a transmission circuit that includes first and second drive circuits. A first digital signal at a data rate of a predetermined period length is input to the first drive circuit. A second digital signal at the data rate of the predetermined period length shifted by ½ of the predetermined period length relative to the first digital signal is input to second drive circuit. The outputs of the first drive circuit and the second drive circuit are connected. The connected output indicates the maximum level or the minimum level when the value of the first digital signal and the value of the second digital signal are the same. The connected output indicates a level between the maximum level and the minimum level when the value of the first digital signal and the value of the second digital signal are different.

Abstract: Methods and systems for a low input voltage low impedance termination stage for current inputs may include, in a semiconductor die, generating an output current proportional to an input signal, where the output current is generated by an output stage that may include a pair of input cascode transistors and at least one pair of stacked output transistors. A source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source that is coupled to ground. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor.

Abstract: One embodiment of the present disclosure relates to a circuit. The circuit includes a digital to analog converter (DAC) configured to convert a time-varying, multi-bit digital value to a corresponding time-varying output current. The circuit also includes a mixer module downstream of the DAC and comprising a plurality of mixers. A control block is configured to selectively steer output current from the DAC to different mixers of the mixer module. Other techniques are also described.

Abstract: A system configured to receive bits of data. The bits of data include most significant bits and least significant bits. The system includes a first converter, a voltage-to-current converter, a current converter, and a current-to-voltage converter. The first converter is configured to generate input voltages. The input voltages represent the most significant bits of the bits of data. The voltage-to-current converter is configured to convert a selected one of the input voltages to a first current. The current converter is configured to, based on least significant bits of the bits of data, interpolate or divide the first current to generate a second current. The current-to-voltage converter is configured to convert the second current to an output voltage. The output voltage represents the most significant bits and the least significant bits.

Abstract: A digital to analog converter for a source driver chip of a liquid crystal display device is disclosed. The digital to analog converter comprises an output terminal for outputting an output voltage, a plurality of receiving terminals for receiving a plurality of Gamma voltages, and a plurality of transmission paths comprising a plurality of first-type transistors coupled between the plurality of receiving terminals and the output terminal, respectively, for outputting one of the plurality of Gamma voltages as the output voltage according to a digital select signal; wherein a first transmission path corresponding to a first receiving terminal receiving a first Gamma voltage closest to a middle voltage among the plurality of Gamma voltages has lower on-resistance than other transmission paths among the plurality of transmission paths when a same source-to-gate voltage is applied.

Abstract: Methods and circuits for transmitting data are disclosed. An embodiment of a method includes transmitting a predetermined number of pulses during predetermined period of time. A first predetermined number of pulses transmitted during the predetermined period of time represents a first value and a second predetermined number of pulses transmitted during the predetermined period of time represents a second value.

Abstract: A processor transmitter includes a sensor, a first signal path, a second signal path, and an output summing circuit. The sensor produces a process signal that is a function of a process parameter. The first signal path digitally compensates the process signal. The second signal path digitally filters the process signal and subjects the process signal to less delay than the first signal path. The output summing circuit sums the digitally compensated process signal from the first signal path and the digitally filtered process signal from the second signal path to produce a fast digital compensated process signal.

Abstract: An analog to digital converter including a low pass filter element, a quantizer, and a digital to analog converter provide in a feedback path. The low pass filter element is configured to filter an analog input signal. The quantizer is configured to receive an analog output signal that is based on the filtered analog input signal and convert the analog output signal to a digital output signal. The digital to analog converter is configured to generate an analog feedback signal based on the digital output signal and selectively inject or absorb current associated with the feedback path to reduce noise associated with the digital to analog converter. The analog feedback signal is combined with the analog input signal at an input of the low pass filter element.

Abstract: A solid-state image sensing device according to the invention which can reduce an instantaneous current occurring in transferring image digital signals from analog-digital converters to registers to reduce noise sneaking into the analog-digital converters and a pixel array includes a pixel array, a vertical scanning circuit, a plurality of column ADCs, a plurality of registers, and control signal generation units. The control signal generation units are provided for respective groups into which the column ADCs and the registers disposed on one side of the pixel array are divided, and generate control signals of different timings, for respective units including at least one group, of transfer of converted image digital signals to the registers from the column ADCs operating in parallel.

Abstract: A self clocking data extraction method is shown that is tolerant of timing jitter, data skew and the presence of multiple edges per data bit. The data is sampled when the following criterion are met: There is at least one edge across any track (the clock assures this criteria is met), followed by no edges in any track for a defined period of time (T), and all edge activity must occur in a period of time less than T (to keep from detecting false samples). This method enables the handling of trace data signals with poor electrical characteristics that can not be recorded by methods known in the prior art.

Abstract: Input codes are sequenced at a lower-resolution linear DAC and the output is converted to a linear current waveform. A first of two interconnected analog current multipliers multiplies the linear current by itself and by the inverse of a first constant current source to create a quadratic current output. A second current multiplier multiplies the quadratic output current by the linear current and by the inverse of a second constant current source to generate a cubic current output. The quadratic and cubic currents are subtracted from the linear current to generate an approximation of the first 180 degrees of a sine wave current. Alternate (pi to 2*pi) positive-going one-half sine waves may be polarity reversed to create a complete positive-going and negative-going sine-shaped electrical current of higher resolution than is available from a sine DAC of resolution equivalent to that of the lower-resolution linear DAC.

Abstract: Methods and systems are provided for using localized dynamic element matching (DEM) and/or dynamic noise scaling (DNS) in digital-to-analog converters (DACs). Adaptive (localized) DEM may be applied in a DAC, by selecting one or more of a plurality DAC elements in the DAC, forcing the selected one or more of the plurality of DAC elements not to switch during digital-to-analog conversions, and scrambling remaining one or more of plurality of DAC elements when generating an output of the DAC. The adaptive DEM may be applied when the DAC input is backed off from full-scale. DNS may be applied in a DAC, by adaptively selecting one or more of a plurality DAC elements in the DAC and switching off the selected one or more of the plurality DAC elements such that the selected one or more of the plurality DAC elements do not contribute to generating an output of the DAC.

Abstract: First order gradient errors are canceled with no current source splitting by placing consecutive current sources symmetrically around the center of the array. Consecutive elements that correspond to small input amplitudes (mid-scale codes) make a smaller spatial jump than those correspond to larger signal amplitudes. Both linear and second order gradients are reduced by splitting each current cell into two and placing sub-elements symmetrically with respect to the center of the array to address the linear gradient effect. To address second order gradients, current element placement follows a pattern such that consecutive element pairs are chosen with one of the pair being placed with respect to the zero error contour of the second order gradient so as to have a positive error and the second of the pair being placed so as to have a negative error resulting in reduced second order error accumulation.

Abstract: Disclosed herein are apparatus, method, and computer program product whereby a device receives an acoustic signal. In response to the received acoustic signal, the device outputs electrical signals from a first input audio transducer and a second input audio transducer. The second input audio transducer is less sensitive than the first input audio transducer.

Abstract: Techniques for performing noise cancellation/attenuation are disclosed. In one design, an apparatus includes a power supply generator having a switcher, a coupling circuit, an envelope amplifier, and a feedback circuit. The switcher generates DC and low frequency components and the envelope amplifier generates high frequency components of a supply voltage for a load, e.g., a power amplifier. The switcher receives a first supply voltage and provides a switcher output signal having switcher noise. The coupling circuit receives the switcher output signal and provides a first output signal having a first version of the switcher noise. The feedback circuit receives the switcher output signal and provides a feedback signal. The envelope amplifier receives an envelope signal and the feedback signal and provides a second output signal having a second version of the switcher noise, which is used to attenuate the first version of the switcher noise at the load.

Abstract: Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.

Abstract: A phase estimator comprising a first input terminal configured to receive a first analog input signal; a second input terminal configured to receive a second analog input signal, wherein the second analog input signal is 90° out of phase with the first analog input signal. The phase estimator is configured to provide a digital word representative of the phase of the first analog input signal and the second analog input signal. The phase estimator comprises a register configured to store N bits as a digital word a first reference signal generator, a second reference signal generator and a comparator.

Abstract: The embodiments herein describe a power converter including a controller that estimates input current of the power converter. The controller estimates the input current without explicitly sensing the input current. The estimated input current can be used in various applications such as regulating power factor and total harmonic distortion as well as estimating current required to maintain proper operation of a dimmer switch in light emitting diode lamp systems.

Abstract: A digital radio frequency memory (DRFM) comprises a plurality of time interleaved analog to digital converters (ADCs) in cooperation with a plurality of time interleaved digital to analog converters (DACs) to provide an effective sampling rate which may be greater than the clock rate of the system. A higher sampling rate at the ADC increases instantaneous bandwidth, while a higher sampling rate at the DAC improves spectral purity. The ADCs and DACs are time interleaved by supplying a clock signal to each ADC/DAC which is skewed with respect to the previous and subsequent skewed signal. In order to process the higher effective sampling rate, a pre-computation of DAC values for each high rate sample is performed by an SDAC algorithm that pipelines the calculations of the processed sample values provided to the DAC. A DAC bias correction is provided to adjust for drift in the DACs.

Abstract: A digital-to-analog conversion circuit includes first current sources weighted depending on lower-order bits of digital input signals and supplied with a first bias voltage and second current sources weighted depending on higher-order bits of the digital input signals and supplied with a second bias voltage. A reference current source circuit generates the first and second bias voltages based on a first reference current. An output circuit combines currents from the first and second current sources in accordance with the digital input signals to generate an output current, the currents from the first and second current sources being set according to the first reference current. A correction circuit changes the first reference current into a second reference current smaller than the first reference current, and adjusts the first and second bias voltages based on currents from the first and second current sources changed according to the second reference current.

Abstract: A circuit may include a plurality of primary digital-to-analog (DAC) elements for converting a digital input signal into an analog output signal. A control circuit may control each primary DAC element to switch between a first state and a second state based on the digital input signal to provide the analog output signal at an output representing the digital input signal. A plurality of corrective DAC elements may be coupled in parallel to the plurality of primary DAC elements between the control circuit and the output. The plurality of corrective DAC elements may be controlled to mitigate for intersymbol interference (ISI) due to parasitic capacitance in the primary DAC elements. The plurality of corrective DAC elements may not contribute a direct current to the analog output signal.

Abstract: A digital-to-analog (DAC) element may include a plurality of switches arranged to form two circuit branches between a current source and a first and a second outputs. The first circuit branch may include two switches defining parallel current paths between the current source and the first output terminal. The second circuit branch may include two switches defining parallel current paths between the current source and the second output terminal. A control circuit, responsive to an input signal that selects one of the circuit branches, may provide control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle and to close the other of the switches in the selected circuit branch in a second portion of the clock cycle.

Abstract: Implementations of a high gain range transmitter with variable-size mixers are described.

Abstract: Quantization noise in a fractional-N phase-locked loop (PLL) is canceled using a capacitor-based digital to analog converter (DAC). A phase error is detected between a reference signal and a feedback signal in the PLL. A charge pump circuit charges a first capacitor circuit based on the phase error to generate a phase error voltage corresponding to the phase error. The capacitor based DAC generates a quantization error correction voltage based on a digital value corresponding to the quantization error, which is then combined with the phase error voltage to cancel the quantization error.

Abstract: Embodiments of the present invention create a circuit having a digital-to-time converter with a high-frequency input for receiving a high-frequency signal, a digital input for receiving a first digital signal, and a high-frequency output for the provision of a chronologically delayed version of the HF signal. In addition, the circuit has an oscillator arrangement for the provision of the high-frequency signal, having a phase-locked loop for adjusting a frequency of the high-frequency signal. The digital-to-time converter is designed to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input.

Abstract: A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit.

Abstract: The invention relates to digital-to-analog converters for converting current. The converter includes a pair of differential branches with two transistors controlled by a digital register activated at a clock frequency, and two resistive loads receiving the currents of the differential branches to produce a differential electrical signal representing the analog result of the conversion. The converter includes a dual switching circuit for the currents of the differential branches: a first switching circuit enables the transmission of the currents of the differential branches toward the loads for 70% to 95% of the clock period and shunts these currents outside the loads for the rest of the time; a second switching circuit alternately and symmetrically makes a direct link followed by a cross link between the differential branches and the loads.

Abstract: A modulator and a method are disclosed. The modulator is for generating a band pass signal and comprises: sigma delta modulation logic operable to receive an input signal and to perform at least a 3-level quantisation of the input signal to generate an at least 3-level quantised signal; and requantisation logic operable to requantise the at least 3-level quantised signal to a 2-level quantised signal to be provided as the band pass signal. This approach improves the coding efficiency achieved compared to that possible using a 2-level sigma delta modulator, whilst also providing improved noise performance due to the inherent linearity of the 2-level quantised signal which is provided to drive the switch mode power amplifier. Accordingly, the performance of the modulator is improved by increasing its coding efficiency whilst maintaining its linearity which improves the noise performance in adjacent channels.

Abstract: A band division apparatus obtains an analog low-band signal, an analog intermediate-band signal and an analog high-band signal from a digital sound signal. In the band division apparatus, a digital filter separates the digital sound signal into a digital intermediate-band signal having the intermediate frequency band while the high frequency band and the low frequency band are attenuated, and a digital low-high-band signal having a frequency band combining the low frequency band and the high frequency band while the intermediate frequency band are attenuated. A DA converter converts the digital low-high-band signal into an analog low-high-band signal. Another DA converter converts the digital intermediate-band signal into the analog intermediate-band signal. An analog filter separates the analog low-high-band signal into the analog low-band signal and the analog high-band signal.

Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.

Abstract: A RF digital to analog converter has a first capacitor arrangement, a first common node, and a first controller. The first capacitor arrangement has multiple switchable capacitor paths arranged in parallel. Respective switchable capacitor paths have a switchable element and a capacitor coupled in series. The first common node is connected to the multiple switchable capacitor paths. The first controller receives a baseband signal having a component, and a local oscillator (LO) signal. The first controller combines the component and the LO signal to obtain a first modulation signal. The first controller controls the multiple switchable capacitor paths of the first capacitor arrangement with the first modulation signal.

Abstract: A circuit including an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a noise shaper. The noise shaper is configured to truncate the digital output and generate a noise shaper output having a lower number of bits than the digital output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC). The PWM DAC configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output.

Abstract: A delta-sigma modulator and corresponding method are disclosed. In one implementation, the delta-sigma modulator includes a multiplexer for receiving an analog input signal and a common mode signal and outputting a multiplexed signal in accordance with a selection signal; a summing circuit for receiving the multiplexed signal and an analog feedback signal and outputting an error signal; a loop filter for receiving the error signal and outputting a filtered signal; a quantizer for receiving the filtered signal and outputting a raw digital output signal; a digital-to-analog converter for receiving the raw digital output signal and outputting the analog feedback signal along with a rotated digital output signal in accordance with a phase indicator and a rotation number; and a calibration logic for receiving the rotated digital output signal and a mode indicator and outputting the selection signal, the phase indicator, the rotation number, and a calibrated digital output signal.

Abstract: The perceived sample rate at which a DAC can operate can be increased by allowing multiple DACs to process different portions of a digital signal in parallel. In this way, the outputs of multiple DACs can be combined into a single analog signal to achieve the desired speeds and resolutions of the analog output. This parallel processing can be implemented using a time-interleaving technique or a sub-band reconstruction technique. Pre-distortion can be applied to the digital input signal to compensate for degradation detected in the analog output signal. By applying pre-distortion, waveforms having high sampling rates can be efficiently generated.

Abstract: A MASH sigma-delta modulator includes: parallel integration units in M stages configured to receive N pieces of data from a previous stage, to perform integral calculation in parallel; parallel differentiation units each configured to calculate a difference between neighboring overflows of the corresponding parallel integration unit of the integration part; and a parallel-to-serial conversion part configured to parallel-to-serial convert outputs from the differentiation part, wherein the parallel integration units receive pieces of input data in parallel, the parallel integration unit in each stage and the parallel differentiation unit in each stage perform integral calculation and differential calculation in each stage in one operation clock of a frequency 1/N times a master clock frequency, and the parallel-to-serial conversion part outputs the result of the parallel-to-serial conversion in synchronization with the master clock.

Abstract: An amplifier includes a front-end gain stage and an AC-coupled push-pull output stage. The AC-coupled push-pull output stage includes a first transistor, having a source, a drain and a gate, wherein the source of the first transistor is coupled to a first voltage level; a second transistor, having a source, a drain and a gate, wherein the source of the second transistor is coupled to a second voltage level, the gate of the second transistor is coupled to the front-end gain stage, and the drain of the second transistor is coupled to the drain of the first transistor to form an output terminal of the amplifier; an AC-coupled capacitor, which is a passive two terminal electrical component coupled between the front-end gain stage and the gate of the first transistor; and a resistance component, coupling the gate of the first transistor to a bias voltage level.

Abstract: A digital-to-analog converter (DAC) comprising a first section having a first plurality of current flow paths forming binary weighted values in the DAC; and a second section connected to the first section and having a second plurality of current flow paths, wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and wherein weights of one or more of the second plurality of current flow paths are notionally equal to weights of one or more of the first plurality of current flow paths so as to provide redundancy in the first section.

Abstract: A digital to analog converter includes a first switch, a second switch, and a driver module. The first switch includes a first differential pair of transistors connected to first inputs to receive digital data for conversion to analog data based on a clock signal output by a clock, and first outputs to output the analog data. The second switch includes second and third differential pairs of transistors connected to second inputs and the first outputs. The driver module drives one of the second inputs based on the digital data and toggles the second switch during a first cycle of the clock signal if the first switch is not toggled during the first cycle of the clock signal.

Abstract: A digital-to-time converter (DTC) comprises a gate controller configured to generate a gate enable signal based on first and second digital values so that the gate enable signal has a first enable period and a second enable period for each pair of a first digital value and a second digital value. A gate conditionally passes a main clock signal to a gate output in response to the gate enable signal, the gate thus providing a gated signal at a gate output. A frequency divider generates a frequency divided signal as the output signal of the digital-to-time converter based on the gated signal. The DTC may be calibrated by a time-to-digital converter connected between an input for the main clock signal and an output of a delay element of the DTC.

Abstract: There is provided A DA converter in which the N current switch cells each include: a current source having one end connected to a first power source; and first and second switch transistors differentially operating each other, each having a control terminal receiving a digital signal, the first combining node combines a current output from the first switch transistor in each current switch cell, the second combining node combines a current output from the second switch transistor in each current switch cell, the first output impedance element has ends connected to the first combining node and a second power source, the second output impedance element has ends connected to the second combining node and the second power source, the controller controls the current source in each current switch cell to reduce variation in amount of a current flowing from the first power source.

Abstract: A digital-to-analog conversion circuit operates by selectively discharging members of a plurality of capacitors. Charging of the capacitors occurs during a reset period while digital-to-analog conversion occurs as the capacitors are discharged. Those capacitors that are discharged are selected from the plurality of capacitors based on a digital input. The analog output includes the charge discharged from the capacitors. The capacitors are optionally divided into separate capacitor banks.

Abstract: A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an NMOS and a PMOS switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second NMOS or PMOS transistor, a first or second resistor, and the other pair of transistors. The first and second resistors can have substantially equal resistance values. A ratio of width-to-length ratios of the second NMOS to PMOS transistors can be substantially equal to such a ratio of the switch circuit NMOS to PMOS transistors.

Abstract: A delta-sigma D/A converter, by which a digital valued, input signal is convertible into a binary, clock signal time discrete, output signal. By forming an average value of the output signal over a number of clock signal cycles, an analog value of the input signal can be displayed. The delta-sigma D/A converter is embodied in such a manner that, in use, it provides the output signal by serial arrangement of signal patterns of a set of signal patterns, wherein the signal patterns of the set are, in each case, binary, clock signal time discrete and extend over a signal pattern cycles total of a plurality of clock cycles. At least two signal patterns of the set have mutually different signal pattern average values, which are formed over the respective signal pattern cycles total, and all signal patterns of the set have, in each case, essentially the same number, especially exactly the same number, of edges.

Abstract: Systems and methods provide for the control of a fully-segmented digital-to-analog converter. The selected lead-most current cell of an array in the digital-to-analog converter is addressed individually using a row/column scheme and a decoder. The remaining current cells behind the lead-most current cell are enabled via a ripple enable signal that propagates backwards from the lead-most current cell. The ripple enable signal snakes through the array to enable all the current cells behind the lead-most current cell in a cell-by-cell fashion. The current cells in front of the lead-most current cell are not enabled.

Abstract: Systems and methods for providing a mechanism by which digital signals can be converted to analog signals with an efficient structure that reduces the number of filters required by providing a mechanism for cancelling images that would otherwise be generated. By adjusting three parameters in the system, a selection can be made as to whether to generate upper sidebands, lower sidebands and in which direction the envelope of the output from the system will be skewed.

Abstract: Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.

Abstract: An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available. A CMOS image sensor converts successive analog signals, representing at least a portion of an image, into successive digital signals using an analog to digital circuit block. Multiple clock cycles may be used by the circuit block to fully convert an analog signal into a corresponding digital signal. The conversion of one analog signal into a corresponding digital signal by the circuit block may be offset in time and partially overlapping with the conversion of a successive analog signal into its corresponding successive digital signal by the circuit block.