Abstract: An apparatus and method for digital-to-analog conversion. A digital-to-analog converter includes a sampler for resampling a digital signal and a DAC array. The DAC array includes a sequencer, a unit element activator, and an array of one-bit DACs (unit elements). The unit elements are activated in a cyclical sequence, based on the resampled digital signal. Unit elements in the sequence may be skipped, based on a disruption probability. The disruption probability may be determined randomly, or pseudo-randomly. Output signals of the unit elements are summed or averaged to form an analog signal. The converter may include a filter to filter the analog signal.

Abstract: Disclosed is a digital-analog converter including a current generation section, a current source transistor bias voltage keeping section, a cascade transistor group switch section, and a conversion section. The current generation section has at least one current source transistor group including a plurality of current source transistors and generates an output current based on a value of a digital input signal. The current source transistor bias voltage keeping section has a plurality of cascade transistor groups each including cascade transistors connected in series to the current source transistors and keeps bias voltages of the current source transistors constant. The cascade transistor group switch section selects one of the plurality of cascade transistor groups. The conversion section performs current-voltage conversion of the output current supplied via the selected cascade transistor group.

Abstract: A solid-state image capture device including: a pixel having a photoelectric conversion element and first to fourth switch elements; a reference-signal generator that generates a reference signal; and an analog-to-digital converter that generates a digital signal corresponding to an analog signal output by the pixel, by using a comparator having first and second input terminals. The second switch element is turned on to reset a voltage of the predetermined connection point, the fourth switch element is turned on while a connection degree of the second switch element is in an intermediate state between an on state and an off state to cause the first and second input terminals to reach a same potential, and the second switch element is not turned on and at least one of the first and third switch elements is turned on to cause the analog-to-digital converter to perform conversion into a digital signal.

Abstract: A D/A conversion circuit in accordance with the present invention, which is provided with a switch swD, allows a writing operation of a voltage (a true gradation voltage) to be performed at a higher speed by first applying a first voltage (a voltage close to the true gradation voltage), which is supplied without passing through a resistor element, to an output line and then applying a second voltage (the true gradation voltage), which is supplied via the resistor element, to the output line. Thus, the present invention can provide a D/A conversion circuit capable of writing display data to liquid crystal cells with higher precision at higher speed, and a semiconductor device utilizing such a D/A conversion circuit.

Abstract: Logic such as hardware and/or code for high-speed analog-to-digital conversion of a signal. Logic may receive an analog signal as an input to a sampling receiver. The sampling receiver may implement a successive approximation register (SAR), analog-to-digital converter (ADC) to produce the digital output. Logic may re-task a comparator of the SAR ADC during a sampling mode to generate a digital comparator output that represents a comparison of a voltage of the charge on a capacitance of the DAC against a threshold reference voltage. The digital comparator output may be applied to the input of automatic gain control (AGC) logic. The AGC logic may receive the digital comparator signal which is representative of one sample of a multiple sample, sample cycle, allowing the AGC logic to generate a gain control signal that is responsive to both total composite average and peak amplitudes.

Abstract: An envelope detector includes an input receiving a digital input signal indicative of a magnitude of a signal to be amplified by a power amplifier. A circuit is provided for generating an analog envelope signal based on the digital input signal. The envelope detector includes an output for outputting the analog envelope signal.

Abstract: Among other things, an arrangement for a digital-to-analog converter (DAC) is provided herein. In some embodiments, a metal-oxide semiconductor (MOS) array of the DAS comprises one or more cells respectively comprising one or more current sources. The current sources comprise one or more transistors having a horizontal gate layout. A switch arrangement of the DAS, to which the MOS array is connected, comprises one or more transistors having a vertical gate layout. Accordingly, in some embodiments, a DAC is provided which comprises transistors having a vertical gate layout and transistors having a horizontal gate layout.

Abstract: An RF-DAC cell is configured to generate an RF output signal based on a baseband signal, a first signal and a second signal. The first signal has a first duty cycle and toggles between first predefined amplitude values, and the second signal has a second duty cycle smaller than the first duty cycle and toggles between second predefined amplitude values.

Abstract: An interpolative digital-to-analog (D/A) converter is adapted to convert a N-bit digital signal into an analog signal, where N is a positive integer greater than 1. The interpolative D/A converter includes a router unit that outputs first and second router voltages based on the first and second bits of the digital signal, and an interpolation unit that receives the first and second router voltages from the router unit, and that performs interpolation operation on the first and second router voltages according to the first bit of the digital signal, so as to generate the analog signal having a voltage magnitude ranging from the first router voltage to the second router voltage.

Abstract: A digital to analog converter (DAC) includes: first and second nodes; a first switching device; a second switching device; and a switch control module. The switch control module selectively configures the first and second switching devices such that: in a first configuration, the first switching device connects a first current to the first node and the second switching device connects a second current to the second node; in a second configuration, the first switching device connects the first current to the second node and the second switching device connects the second current to the first node; and in a third configuration, the first and second switching devices disconnect the first current and the second current from the first and second nodes.

Abstract: An integrated circuit device comprises at least one digital to analogue converter module. The DAC module includes at least one current replicator component having a first channel terminal, a second channel terminal and a reference voltage terminal arranged to receive a reference voltage signal; the at least one current replicator component being arranged to moderate a current flowing between the first and second channel terminals based at least partly on the received reference voltage signal. The DAC module also includes at least one filter component coupled to the reference voltage terminal to perform filtering of the reference voltage signal.

Abstract: A method and circuit to perform noise shaped splitting of a digital input signal may include using multiple layers to process the input signal. In the first layer, the most significant bits of the input signal may be distributed to a plurality of branches. Dynamic element matching may be performed using the least significant bits of the input signal. Based on the results of the dynamic element matching, values may be added to the plurality of branches. If there is insufficient data activity, dynamics enhancement may be performed to increase the data activity. The output signals of each of the plurality of branches in the first layer may be provided to a second layer, in which these steps can be repeated on each of the output signals. The outputs of the second layer may be provided to a plurality of three level unit elements.

Abstract: A gamma tab voltage generator includes a plurality of, a data calculator configured to generate a buffer selection information and a buffer combination information based on a current capacity of buffer, a plurality of digital-to-analog converters configured to generate gamma tab voltages based on a gamma tab voltage information, a buffer selector configured to connect input terminals of the buffers selected based on the buffer selection information to output terminals of the digital-to-analog converters, and a buffer combiner configured to connect output terminals of the selected buffers to one another in response to the buffer combination information.

Abstract: Apparatus implementing a monotonic output digital to analog converter (DAC). A high resolution monotonic DAC may be built from a lower resolution DAC using weighting functions that combine the outputs of the lower resolution DAC such that monotonicity is maintained across major carry transitions. The lower resolution DAC should have a true output and a complementary output with a half LSB bias in the output. An extended resolution DAC may be built of; cascaded low resolution DACs; a low resolution DAC in a recursive arrangement with an intermediate storage of its output; or a low resolution DAC with weighting functions that adjust at each of several major carry transition.

Abstract: An output device receives a data signal, outputs an output signal corresponding to the data signal in synchronization with a clock signal, and includes a driving unit configured to drive an output buffer that outputs the output signal. The driving unit includes a signal switching unit and first and second driving circuits that operate with the same power supply. The signal switching unit inputs the clock signal into one of the first and second driving circuits in accordance with the level of the data signal, and the one of the first and second driving circuits outputs a driving signal whose level varies in accordance with a change in the level of the clock signal to the output buffer.

Abstract: One example described herein relates to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and a plurality of cells arranged in rows and columns. Each cell includes a current source. A row decoder and a column decoder provide respective control signals to respective rows and respective columns to selectively couple a number of the current sources to an output of the DAC. The number of current sources which are coupled to the output by the control signals is dependent on the multi-bit digital input signal. At least one of the control signals is modulated based on a local oscillator signal.

Abstract: Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.

Abstract: A delta-sigma modulator includes: a loop filter for processing an analog input signal and a feedback signal to generate a filtered signal; a noise coupler operable to generate a noise coupled signal based on the filtered signal and the feedback signal; a quantizer for quantizing the noise coupled signal to generate a digital output signal; and a digital-to-analog converter converting the digital output signal to the feedback signal. The noise coupler includes an amplifier that has an inverting input terminal receiving a difference between the filtered signal and the feedback signal, and a non-inverting output terminal outputting the noise coupled signal, and a capacitor coupled between the inverting input terminal and the non-inverting output terminal of the amplifier.

Abstract: A technique includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The technique includes generating the plurality of control signals based on the digital code, a random digital code having a number of bits based on a feedback signal, and an indicator of a second sequence of unit elements of the plurality of unit elements enabled in response to a prior digital code.

Abstract: This disclosure describes techniques and apparatuses for low-memory-usage arbitrary waveform representation or generation. These techniques and/or apparatuses enable representation and/or generation of arbitrary waveforms using less memory than many current techniques, thereby reducing costs or memory size. Further, in some embodiments the techniques and apparatuses generate arbitrary waveforms without using processor resources.

Abstract: A FIRDAC with a return-to-zero or return-to-open drive uses multiple DACs receiving delayed copies of a digital input data signal to reduce thermal noise and intersymbol interference to produce a summed analog output. The SNR of sigma-delta ADCs using current-source-based DACs is significantly limited by the thermal noise of the DAC current sources. DACs using a switched voltage connected via a resistor or other passive element are quieter, but in a non-return-to-zero configuration tend to suffer from intersymbol interference if used at GHz clock frequencies. The intersymbol interference can be avoided by using a return-to-zero or return-to-open drive using multiple DACs clocked on successive half clock cycles (a finite-impulse-response DAC).

Abstract: A volume adjusting circuit which converts a digital audio signal to an analog signal by a D/A converter and outputs the analog signal includes: a first gain variable circuit unit which controls a gain of the digital audio signal; a second gain variable circuit unit which controls a gain of the analog signal output from the D/A converter; a storage unit which stores gain setting value; and a control unit which controls the gain of the first gain variable circuit unit and the gain of the second gain variable circuit unit based on the gain setting value stored in the storage unit, wherein the storage unit and the control unit are shared in controlling the first gain variable circuit unit and in controlling the second gain variable circuit unit.

Abstract: A digital-to-analog converter (DAC) has a pulse-width encoder that generates a charging pulse having a pulse width proportional to the DAC's digital input value. The charging pulse controls a charging switch that selectively connects a current source to a capacitor for the duration of the charging pulse. At the end of the charging pulse, a voltage corresponding to the charge stored in the capacitor forms the DAC's analog output signal. Such DACs can be configured (1) with negative-gain amplifiers across the capacitor to form a negative feedback loop, (2) with multiple parallel current sources, and/or (3) in differential architectures.

Abstract: A digitally controlled variable capacitance integrated electronic circuit module (100) comprises a set of basic cells in a matrix arrangement. Each basic cell itself comprises a functional block (11) which can be switched between two individual capacitance values, a control block (12), and a control junction connecting the control block and the functional block of said basic cell. The functional blocks and the control blocks are grouped into separate regions (110, 120) of the matrix arrangement, to reduce capacitive interaction between output paths and power supply paths of the module. The functional blocks can still be switched in a winding path order within the matrix arrangement. A module of the invention can be used in an oscillator capable of producing a signal at 4 GHz.

Abstract: A driving circuit includes a plurality of reference voltage lines and a digital to analog converter. The reference voltage lines are configured for respectively transmitting different grayscale reference voltages, in which the grayscale reference voltages are divided into at least two groups, and the wire diameter/wire width of at least one reference voltage line among the reference voltage lines of a first voltage group among the at least two groups is different from the wire diameters/wire widths of the reference voltage lines of a second voltage group among the at least two groups. The digital to analog converter is coupled to the reference voltage lines to receive the grayscale reference voltages and is for converting a digital signal into a grayscale voltage according to the grayscale reference voltages.

Abstract: An analog-digital converter includes: comparators disposed to correspond to analog signals which are converted into digital signals and configured to compare a voltage value of the analog signal, which is converted into the digital signal, with a voltage value of a predetermined reference signal; counters disposed to correspond to the comparators and configured to count a count value at the time point when the comparison process of the corresponding comparator is finished; and a determiner configured to determine a time point when all the comparators finish their comparison processes.

Abstract: Embodiments of the present invention may provide a string DAC with charge boosting. The string DAC may include multiple strings, such as an MSB DAC and an LSB DAC, for converting a digital word into a corresponding analog voltage. The string DAC may also include a charge boost system to couple a charge into or out of the DAC during a code transition, such as a MSB code transition. The string DAC may operate in a break-before-make connection technique where all relevant connections are substantially open-circuited before new connections are made. Therefore, the charge boost may shorten the settling time of impedance elements in the string DAC between code transitions and may substantially reduce (or eliminate) glitches.

Abstract: There is provided a digital-to-analog converter including: a mirror circuit including a first transistor to copy a reference current at a predetermined mirror ratio, and a second transistor cascade coupled with the first transistor; and an analog switch coupled with a gate of the second transistor, the analog switch being configured to be controlled, by a digital signal input from outside, so as to be turned on or off.

Abstract: A digital to analog converter including at least one current steering source and a master replica bias network. Each current steering source includes a data current source, two switches, two buffer devices, and two activation current sources. The switches are controlled by a data bit and its inverse for switching the source current between first and second control nodes. The buffer devices buffer the control nodes between corresponding output nodes. The activation current sources ensure that each buffer device remains active regardless of the state of the switches. The master replica bias network includes a replica buffer device coupled to a replica control node and a master buffer amplifier. The master buffer amplifier drives the first, second and replica buffer devices in parallel to maintain the first, second and replica control nodes at a common master control voltage to minimize noise and glitches at the output.

Abstract: An integrated circuit that communicates with a host device via audio channels includes an interfacing circuit that receives and transmits analog signals on the audio channels. Such audio channels are designed for audio speakers and microphones and the interfacing circuit transmits digital data based on the received analog signals. The integrated circuit includes a processing device that is electrically coupled to the interfacing circuit. The processing device receives the digital data from the interfacing circuit and adjusts at least one parameter of the interfacing circuit based on the received digital data. The interfacing circuit receives the digital data from the processing device and transmits analog signals on at least one of the audio channels based on the at least one adjusted parameter.

Abstract: An N bit sub-binary radix digital-to analog converter (DAC) includes a radix conversion module that converts an m bit digital input signal to an N bit sub-radix DAC code. A ladder module having NL bits has a plurality of first circuit elements corresponding to first respective bits of the N bit sub-radix DAC code. A segment module having NS bits has at least one second circuit element corresponding to second respective bits of the N bit sub-radix DAC code. N>m, and N is the sum of NL and NS.

Abstract: Techniques for adaptive gain adjustment in a signal processing path to achieve greater dynamic range. In an exemplary embodiment, a digital gain is applied to a digital input signal based on a detected level of the digital input signal. A corresponding analog gain is applied to the output of a digital-to-analog converter for converting the digital input signal to an analog signal, the product of the digital gain and the analog gain being kept constant. In an exemplary embodiment, a zero cross detector is employed to update the digital and analog gains only in the vicinity of zero crossings detected in the signal. In a further exemplary embodiment, a peak detector is employed to instantaneously adjust the digital and analog gains to avoid clipping in the signal path.

Abstract: An improved quadrature bandpass-sampling delta-sigma analog-to-digital demodulator is provided, which includes a loop filter, an A/D responsive to the loop filter, and a first feedback D/A responsive to the A/D up-converted in frequency by a first multiplier and a clock. A first summing circuit is responsive to the first D/A and an RF input for providing an input to the loop filter. A plurality of feedback D/As is responsive to the A/D up-converted in different frequencies by a plurality of multipliers and a plurality of clocks for providing feedback inputs to the loop filter. The loop filter comprises a plurality of resonators arranged in cascade configuration, a plurality of analog mixers to provide frequency shifting of the error signals propagating through the resonators, and a plurality of summing circuits responsive to the feedback D/As.

Abstract: A differential resistor-based digital-to-analog converter (RDAC) can include a positive digital-to-analog converter (PDAC) stage and a negative digital-to-analog converter (NDAC) stage. A first network of resistors of the PDAC stage can be electrically coupled to a second network of resistors of the NDAC stage utilizing an intermediary network of resistors. Further, a differential receiver can include a first input and a second input. The first input can be electrically coupled to a first resistor of the intermediary network of resistors, and the second input can be electrically coupled to a second resistor of the intermediary network of resistors. Furthermore, a portion of the first network of resistors can be electrically coupled to a positive output of the RDAC, and another portion of the second network of resistors can be electrically coupled to a negative output of the RDAC.

Abstract: A technique includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The technique includes generating the plurality of control signals based on the digital code, a random digital code having a number of bits based on a feedback signal, and an indicator of a second sequence of unit elements of the plurality of unit elements enabled in response to a prior digital code.

Abstract: A resistor-2 resistor (R-2R) digital-to-analog converter with resistor network reversal and methods of use are disclosed. A circuit includes a plurality of resistor stacks and a plurality of separation resistors which separate the resistor stacks. The circuit further includes a plurality of selection devices connected to a respective one of the plurality of resistor stacks. The circuit also includes a first termination resistor stack connected to a drain of a first resistor stack of the plurality of resistor stacks and a second termination resistor stack connected to a drain of a last resistor stack of the plurality of resistor stacks. The circuit further includes a first switch connected to the drain of the first resistor stack of the plurality of resistor stacks and an output. The circuit also includes a second switch connected to the drain of the last resistor stack of the plurality of resistor stacks and the output.

Abstract: In accordance with some embodiments of the present disclosure, a receiver may include a downconverter configured to demodulate a modulated wireless signal to produce a current-mode baseband signal and an analog-to-digital converter (ADC) configured to convert the current-mode baseband signal into a digital output signal. The downconverter may be coupled to the ADC without an intervening filter element.

Abstract: A digital-to-analog converter and a performing method thereof are disclosed. The digital-to-analog converter includes a random rotation unit, a plurality of conversion units, and a summing unit. The random rotation unit receives a plurality of binary-weighted inputs and generates a plurality of rotated digital outputs according to a random rotation number. The conversion units respectively receive one of the rotated digital outputs and generate a respective analog output. The summing unit sums the respective analog outputs of the conversion units for generating an analog output. The present invention implements the dynamic element matching technique by randomly rotating the binary-weighted inputs, so as to reduce the manufacturing cost of the digital-to-analog converter.

Abstract: A method and apparatus for detecting an event and sampling first value from a pin in response to the event. For example, the event is identified by a signal object of a plurality of signal objects stored in a memory. Each signal object of the plurality of signal objects identifies a single analog input pin and a trigger.

Abstract: A signal processing circuit has a first circuit, a digital-to-analog converter (DAC) and a second circuit. The first circuit receives a digital input signal with a non-zero direct current (DC) component, and subtracts at least a portion of the DC) component of the received digital input signal from the received digital input signal. The DAC is operably coupled to the first circuit, and arranged to perform a digital-to-analog conversion upon an output of the first circuit. The second circuit is operably coupled to the DAC, and arranged to add a DC component to an analog output signal derived from an output of the DAC. The signal processing circuit may be part of an integrated circuit or a wireless communication unit.

Abstract: Embodiments provide a mixer cell, which is implemented to logically combine a data signal with an oscillator signal and a sign signal to obtain a mixer cell output signal based on the logical combination. Further embodiments provide a modulator with a plurality of mixer cells.

Abstract: N upper-side resistors and N lower-side resistors are severally associated with respective bits of a digital input code. Each resistance value is weighted in an essentially binary manner according to the corresponding bit. N upper-side switches are each arranged in parallel with a corresponding upper-side resistor, and each is configured such that its on/off state is controlled according to the corresponding bit. N lower-side switches are each arranged in parallel with a corresponding lower-side resistor, and each is configured such that its on/off state is controlled according to logical inversion of the corresponding bit.

Abstract: A differential switch drive circuit includes a current source, a current control circuit including a pair of transistors having a pair of differential input terminals, a pair of differential output terminals for outputting differential output voltages, and a common connection node connected to the current source, and load elements each connected to a corresponding one of the pair of differential output terminals. Currents flowing through the pair of transistors are controlled so that the sum of currents flowing through the load elements during a steady state of the differential output voltages is different from the sum of currents flowing through the load elements during a transient state of the differential output voltages.

Abstract: A D/A conversion circuit includes: current generation circuits each including a constant current source configured to generate a current, a first MOSFET connected to the constant current source and configured to control a supply destination of the current, a first gate control section configured to exclusively supply a first voltage and a second voltage to a gate of the first MOSFET, and a first discharge switch connected to the first gate control section and the gate of the first MOSFET, controlled to be turned on at the same time as the first gate control section supplies the second voltage and controlled to be turned off before the first gate control section supplies the first voltage; a first current addition line; a discharge line; a first resistor connected to the first current addition line; and a voltage source configured to supply the second voltage to the first gate control sections.

Abstract: A system and method is disclosed for a digital to analog converter which includes an interpolation filter to up-sample a digital signal, a noise shaping modulator to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to a Class D delta-sigma pulse width modulation control loop.

Abstract: Embodiments of a digital-to-analog conversion system that utilizes a specialized clock signal to reshape an analog impulse response of a digital-to-analog converter (DAC) are disclosed. Preferably, a shape of the specialized clock signal is such that Nyquist images resulting from digital-to-analog conversion are controlled in a desired manner. In one embodiment, the digital-to-analog conversion system includes a DAC that converts a digital input signal into an analog output signal. A specialized clock signal is applied to the analog output signal of the DAC such that an analog impulse response of the DAC is reshaped according to a shape of the specialized clock signal, thereby providing a modified analog output signal. The specialized clock signal reshapes the analog impulse response of the DAC such that Nyquist images resulting from digital-to-analog conversion are controlled in a desired manner.

Abstract: A system and method is disclosed for a digital to analog converter which includes an interpolation filter to up-sample a digital signal, a noise shaping modulator to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to a reconstruction filter which outputs the analog signal.

Abstract: A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.

Abstract: Embodiments may comprise logic such as hardware and/or code for high-speed digital-to-analog conversion of signals. Many embodiments comprise a demultiplexer to distribute sets of bits to digital-to-analog converters, the digital-to-analog converters to receive the sets of bits and the operate concurrently to convert the sets of bits from digital representations of signal segments to output analog signal segments, and an interleaver to interleave the analog signal segments from each of digital-to-analog converters in the sequence to generate an analog signal. In many embodiments, the interleaver is adapted to interleave the analog signal segments by latching magnitudes of each of the analog signal segments to an interleaved output near ends of clock cycles to attenuate non-linearities in the magnitudes of each of the analog signal segments when the magnitudes are output.

Abstract: One embodiment of the present disclosure relates to a circuit. The circuit includes a digital to analog converter (DAC) configured to convert a time-varying, multi-bit digital value to a corresponding time-varying output current. The circuit also includes a mixer module downstream of the DAC and comprising a plurality of mixers. A control block is configured to selectively steer output current from the DAC to different mixers of the mixer module. Other techniques are also described.