Component Within Printed Circuit Board Patents (Class 361/761)
  • Patent number: 8035979
    Abstract: A printed wiring board includes a built-in semiconductor element. A protective film is formed on a semiconductor element-mounted surface of a base substrate to which the built-in semiconductor element is connected to protect the semiconductor element-mounted surface excepting a mounting pad. Upper and side surfaces of the built-in semiconductor element are covered with a first insulating film formed by filling a sealing material. The first insulating film is covered with a second insulating film formed of an insulating resin melted from an insulating layer that is provided in side and upper portions of the built-in semiconductor element.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: October 11, 2011
    Assignees: CMK Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Yutaka Yoshino, Takahiro Shirai, Shinji Kadono, Mineo Kawamoto, Minoru Enomoto, Masakatsu Goto, Makoto Araki, Naoki Toda
  • Patent number: 8035978
    Abstract: A printed circuit board includes a mounted a first electronic component. The printed circuit board includes a first through holes extending from a mounting surface on which the electronic component is mounted. The printed circuit board includes a second through holes extending from a surface opposite the mounting surface and aligned with the first through holes. A second electronic component may be longitudinally between the first through holes and the second through holes. The first and second through holes may be electrically connected with the second electronic component.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: October 11, 2011
    Assignee: Fujitsu Limited
    Inventor: Shigeru Sugino
  • Patent number: 8031474
    Abstract: A printed circuit board assembly has plural printed circuit boards that are mechanically and electrically connected to each other with them being stacked, and a connection layer that connects the adjacent two printed circuit boards to each other is provided. The connection layer includes an insulation portion and an electric conduction portion. The insulation portion contains an insulating member and is adhered to each of the adjacent two printed circuit boards. The electric conduction portion passes through the insulation portion and connects electrode terminals of the adjacent two printed circuit boards.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: October 4, 2011
    Assignee: Sony Corporation
    Inventors: Minoru Ogawa, Kazuto Nishimoto
  • Patent number: 8022312
    Abstract: A substrate structure capable of miniaturizing and thinning a housing of a portable terminal is provided. A substrate structure 10 comprises a substrate 11, plural electronic components 12 mounted along one mounting surface 11A in the substrate 11, and a resin part 13 for making close contact with the mounting surface 11A of the substrate 11while each of the electronic components 12 is covered with a resin 13A. In the substrate structure 10, a through hole 14 extending through the substrate 11 in a thickness direction is disposed and also the side of the mounting surface 11A in the through hole 14 is closed by a lid member 15. A rising part 21 is disposed in a peripheral part of this lid member 15.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: September 20, 2011
    Assignee: Panasonic Corporation
    Inventors: Haruo Hayakawa, Kazuhiro Konishi, Mamoru Yoshida, Kazunori Kouno
  • Patent number: 8023278
    Abstract: A circuit board includes a plurality of conductive layers, a plurality of insulating layers, a telecommunication network connection port and a modem card processing module. A high voltage signal line is laid out at one of the conductive layers. The insulating layers are disposed between each of the conducting layers, respectively. The telecommunication network connection port is disposed on the conductive layers and is electrically connected to one end of the high voltage signal line. The modem card processing module is disposed on the conductive layers and is electrically connected to the other end of the high voltage signal line.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: September 20, 2011
    Assignee: Asustek Computer Inc.
    Inventor: Ching-Jen Wang
  • Publication number: 20110216514
    Abstract: A combined multilayered circuit board is provided. The combined multilayered circuit board includes a plurality of multilayered circuit boards, at least one of the plurality circuit boards being formed with an embedded electronic component and an internal chamber receiving the embedded electronic component. The internal chamber is full of air. The combined multilayered circuit board further includes at least one glue layer interposed between each of the plurality of multiple circuit boards for bonding the plurality of multilayered circuit boards together.
    Type: Application
    Filed: February 24, 2011
    Publication date: September 8, 2011
    Applicant: MUTUAL-TEK INDUSTRIES CO., LTD.
    Inventor: Jung-Chien Chang
  • Publication number: 20110216513
    Abstract: An electro device embedded printed circuit board and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, a printed circuit board embedded with an electro device, in which a pair of electrodes are formed on either end, includes: a core substrate in which a first cavity is formed; a first passive device embedded in the first cavity and being thinner than the core substrate; and a second passive device stacked on an upper side of the first passive device such that the second passive device is embedded in the first cavity. The first passive device and the second passive device are stacked to cross each other.
    Type: Application
    Filed: September 8, 2010
    Publication date: September 8, 2011
    Inventors: Doo-Hwan LEE, Sang-Jin Baek, Jin-Soo Jeong, Sang-Chul Lee, Jong-Yun Lee, Jae-Kul Lee
  • Patent number: 8012801
    Abstract: A flip chip mounting process includes the steps of supplying a resin (13) containing solder powder and a convection additive (12) onto a wiring substrate (10) having a plurality of electrode terminals (II), then bringing a semiconductor chip (20) having a plurality of connecting terminals (11) into contact with a surface of the supplied resin (13), and then heating the wiring substrate (10) to a temperature that enables the solder powder to melt. The heating step is carried out at a temperature that is higher than the boiling point of the convection additive (12) to allow the boiling convection additive (12) to move within the resin (12). During this heating step, the melted solder powder is allowed to self-assemble into the region between each electrode terminal (11) of the wiring substrate (10) and each connecting terminal (21) of the semiconductor chip to form an electrical connection between each electrode terminal (11) and each connecting terminal (21).
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: September 6, 2011
    Assignee: Panasonic Corporation
    Inventors: Seiji Karashima, Yoshihisa Yamashita, Satoru Tomekawa, Takashi Kitae, Seiichi Nakatani
  • Publication number: 20110211319
    Abstract: Printed circuit boards including voltage switchable dielectric materials (VSDM) are disclosed. The VSDMs are used to protect electronic components, arranged on or embedded in printed circuit boards, against electric discharges, such as electrostatic discharges or electric overstresses. During an overvoltage event, a VSDM layer shunts excess currents to ground, thereby preventing electronic components from destruction or damage.
    Type: Application
    Filed: February 25, 2011
    Publication date: September 1, 2011
    Inventors: Lex Kosowsky, Robert Fleming, Bhret Graydon, Daniel Vasquez
  • Patent number: 7999401
    Abstract: Semiconductor device has a semiconductor chip embedded in an insulating layer. A semiconductor device comprises a semiconductor chip formed to have external connection pads and a positioning mark that is for via formation; an insulating layer containing a non-photosensitive resin as an ingredient and having a plurality of vias; and wiring electrically connected to the external connection pads through the vias and at least a portion of which is formed on the insulating layer. The insulating layer is formed to have a recess in a portion above the positioning mark. The bottom of the recess is the insulating layer alone. Vias have high positional accuracy relative to the mark.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: August 16, 2011
    Assignees: NEC Corporation, Renesas Electronics Corporation
    Inventors: Hideya Murai, Kentaro Mori, Shintaro Yamamichi, Masaya Kawano, Takehiko Maeda, Kouji Soejima
  • Patent number: 8000107
    Abstract: A carrier with embedded components comprises a substrate and at least one embedded component. The substrate has at least one slot and a first composite layer. The embedded component is disposed at the slot of the substrate. The first composite layer has a degassing structure, at least one first through hole and at least one first fastener, wherein the degassing structure corresponds to the slot, the first through hole exposes the embedded component, and the first fastener is formed at the first through hole and contacts the embedded component. According to the present invention, the degassing structure can smoothly discharge the hydrosphere existing within the carrier under high temperature circumstances and the first fastener is in contact with the embedded component, which increases the joint strength between the embedded component and the substrate.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: August 16, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Hui Wang, In-De Ou, Chih-Pin Hung
  • Publication number: 20110194265
    Abstract: An embodiment of an embedded component substrate includes: (1) a semiconductor device including lower, lateral, and upper surfaces; (2) a first patterned conductive layer including a first electrical interconnect extending substantially laterally within the first patterned conductive layer; (3) a second electrical interconnect extending substantially vertically from a first surface of the first interconnect, and including lateral and upper surfaces, and a lower surface adjacent to the first surface; (4) a dielectric layer including an opening extending from an upper surface of the dielectric layer to a lower surface of the dielectric layer, where: (a) the dielectric layer substantially covers the lateral and upper surfaces of the device, and at least a portion of the lateral surface of the second interconnect; and (b) the second interconnect substantially fills the opening; and (5) a second patterned conductive layer adjacent to the upper surfaces of the dielectric layer and the second interconnect.
    Type: Application
    Filed: February 5, 2010
    Publication date: August 11, 2011
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Ming-Chiang Lee, Chien-Hao Wang
  • Patent number: 7992291
    Abstract: A method of manufacturing a circuit board, which includes a bump pad on which a solder bump may be placed, may include forming a solder pad on a surface of a first carrier; forming a metal film, which covers the solder pad and which extends to a bump pad forming region; forming a circuit layer and a circuit pattern, which are electrically connected with the metal film, on a surface of the first carrier; pressing the first carrier and an insulator such that a surface of the first carrier and the insulator faces each other; and removing the first carrier. Utilizing this method, the amount of solder for the contacting of a flip chip can be adjusted, and solder can be filled inside the board, so that after installing a chip, the overall thickness of the package can be reduced.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: August 9, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hoe-Ku Jung, Je-Gwang Yoo, Myung-Sam Kang, Ji-Eun Kim, Jeong-Woo Park, Jung-Hyun Park
  • Patent number: 7994429
    Abstract: A manufacturing method and structure for substrate with vertically embedded capacitors includes the steps of providing a plurality of conductive layers having a first dielectric layer and a leading wire layer formed on the first dielectric layer, providing a plurality of composite layers having a second dielectric layer and a patterned electrode layer formed on the second dielectric layer, laminating the conductive layers and the composite layers to form a block which defines a plurality of substrates with vertically embedded capacitors and a plurality of sawing streets between the substrates, and sawing the block along the sawing streets to singularize the substrates.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: August 9, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Guo-Cheng Liao
  • Patent number: 7989706
    Abstract: A circuit board has an embedded electronic component such as an integrated circuit chip with a wafer level chip size package. A via hole extends through the electronic component. Another via hole extends through the substrate or prepreg on which the electronic component is mounted inside the circuit board. Conductors in the via holes enable a terminal on the surface of the electronic component to be electrically connected to a wiring pattern or another electronic component on the opposite side of the substrate or prepreg. Routing the connection through the electronic component itself saves space and reduces the length of the connection.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: August 2, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yoshinori Shizuno
  • Patent number: 7983055
    Abstract: A printed circuit board having an embedded cavity capacitor is disclosed. According to an embodiment of the present invention, the printed circuit board having the embedded cavity capacitor, the printed circuit board can include two conductive layers to be used as a power layer and a ground layer, respectively; and a first dielectric layer, placed between the two conductive layers, wherein at least one cavity capacitor is arranged in a noise-transferable path between a noise source and a noise prevented destination which are placed on the printed circuit board, the cavity capacitor being formed to allow a second dielectric layer to have a lower stepped region than the first dielectric layer, the second dielectric layer using the two conductive layers as a first electrode and a second electrode, respectively, and placed between the first electrode and the second electrode.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: July 19, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Han Kim, Je-Gwang Yoo, Chang-Sup Ryu
  • Publication number: 20110170273
    Abstract: A photostructurable ceramic is processed using photostructuring process steps for embedding devices within a photostructurable ceramic volume, the devices may include one or more of chemical, mechanical, electronic, electromagnetic, optical, and acoustic devices, all made in part by creating device material within the ceramic or by disposing a device material through surface ports of the ceramic volume, with the devices being interconnected using internal connections and surface interfaces.
    Type: Application
    Filed: January 13, 2010
    Publication date: July 14, 2011
    Applicant: The Aerospace Corporation
    Inventor: Henry Helvajian
  • Patent number: 7975377
    Abstract: A wafer scale heat slug system is presented providing dicing an integrated circuit from a semiconductor wafer, forming a heat slug blank equivalent in size to the semiconductor wafer, dicing the heat slug blank to produce a heat slug equivalent in size to the integrated circuit, attaching the integrated circuit to a substrate, attaching the heat slug to the integrated circuit and encapsulating the integrated circuit.
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventor: Hyeog Chan Kwon
  • Patent number: 7978031
    Abstract: The present invention is provided with a high frequency module comprising a multilayered substrate, a power amplifier IC mounted on the upper surface of the multilayered substrate, first and second filters disposed substantially directly below the power amplifier IC in an inner layer of the multilayered substrate, and coupling-reducing ground vias disposed between the first filter and the second filter. At least the first filter is disposed substantially directly below the power amplifier IC. The coupling-reducing ground vias double as thermal vias for dissipating heat generated by the power amplifier IC.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: July 12, 2011
    Assignee: TDK Corporation
    Inventors: Tomoyuki Goi, Takuya Adachi, Atsuhi Ajioka, Hitoshi Hachiga
  • Publication number: 20110164391
    Abstract: Disclosed herein is an electronic component-embedded printed circuit board, including: a metal substrate including an anodic oxide film formed over the entire surface thereof; two electronic components disposed in a cavity formed in the metal substrate in two stages; an insulation layer formed on both sides of the metal substrate to bury the electronic components disposed in the cavity; and circuit layers including vias connected with connecting terminals of the electronic components and formed on the exposed surfaces of the insulation layer. The electronic component-embedded printed circuit board is advantageous in that its radiation performance of radiating the heat generated from an electronic component can be improved, and its production cost can be reduced, because a metal substrate is used instead of a conventional insulating material.
    Type: Application
    Filed: May 6, 2010
    Publication date: July 7, 2011
    Inventors: Yee Na SHIN, Tae Sung JEONG, Young Ki LEE, Seung Eun LEE
  • Patent number: 7968800
    Abstract: A passive component incorporating interposer includes a double-sided circuit board (1) having a wiring layer (8) on both sides, a passive component (2) mounted on the wiring layer (8) on one surface of the double-sided circuit board (1), a second insulating layer (3) made of woven fabric or non-woven fabric or inorganic filler and thermosetting resin laminated on the surface of the double-sided circuit board (1) mounted with the passive component (2), a first insulating layer (4) made of woven fabric or non-woven fabric or inorganic filler and thermosetting resin laminated on the other surface of the double-sided circuit board (1) not mounted with the passive component (2), first and second wiring layers (5, 6) formed on the first and second insulating layers (3, 4), and a through hole (7) for electrically connecting the wiring layers (8) disposed on both surfaces of the double-sided circuit board (1) and the first and second wiring layers (5, 6), where the first wiring layer (5) is formed to enable mounting
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: June 28, 2011
    Assignee: Panasonic Corporation
    Inventors: Tatsuo Sasaoka, Yasuhiro Sugaya, Eiji Kawamoto, Kazuhiko Honjo, Toshiyuki Asahi, Chie Sasaki, Hiroaki Suzuki
  • Patent number: 7968991
    Abstract: A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads; the first circuit board comprises a first surface, an opposite second surface, a plurality of exposed electro-connecting ends, a plurality of first conductive pads on the first surface, a plurality of conductive vias, and at least one circuit layer, therewith the electrode pads of the first chip electrically connecting to the electro-connecting ends and the first conductive pads directly through the conductive vias and the circuit layer; and a second package structure electrically connecting to the first package structure through a plurality of first solder balls to make a package on package. The stacked package module of this invention has characters of compact size, high performance, high flexibility, and detachability.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: June 28, 2011
    Assignee: Unimicron Technology Corp.
    Inventors: Lin-Yin Wong, Mao-Hua Yeh, Wang-Hsiang Tsai
  • Patent number: 7969745
    Abstract: The present invention provides a circuit board having electronic components integrated therein, including a carrier board having an metallic oxide layer formed on each two surfaces of a metal layer, and having at least one through cavity; at least a semiconductor chip hold in the opening; at least a capacitor disposed on one surface of the carrier board, wherein the surface with the capacitor disposed thereon is at the same side with the active surface of the semiconductor chip. The capacitor is constituted of a first electrode plate disposed on partial surface of one side of the carrier board, a high dielectric material layer disposed on the surface of the first electrode plate, and a second electrode plate, paralleling and corresponding to the first electrode plate, disposed on the surface of the high dielectric material. The metal layer and the oxidation layer of the carrier board can enhance rigidity as well as tenacity and also integrate semiconductor chips and capacitors in the circuit board structure.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: June 28, 2011
    Assignee: Unimicron Technology Corporation
    Inventors: Shih-Ping Hsu, Kan-Jung Chia
  • Publication number: 20110149538
    Abstract: This provisional application relates to reducing electromagnetic interferences (EMI) using embedded magnetic material in a printable circuit board (PCB) and the applications thereof.
    Type: Application
    Filed: September 18, 2010
    Publication date: June 23, 2011
    Inventors: Ji Cui, Nie Luo
  • Publication number: 20110149519
    Abstract: According to various aspects of the present disclosure, an apparatus is disclosed that includes a small form factor mobile platform including a system-on-package architecture, the system-on-package architecture arranged as a stack of layers including a first layer having a first conformable material; a second layer having a second conformable material; one or more electronic components embedded within the stack of layers; and a vertical filtering structure arranged periodically between the one or more electronic components, wherein the first conformable material, the second conformable material, or both are configured to allow high frequency signal routing.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventors: Dobabani CHOUDHURY, Prasad ALLURI
  • Patent number: 7957155
    Abstract: A method and system for transporting a fluid, gas, semi-solid, cryogen, or particulate matter, or combination thereof, between a three-dimensional structure and a substantially two-dimensional structure is disclosed. A system and method for electrically coupling a three-dimensional structure to a substantially two dimensional structure is also disclosed.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: June 7, 2011
    Assignee: Medconx, Inc.
    Inventors: Harold B. Kent, Steven T. Kent
  • Patent number: 7956713
    Abstract: In one embodiment, the present invention includes an apparatus having a substrate with vias extending between first and second surfaces thereof, and at least one helical inductor adapted within a via, which may be formed of a conductive material. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: June 7, 2011
    Assignee: Intel Corporation
    Inventors: Arun Chandrasekhar, Srikrishnan Venkataraman, Priyavadan R. Patel, Shamala Chickamenahalli, Robert J. Fite, Charan Gurumurthy
  • Patent number: 7952204
    Abstract: An exemplary semiconductor die package is disclosed having one or more semiconductor dice disposed on a first substrate, one or more packaged electrical components disposed on a second substrate that is electrical coupled to the first substrate, and an electrically insulating material disposed over portions of the substrates. The first substrate may hold power-handling devices and may be specially constructed to dissipation heat and to facilitate fast and inexpensive manufacturing. The second substrate may hold packaged components of control circuitry for the power-handling devices, and may be specially constructed to enable fast and inexpensive wiring design and fast and inexpensive component assembly. The first substrate may be used with different designs of the second substrate.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: May 31, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yumin Liu, Hua Yang, Yong Liu, Tiburcio A. Maldo
  • Patent number: 7948764
    Abstract: Method for mounting an electronic component, such as a silicon chip, on a support which consists in: providing an electronic component (40) having connection pads, whereof one predetermined pad (41A) is provided with a bump (42); providing a support having (30) to the predetermined pad via the bump; aligning the predetermined pad provided with the bump with the terminal; contacting the bump and the terminal and assembling them in specific temperature and pressure conditions. Prior to contacting and fixing the bump and the terminal, the surface of the terminal is covered with an insulating layer (32), the insulating layer being a material selected so as to be traversed by the bump in the temperature and pressure conditions.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: May 24, 2011
    Assignee: Oberthur Technologies
    Inventors: Guy Enouf, Xavier Borde, Florian Demaimay
  • Patent number: 7948767
    Abstract: The invention provides an integrated circuit packaging and method of making the same. The integrated circuit packaging includes a substrate, a semiconductor die, a heat-dissipating module, and a protection layer. The substrate has an inner circuit formed on a first surface, and an outer circuit formed on a second surface and electrically connected to the inner circuit. The semiconductor die is mounted on the first surface of the substrate such that the plurality of bond pads contact the inner circuit. The heat-dissipating module includes a heat-conducting device, and the heat-conducting device, via a flat end surface thereof, contacts and bonds with a back surface of the semiconductor die. The protection layer contacts a portion of the first surface of the substrate and a portion of the heat-conducting device, such that the semiconductor die is encapsulated therebetween.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: May 24, 2011
    Assignee: Neobulb Technologies, LLP.
    Inventor: Jen-Shyan Chen
  • Patent number: 7948766
    Abstract: A method is for making a structural printed wiring board panel that includes a multilayer printed wiring board having opposing, outer faces and interlayer interconnects that route RF, power and control signals. Connection areas are formed in or on at least on one face for connecting the interlayer interconnects and any electrical components. A metallic face sheet is secured onto at least one outer face, adding structural rigidity to the multilayer printed wiring board. A metallic face sheet can have apertures positioned to allow access to connection areas. RF components can be carried by a face sheet and operatively connected to connection areas. Antenna elements can be positioned on the same or an opposing face sheet and operatively connected to RF components to form a phased array printed wiring board (PWB) panel.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: May 24, 2011
    Assignee: Harris Corporation
    Inventors: Gregory M. Jandzio, Anders P. Pedersen, Gary A. Rief, Walter M. Whybrew
  • Publication number: 20110116246
    Abstract: An electronic component embedded printed circuit board and a method of manufacturing the same are disclosed. The electronic component embedded printed circuit board in accordance with an embodiment of the present invention can include a first substrate, which has a cavity formed therein, a first electronic component, which is embedded in the cavity in a face-down manner, a second electronic component, which is stacked on an upper side of the first electronic component and embedded in the cavity in a face-up manner, and a second substrate, which is stacked on upper and lower surfaces of the first substrate.
    Type: Application
    Filed: June 18, 2010
    Publication date: May 19, 2011
    Inventors: Jin-Won LEE, Yul-Kyo Chung, Seung-Hyun Sohn, Moon-Il Kim
  • Patent number: 7944171
    Abstract: An attachable wireless charging device includes a carrier board, a receiving coil, a circuit board, and at least two conductive wires. The carrier board has a back surface on which an adhesive layer is coated. The receiving coil is formed in the carrier board. The circuit board is mounted to one side of the carrier board and includes a power receiving circuit, which includes a receiving control circuit, a resonance control circuit, a regulation circuit, a control circuit, a polarity selection circuit, and a circuit output section, which are electrically and sequentially connected. Electrical connection is established between the receiving control circuit and the receiving coil. The at least two conductive wires are arranged at one side of the circuit board and are electrically connectable with the circuit output section of the circuit board. As such, an attachable wireless charging device featuring automatic determination of polarity connection is provided.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: May 17, 2011
    Inventor: Ming-Hsiang Yeh
  • Patent number: 7939765
    Abstract: An intermediate layer 38 is provided on a die pad 22 of an IC chip 20 and integrated into a multilayer printed circuit board 10. Due to this, it is possible to electrically connect the IC chip 20 to the multilayer printed circuit board 10 without using lead members and a sealing resin. Also, by providing the intermediate layer 38 made of copper on an aluminum pad 24, it is possible to prevent a resin residue on the pad 24 and to improve connection characteristics between the die pad 24 and a via hole 60 and reliability.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: May 10, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Hajime Sakamoto, Dongdong Wang
  • Patent number: 7936063
    Abstract: A carrier assembly for an integrated circuit is disclosed. The carrier assembly has a retainer with electrical contacts for receiving the integrated circuit, and island defining portions arranged about the retainer. Each island defining portion is connected to neighboring island defining portions through a serpentine member. This connection allows resilient deflection between the island defining portions.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: May 3, 2011
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 7936567
    Abstract: A method for manufacturing a wiring board with built-in component. The method provides a secure connection between a component and interlayer insulating layers so that the wiring board with built-in component has excellent reliability. The wiring board is manufactured through a core board preparation step, a component preparation step, an accommodation step and a height alignment step. In the core board preparation step, a core board having an accommodation hole therein is prepared. In the component preparation step, a ceramic capacitor having therein a plurality of protruding conductors which protrudes from a capacitor rear surface is prepared. In the accommodation step, the ceramic capacitor is accommodated in the accommodation hole with the core rear surface facing the same side as the capacitor rear surface. In the height alignment step, a surface of a top portion of the protruding conductor and a surface of a conductor layer formed on the core rear surface are aligned to the same height.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: May 3, 2011
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Tsuneaki Takashima, Jun Otsuka, Makoto Origuchi, Yukinobu Nagao, Chy Narith, Kozo Yamasaki
  • Patent number: 7935573
    Abstract: The electronic device comprises a first substrate 10 with an electric circuit element formed in a predetermined region of one primary surface, a second substrate 12 formed, opposed to said one primary surface of the first substrate 10, sealing portions 26, 40 formed between the first substrate 10 and the second substrate 12, enclosing the predetermined region of the first substrate 10, and an adhesion layer 42 formed on the side surfaces of the sealing parts 26, 40. The adhesion layer is formed on the side surfaces of the first sealing structure 26 on the side of the first substrate 10 and the second sealing structure 40 on the side of the second substrate 12, whereby when the first sealing structure 26 and the second sealing structure 40 are bonded to each other, the adhesion between the first sealing structure 26 and the second sealing structure 40 can be sufficiently ensured.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: May 3, 2011
    Assignee: Fujitsu Limited
    Inventor: Masataka Mizukoshi
  • Patent number: 7933128
    Abstract: An electronic device includes: an outline configuration including a first surface, a second surface facing opposite from the first surface, and a mounting surface coupled to the first and second surfaces; a first substrate including a first electrode; a second substrate including a second electrode; a resin disposed between the first and second substrates; and an electric element sealed with the resin and having an outline configuration of a polyhedron, the electric element being disposed such that a broadest surface of the polyhedron faces one of the first substrate and the second substrate. The first surface is one surface of the first substrate, the one surface being opposite from another surface of the first substrate on a side adjacent to the resin. The second surface is one surface of the second substrate, the one surface being opposite from another surface of the second substrate on a side adjacent to the resin.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: April 26, 2011
    Assignee: Epson Toyocom Corporation
    Inventors: Atsushi Ono, Yoshihiro Kobayashi, Shojiro Kitamura, Masayuki Matsunaga, Akitoshi Hara
  • Patent number: 7932471
    Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: April 26, 2011
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Kazuhiro Hayashi, Jun Otsuka, Manabu Sato
  • Publication number: 20110090656
    Abstract: A method for manufacturing an electronic device comprising a terminal provided with a conductor which penetrates a cured prepreg is provided. At least one opening is formed in the prepreg. The prepreg is attached to a substrate over which an electronic element is formed so that the conductor included in the terminal overlaps with the opening. A conductive paste is provided in a region of the prepreg where the opening is provided. Part of the conductive paste flows into the opening to be in contact with the conductor included in the terminal. Then, heat treatment is performed so that the conductive paste and the prepreg are cured. In the process for manufacturing the terminal, it is not necessary to perform a step of forming an opening with a laser beam after the prepreg is cured. Thus, an adverse effect of a laser beam on the electronic element can be eliminated.
    Type: Application
    Filed: October 20, 2010
    Publication date: April 21, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Toshiji HAMATANI, Tomoyuki AOKI, Hiroki ADACHI, Hiroyuki YAJIMA
  • Patent number: 7929312
    Abstract: The present invention provides a device mounting structure and a device mounting method in which the short circuit can be prevented between a device lead part and a device ground part when the reflow process is executed. Thus, in the device mounting structure of the present invention, the device is contained in an aperture part provided in a wired board on a heat-radiating plate, a device main part of the device being fixed on the device ground part, a device lead part extending from opposing sides of the device main part is connected to a wiring part on the wired board, and an internal wall of the aperture part positioned just under the device lead part and the device ground part positioned on the heat-radiating plate are separated by a predetermined distance.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: April 19, 2011
    Assignee: NEC Corporation
    Inventor: Masahiro Tamura
  • Publication number: 20110085310
    Abstract: The present invention is a circuit board with precision clearance holes that accommodate components that are attached to the circuit board. The components are mounted in an inverted position so that the component contacts are still connected to the top side of the circuit board and the body of the component fits substantially within the precision clearance hole.
    Type: Application
    Filed: October 9, 2009
    Publication date: April 14, 2011
    Inventors: Joseph M. Cachia, Ken Segler
  • Patent number: 7924569
    Abstract: By providing thermoelectric elements, such as Peltier elements, in a semiconductor device, the overall heat management may be increased. In some illustrative embodiments, the corresponding active cooling/heating systems may be used in a stacked chip configuration to establish an efficient thermally conductive path between temperature critical circuit portions and a heat sink of the stacked chip configuration.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: April 12, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Tobias Letz
  • Publication number: 20110075384
    Abstract: Sensitive electronic components can be mounted on a printed circuit board within an electronic device. To isolate a sensitive component from stresses that may arise during an unintended impact event, the electronic component can be isolated using a groove in the printed circuit board. The electronic component may be mounted to a component mounting region using solder balls. The component mounting region may be surrounded on some or all sides by the groove. Flex circuit structures that bridge the groove or a portion of the rigid printed circuit board may be used to hold the component mounting region in place. The flex circuit structures may be provided in the form of separate structures or may be provided as an integral portion of the printed circuit board.
    Type: Application
    Filed: September 29, 2009
    Publication date: March 31, 2011
    Inventor: Kyle H. Yeates
  • Publication number: 20110075387
    Abstract: A strain measurement chip including a body, a strain gauge provided within the body, and electrical contacts with which the strain measurement chip can be mounted to a circuit board, at least one of the electrical contacts being in electrical communication with the strain gauge to enable communication of strain data measured by the strain gauge to the circuit board.
    Type: Application
    Filed: May 21, 2008
    Publication date: March 31, 2011
    Inventors: Steven S. Homer, Mark S. Tracy, Kenneth D. Reddix, Walter J. Rankins
  • Patent number: 7916497
    Abstract: Provided is a system adopting a differential signaling system including a low frequency signaling line arranged to be adjacent to a pair of differential signaling lines in parallel to each other, for transmitting a signal having a frequency which is smaller than a frequency of a signal to be transmitted through the pair of differential signaling lines, in which a transmission end of the low frequency signaling line is connected to a ground pattern through a first capacitive element, and a reception end of the low frequency signaling line is connected to the ground pattern through a second capacitive element. Thus, it is possible to provide, easily and at a low cost, a differential signaling system in which a common mode noise is eliminated without increasing the number of pins.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: March 29, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroyuki Yamaguchi
  • Patent number: 7911026
    Abstract: Carrier including: a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and; has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: March 22, 2011
    Assignee: Qimonda AG
    Inventors: Florian Binder, Thomas Haneder, Judith Lehmann, Manfred Schneegans, Grit Sommer
  • Patent number: 7911801
    Abstract: A laminate includes base material layers and interlayer constraining layers disposed therebetween. The base material layers are formed of a sintered body of a first powder including a glass material and a first ceramic material, and the interlayer constraining layer includes a second powder including a second ceramic material that will not be sintered at a temperature for melting the glass material, and is in such a state that the second powder adheres together by diffusion or flow of a portion of the first powder including the glass material included in the base material layer at the time of baking. The incorporated element is in such a state that an entire periphery thereof is covered with the interlayer constraining layer.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: March 22, 2011
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yuichi Iida, Osamu Chikagawa
  • Publication number: 20110063811
    Abstract: A printed wiring board includes a main body having a mounting portion and ground and power supply pads in the mounting portion such that a ground line of a semiconductor device is connected to a ground pad and a power supply line of the device is connected to a power supply pad, and a layered capacitor disposed in the main body and having a high dielectric constant layer and first and second layer electrodes sandwiching the dielectric layer. One of the electrodes is connected to the power supply line and the other electrode is connected to the ground line, the first electrode has a solid pattern including passage holes through which second rod terminals connected to the second electrode pass in a non-contacting manner, and the second electrode has a solid pattern including passage holes through which first rod terminals connected to the first electrode pass in a non-contacting manner.
    Type: Application
    Filed: November 18, 2010
    Publication date: March 17, 2011
    Applicant: IBIDEN CO., LTD.
    Inventors: Takashi KARIYA, Akira Mochida
  • Patent number: 7907417
    Abstract: A printed circuit board (PCB) is disclose such that the PCB has enhanced structural integrity. The PCB has opposing, outer faces and interlayer interconnects that route RF, power and control signals. Connection areas are formed in or on at least on one face for connecting the interlayer interconnects and any electrical components. A metallic face sheet is secured onto at least one outer face, adding structural rigidity to the multilayer printed wiring board. A metallic face sheet can have apertures positioned to allow access to connection areas. RF components can be carried by a face sheet and operatively connected to connection areas. Antenna elements can be positioned on the same or an opposing face sheet and operatively connected to RF components to form a phased array printed wiring board (PWB) panel.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: March 15, 2011
    Assignee: Harris Corporation
    Inventors: Gregory M. Jandzio, Anders P. Pedersen, Gary A. Rief, Walter M. Whybrew