Abstract: The techniques described herein relate to methods, apparatus, and computer readable media configured to schedule individual orthogonal frequency-division multiple access (OFDMA) resources on an upstream channel to serve a data transmission request from a downstream device. A schedule for a set of available resources on the upstream channel to serve the data transmission request is generated, based on a dynamic bit loading profile, including generating data indicative of a first bit loading profile for a first set of resources from the set of available resources for a first burst, and data indicative of a second bit loading profile for a second set of resources from the set of available resources for a second burst. The schedule is transmitted to a downstream device, such that the downstream device is configured to encode the first burst using the first bit loading profile and the second burst using the second bit loading profile.
Abstract: A distributed control information system for three party communications in a Vehicle to Everything (V2X) environment is disclosed. A first node can generate sidelink control information for a transmission between a second node and a third node. The first node can transmit the sidelink control information to the second node, and then the second node can transmit a portion of the sidelink control information relevant to the third node to the third node. In an embodiment, the first node can also send the third node portion of the sidelink control information to the third node directly, thus improving the reliability of the system. These transmissions can be performed via sidelink communications channels.
Abstract: A network device synchronization method is provided. In various embodiments, a first SSM and a second SSM are received. The first SSM carries a first SSM code indicating a quality level of a first clock source and a first eSSM code indicating the quality level of the first clock source, the second SSM carries a second SSM code indicating a quality level of a second clock source. The second SSM lacks an eSSM code indicating the quality level of the second clock source, and a value of the first SSM code is equal to a value of the second SSM code. When a value of the first eSSM code is less than 0xFF, calibrating a frequency of the network device based on a timing signal of the first clock source.
Abstract: A computer-implemented method for importing external data into a content management system (CMS) may be provided. The CMS comprises a search and an authoring service. The CMS also comprises a dynamic page connector service enabling an import of external data into the content management system. The method comprises receiving address data relating to the external data, reading the external data using the address data received, selecting a page template from a plurality of predefined page templates, creating at least one new content item in the content management system comprising at least a data element of the read external data based on the selected predefined page template, and integrating in the at least one new content item data concerning a hierarchy structure between the at least one created content item and other content items.
Type:
Grant
Filed:
June 4, 2019
Date of Patent:
March 8, 2022
Assignee:
International Business Machines Corporation
Inventors:
Timo Kussmaul, Andreas Stay, Dieter Buehler
Abstract: In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.
Type:
Grant
Filed:
May 13, 2019
Date of Patent:
March 1, 2022
Assignee:
Intel Corporation
Inventors:
Mark Bordogna, Janardhan Satyanarayana, Yoni Landau, Diwakar Suvvari
Abstract: A transmitter, a receiver and methods therein, configured to transmit a first type of synchronisation signal, in M1 symbols li,, 0?i?(M1?1) and a second type of synchronisation signal in M2 symbols kj,, 0?j?(M2?1) of a subframe, wherein M2?M1?2. The transmitter comprises a processor, configured to determine in which symbols li the synchronisation signal of the first type is to be transmitted, and in addition configured to calculate in which symbols kj, the synchronisation signal of the second type is to be transmitted, by placing each of the M2 symbols kj at a symbol distance from an associated symbol li. The transmitter also comprises a transmitting circuit configured to transmit the synchronisation signals of the first type in the M1 symbols li, and transmitting the synchronisation signals of the second type in the M2 symbols kj.
Abstract: A method of synchronizing signals is disclosed. The method comprises using a clock tracking system to convert a future event target time specified in a time base of a master device into the local unsynchronized time bases of one or more slave devices. Each of the slave devices then generates an event signal at the converted time, such that a coordinated delivery of synchronized signals is achieved.
Abstract: The disclosure describes methods and systems for performing time synchronization in a heterogeneous system. In one example, a method includes evaluating, by a computing system, one or more network conditions of a network to determine whether to perform a time synchronization process with a secondary device in the network, wherein the one or more network conditions include a health score for the secondary device, and, in response to determining, based on the evaluation of the one or more network conditions, to perform the time synchronization process: determining based at least in part on a time indication for a clock on a master device and a time indication for a clock on the secondary device, a time synchronization offset for the secondary device; and sending the time synchronization offset for the secondary device to the secondary device in a data packet.
Abstract: Systems and methods for processing inbound and outbound secure packet traffic are provided herein. A first lookup operation can be performed to identify a security association corresponding to a received packet. A second lookup operation can be performed to determine a security parameters index associated with the packet and the identified security association. The packet can be processed in accordance with the security association and the security parameters index.
Abstract: Some embodiments provide a method of identifying packet latency in a software defined datacenter (SDDC) that includes a network, several host computers executing several machines, and a set of one or more controllers. At the set of controllers, the method o receives, from a set of host computers, (i) a first set of time values associated with multiple packet processing operations performed on packets sent by a set of machines executing on the set of host computers and (ii) a second set of time values associated with packet transmission between host computers through the SDDC network. The method processes the first and second sets of time values to identify a set of latencies experienced by multiple packets processed and transmitted in the SDDC.
Type:
Grant
Filed:
March 2, 2020
Date of Patent:
February 1, 2022
Assignee:
VMWARE, INC.
Inventors:
Haoran Chen, Ming Shu, Xi Cheng, Feng Pan, Xiaoyan Jin, Caixia Jiang, Qiong Wang, Qi Wu
Abstract: A method for transporting Ethernet frame packets assembled from a constant bit rate (CBR) client stream from an ingress network node to an egress network node, each Ethernet frame packet including a payload region having a number of bytes of CBR client data from the CBR client stream determined by a client rate value of the CBR client stream. The method including synchronizing a reference clock signal and a ToD in the ingress network node to a packet-based time distribution mechanism, independently synchronizing a reference clock signal and a ToD in the egress network node to the packet-based time distribution mechanism, for an Ethernet frame packet assembling a presentation time packet including a sequence number and a presentation ToD for the Ethernet frame packet, and transmitting the Ethernet frame packets and the presentation time packet to the egress network node over the packet transport network.
Abstract: Methods, systems, and devices for wireless communications are described. In an example, a method includes a first node receiving a precision time protocol (PTP) message, identifying one or more timing domains to be supported by the first node based at least in part on the PTP message, and sending, to a second node of the wireless communication network, an indicator of the one or more timing domains to be supported by the first node. Another example at a node includes receiving, from additional nodes of the wireless communication network, indicators of one or more timing domains supported by the additional nodes, receiving a PTP message associated with a timing domain, and sending the PTP message to a subset of the additional nodes based at least in a part on the indicators of one or more timing domains supported by the additional nodes.
Type:
Grant
Filed:
February 14, 2020
Date of Patent:
January 18, 2022
Assignee:
QUALCOMM Incorporated
Inventors:
Vinay Joseph, Rajat Prakash, Peerapol Tinnakornsrisuphap, Fatih Ulupinar
Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.
Abstract: A method for transmitting a data stream containing a second ordered sequence of numerical values, which sequence is determined from a first ordered sequence, a second succession of consecutive numerical values of the second sequence being obtained from a corresponding succession of consecutive numerical values of the first sequence. The method estimates a load value representative of a current load on the network, to determine, depending on the estimated value, a second succession to be transmitted in a predefined time interval following the current time, the second succession being a corresponding first succession of the first sequence or a succession modified by applying a selection law to the bits of the first succession and to transmit the second succession and, in case of transmission of a modified succession, a processing indicator signaling a succession modification.
Type:
Grant
Filed:
June 14, 2018
Date of Patent:
December 28, 2021
Assignee:
ORANGE
Inventors:
Apostolos Kountouris, Philippe Surbayrole, Marion Dumay
Abstract: A reflector structure for a tunable laser and a tunable laser. A super structure grating is used as a reflector structure, and a suspended structure is formed around a region in which the super structure grating is located, to implement, using the suspended structure, thermal isolation around the region in which the super structure grating is located, and increase thermal resistance, such that less heat is lost, and heat is concentrated in the region in which the super structure grating is located, thereby improving thermal tuning efficiency of the reflector structure. Moreover, lateral support structures are disposed on two sides of the suspended structure, to provide a mechanical support for the suspended structure. In addition, regions in the super structure grating that correspond to any two lateral support structures on a same side of the suspended structure fall at different locations in a spatial period of the super structure grating.
Abstract: Continuance in quality level of an input timing signal may be provided. Clock source reference timing information may be receive by a first node from a second node as an input. The first node may be downstream from the second node. Then the first node may receive an event message associated with a future event associated with the second node. The first node may then refrain, for a period of time in response to receiving the event message, from switching the input for clock source reference timing information to a source other than the second node.
Abstract: A high-speed data-plane packet aggregation and disaggregation method is disclosed. The method includes following steps: receiving a plurality of packets by the P4 switch; parsing each of the plurality of packets by using a parse graph; determining the type of the packets by using a match-action table; conducting packet aggregation and disaggregation process at the pipeline of the P4 switch; and transmitting the aggregated packet or the original data packet to a deparser of the P4 switch and outputting the aggregated packet or the original data packet by the P4 switch.
Type:
Grant
Filed:
April 3, 2019
Date of Patent:
November 30, 2021
Assignee:
NATIONAL CHIAO TUNG UNIVERSITY
Inventors:
Shie-Yuan Wang, Chia-Ming Wu, Yi-Bing Lin, Jun-Yi Li
Abstract: A communication device 2 according to the present disclosure includes (i) a synchronization signal receiver 203 to receive a synchronization signal from a master device 1 that has a reference time and transmits the synchronization signal every synchronization period, (ii) a synchronization signal determiner 210 to determine whether the synchronization signal is normal or abnormal, (iii) a synchronization processor 211 to perform, when the synchronization signal is determined to be normal by the synchronization signal determiner, synchronization processing based on the synchronization signal determined to be normal, and (iv) an additional transmission requester 214 to request the master device to additionally transmit the synchronization signal before transmitting the synchronization signal during a next period when the synchronization signal is determined to be abnormal by the synchronization signal determiner.
Abstract: The present disclosure relates to a time division duplexing (TDD) sub-system of a distributed antenna system using a TDD mode. According to the present disclosure, a head-end unit of a distributed antenna system using a division duplexing mode has a TDD sub-system which includes a TDD sync detection module, a TDD sync replica module, a TDD sync self delay detection module, and a TDD sync operator delay detection module, whereby quickly detecting possible errors in the system operation, and more efficiently performing responsive servicing thereto.
Abstract: A packet processing apparatus includes a plurality of queues that store received packets according to types of the received packets; and a processor coupled to the plurality of queues and configured to: collect information on packet quantity of received packets in each time slot, identify a periodicity pattern of the received packets based on the packet quantity of the received packets in each time slot, based on the identified periodicity pattern of the received packets, identify a time slot section where received packets of a predetermined type are to be outputted preferentially, and control opening and closing of each of the plurality of queues in the identified time slot section.
Abstract: The present disclosure relates to an electronic apparatus. The electronic apparatus includes a signal receiving unit that may receive a video signal; an interface unit that may communicates with a security processing module; a signal processing unit; and a processor that transmits first data of the video signal received by the signal receiving unit to the security processing module through the interface unit and receives secured second data from the security processing module, controls the signal processing unit to process the received second data for displaying a video, identifies whether continuity of processing of second data by the signal processing unit is limited based on a ratio of a transmission amount of the first data and a transmission amount of the second data transmitted and received between the interface unit and the security processing module, and performs subsequent processing according to the identification.
Abstract: Clock-data timing in a multi-lane serial data communication link may be adjusted to compensate for drift. A reference lane may be selected and periodically trained to adjust clock-data timing. In response to initiation of a first lane transitioning from an active state to an inactive state, first information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. Then, in response to initiation of the first lane transitioning back from the inactive state to the active state, second information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. The clock-data timing of the first lane may be adjusted based on the first information and the second information.
Abstract: A method, device, and system for receiving a downlink signal is provided. The method includes: detecting a Channel State Information Reference Signal (CSI-RS) in a time unit #n on an unlicensed band cell; verifying whether the CSI-RS is used for Discovery RS (DRS) using an initialization value of a CSI-RS sequence of the CSI-RS; and performing a Radio Resource Management (RRM) measurement when the CSI-RS is used for the DRS. The CSI-RS is used for the DRS when an index of the time unit #n is not used for the initialization value of the CSI-RS sequence.
Type:
Grant
Filed:
July 10, 2020
Date of Patent:
August 24, 2021
Assignee:
Beijing Xiaomi Mobile Software Co., Ltd.
Abstract: A wireless customizable referee paging system is disclosed. The system includes at least two flag signaling components, each flag signaling component having an electronic signature to send a unique flag signal based on a flag user's input for that flag signaling component. The system includes a central receiving component that receives the unique flag signal from each flag signaling component and then alerts a central user to receipt of the unique flag signal. The flag signaling components and the central receiving component each having a Bluetooth® radio circuit and thereby the flag signaling components communicate with the central receiving component substantially exclusively via Bluetooth® technology. The flag signaling components and the central receiving component each have a pairing-mode and a signaling-mode. The pairing-mode uniquely pairs each flag signaling component to the central receiving component.
Abstract: Systems and methods for video distribution synchronization are described herein. An example method to distribute a media stream over a distribution network to a number of devices may include determining, by one or more computer processors coupled to memory, a common master-client shared time reference Tref. Example methods may include determining a mean intermediate arrival time for first packets of a first type of the media stream, determining respective first playout times for the first packets based on the mean intermediate arrival time and the time reference Tref, associating the first packets with the respective first playout times, and distributing the media stream to the plurality of devices.
Type:
Grant
Filed:
February 21, 2020
Date of Patent:
August 17, 2021
Assignee:
Amazon Technologies, Inc.
Inventors:
Per Lindgren, Ted Olsson, Anders Cedronius, Hans Insulander, Christer Bohm, Magnus Danielson
Abstract: In one embodiment, a computer apparatus includes a first NIC including at least one network interface port to transfer data with a first packet-data network (PDN) including a master clock to provide a clock synchronization signal S1, a first physical hardware clock (PHC) to maintain a time value T1 responsively to S1, and a first clock controller to generate a clock synchronization signal S2 responsively to S1, S2 having a frequency set responsively to S1, and send S2 over a connection to a second NIC including at least one network interface port to transfer data with a second PDN, a second PHC, and a second clock controller to receive S2, update the second PHC with a time value T2 responsively to S2, send another clock synchronization signal to network nodes in the second PDN responsively to T2, the second NIC acting as a master clock in the second PDN.
Type:
Grant
Filed:
February 25, 2020
Date of Patent:
July 20, 2021
Assignee:
MELLANOX TECHNOLOGIES, LTD.
Inventors:
Dotan David Levi, Liron Mula, Avraham Ganor, Avi Urman, Aviad Raveh, Yuval Itkin, Oren Matus
Abstract: There is provided a transmission device including circuitry configured to generate a physical layer frame. A time information descriptor is included in a preamble of the physical layer frame. The time information descriptor includes a time information flag that indicates presence or absence of time information in the time information descriptor. The circuitry is configured to transmit the physical layer frame including the preamble and a payload. The time information indicates a time of a predetermined position in a stream of the physical layer frame.
Type:
Grant
Filed:
September 30, 2019
Date of Patent:
July 6, 2021
Assignee:
Saturn Licensing LLC
Inventors:
Kazuyuki Takahashi, Lachlan Bruce Michael
Abstract: A network device receives a packet that conforms to a protocol that i) defines a time stamp field, ii) does not define a dedicated field for time correction information, and iii) defines a plurality of general purpose extension fields. The packet includes (i) a time stamp generated by a source node in the time stamp field, and (ii) a time correction value corresponding to multiple ones of the plurality of intermediate nodes, the time correction value being located in one of the general purpose extension fields. The network device identifies (i) a time specified by the time stamp, and (ii) time correction information specified in the one general purpose extension field, and uses the time correction information and the time specified by the time stamp to synchronize a clock maintained by the network device to a clock maintained by the source node.
Abstract: An electronic device, method, and computer program product provide an asynchronous quick connection or reconnection between wireless connecting devices for low-latency transitions in presentation of content to a user. A first device transmits an out-of-band frame sync signal to a second device to prompt the second device to synchronize clocks with the first device and to one of: (i) connect; and (ii) reconnect an over-the-air (OTA) communication session with the first device. First and second devices establish the OTA communication session. The establishment is expedited by the out-of-band frame sync signal. First device transmits output data, via the in-band OTA session, by the first device to the second device to present the output data on a second user output device of the second device.
Abstract: An example method for initializing an interface includes driving a low voltage signal on data lanes and clock lanes. The method further includes performing a reset sequence and an initialization of a link configuration register. The method also includes driving a high voltage signal to the clock lanes and the data lanes. The method further includes driving a bus turn-around (BTA) sequence on the data lanes. The method also includes detecting that the BTA is acknowledged by a host controller.
Type:
Grant
Filed:
January 22, 2019
Date of Patent:
June 29, 2021
Assignee:
Intel Corporation
Inventors:
Zhenyu Zhu, Nobuyuki Suzuki, Anoop Mukker, Daniel Nemiroff, David W. Vogel
Abstract: Provided is an accurate load shedding system and method based on a power-dedicated wireless network. The system includes: a control master station layer, a control substation layer and a terminal user access layer. The control master station layer includes a control master station apparatus and an optical/E1 conversion device. The control substation layer includes an optical/E1 conversion device, a control substation apparatus and a wireless access device. The terminal user access layer includes a wireless core network, a base station and a control terminal. The wireless access device is connected to the wireless core network through Ethernet. The wireless core network is connected with the base station through an optical fiber. The control terminal is connected to a wireless network of the base station through customer premise equipment (CPE).
Type:
Grant
Filed:
May 10, 2019
Date of Patent:
June 22, 2021
Assignees:
State Grid Jiangsu Electric Power Co., Ltd., Nari Technology Co., Ltd.
Abstract: A method of protecting against two or more board failures at the same time by providing an elastic consistency platform (ECP) of high availability (HA) in multiple board environments is described. The ECP is provided between transmission control protocol (TCP) and an application using TCP on each board, including providing input and output buffers to store data between a producer and a consumer. The ECP is used to generate a warning when an amount of data unsynchronized in an output buffer of the ECP on any board reaches a programmable limit.
Abstract: Embodiments of the disclosure pertain to activating in-band OAM based on a triggering event. Aspects of the embodiments are directed to receiving a first notification indicating a problem in a network; triggering a data-collection feature on one or more nodes in the network for subsequent packets that traverse the one or more nodes; evaluating a subsequent packet that includes data augmented by the data collection feature; and determining the problem in the network based on the data augmented to the subsequent packet.
Type:
Grant
Filed:
April 3, 2020
Date of Patent:
June 15, 2021
Assignee:
CISCO TECHNOLOGY, INC.
Inventors:
David D. Ward, Carlos M. Pignataro, Frank Brockners, Shwetha Subray Bhandari
Abstract: A communication system may include a plurality of geographically proximate nodes that communicate via one or more range-limited wireless technologies such as BLUETOOTH® low energy (BLE). An origin node may generate and communicate a first message responsive to detecting an event occurrence. The message may include an identifier associated with the origin node, data indicative of the event occurrence, a hop count, a maximum hop count, and a number of designated recipient nodes within the communication system. A first designated recipient node may, upon receiving the first message, attempt to confirm the event occurrence included in the first message. Upon confirming the event occurrence, the first designated recipient node may communicate a notification to an external third party. If unable to confirm the event occurrence, the first designated recipient node may generate and communicate a second message to a second designated recipient node included in the first message.
Type:
Grant
Filed:
June 27, 2016
Date of Patent:
June 8, 2021
Assignee:
Intel Corporation
Inventors:
Cory J. Booth, Adam Jordan, Michael J. Payne, Alexandra C. Zafiroglu, Joshua Ekandem, Jasmeet Chhabra
Abstract: A system and method for detection and management of atypical synchronization sessions of electronic content. The system is configured to determine whether a pending or ongoing synchronization session between a client device and cloud storage service is associated with a condition that will delay the synchronization process. The proposed system and method can significantly improve the ability of users to safeguard their documents as well as reduce the likelihood of data loss.
Type:
Grant
Filed:
July 16, 2018
Date of Patent:
June 8, 2021
Assignee:
Microsoft Technology Licensing, LLC
Inventors:
Jose Araujo Barreto, Filip Chelarescu, Andrew Keith Glover, John David Rodrigues, Meir Elie Abergel, Steven J. Bailey
Abstract: In some embodiments, a first computing device detects a loss of a connection to a first source of timing information that the first computing device and a second computing device use to maintain synchronization with a first clock and a second clock. The first computing device receives a second source of timing information from the second computing device. The second source of timing information is also being transmitted to a third computing device. The first computing device uses the second source of timing information to determine a first timestamp and determines a second timestamp from the first clock. The first computing device uses the first timestamp and the second timestamp to adjust a rate of the first clock where the first clock is used to transmit the second source of timing information from the second computing device to the third computing device.
Abstract: This invention relates to end-to-end transparent clocks and methods of estimating skew in end-to-end transparent clocks. Embodiments of the invention relate to techniques for estimating clock skew between a free-running clock in a transparent clock and a master clock, in particular by using the timing information embedded in timing messages passing through the transparent clock. Further embodiments of the invention set out uses of these estimates to modify the residence times computed by the transparent clock and a synchronization network including such transparent clocks.
Type:
Grant
Filed:
July 16, 2018
Date of Patent:
May 25, 2021
Assignees:
Khalifa University of Science and Technology, British Telecommunications plc, Emirates Telecommunications Corporation
Abstract: A smart grid timing synchronization method, a smart grid timing synchronization system, a smart grid timing synchronization device and a computer readable storage medium are provided, which is applied to any synchronization device in a smart grid. The method includes: determining whether a clock frequency of a synchronization device is consistent with a preset fixed frequency, and if not, regulating the clock frequency of the synchronization device to be consistent with the preset fixed frequency. The synchronization device includes a communication device and a central coordinator.
Abstract: Aspects of the embodiments are directed to calibrating a cross-talk cancellation module. A data eye response for a first data channel can be acquired, and the left-side and right-side maximum transition edges can be determined while adjacent data channels are silent. The adjacent data channels can be activated, first using an even mode waveform. A strobe can be positioned at the left-side maximum boundary in anticipation of a right-shift due to even mode waveform cross talk. A summer circuit can sum the waveform from the first data channel with cross-talk induced voltage pulse having an opposite polarity from the even mode waveforms on the aggressor channels. A left-side edge can be determined by incrementally adjusting gain and detector parameters. These parameters can be locked once a left-side transition edge is located. The process can be repeated for a right-side transition edge with odd-mode aggressor waveforms.
Type:
Grant
Filed:
December 30, 2016
Date of Patent:
May 25, 2021
Assignee:
Intel Corporation
Inventors:
Chenchu Punnarao Bandi, Amit Kumar Srivastava
Abstract: A network device may receive a timing control packet from a first client device. The network device may determine that the network device is in a synchronized state relative to a network grandmaster clock. The network device may modify a first field of a header of the timing control packet to indicate that the network device is in a synchronized state. The network device may modify a second field of the header of the timing control packet to indicate a time at which the network device received the timing control packet from the first client device. The network device may forward, via the network, the timing control packet toward a second client device.
Type:
Grant
Filed:
January 31, 2020
Date of Patent:
May 11, 2021
Assignee:
Juniper Networks, Inc.
Inventors:
Kamatchi S. Gopalakrishnan, Rajagopalan Subbiah, Julian Kazimierz Lucek
Abstract: A method of driving a display panel includes: correcting a gate-source voltage of a first transistor to cause the gate-source voltage of a first transistor to become closer to a threshold voltage of the first transistor; and writing a signal voltage into a gate of the first transistor by applying a plurality of voltage pulses to a gate of a second transistor. The correcting and the writing are performed in each of pixels of the display panel. The signal voltage corresponds to an image signal. The voltage pulses applied in the writing include a first voltage pulse and a second voltage pulse. The first voltage pulse is applied previous to the second voltage pulse. The second voltage pulse is applied subsequent to the first voltage pulse. A peak value of the first voltage pulse is higher than a peak value of the second voltage pulse.
Abstract: The disclosed techniques can collect and transport telemetry information on-path when a packet of a service flow traverses a communication network. The collected telemetry information can be analyzed to identify potential issues experienced by a user of a service and simplify the association of data with the service. Thus, apparatuses, methods, computer readable media, and systems are disclosed for an on-path collection and transportation of telemetry information in a communication network.
Abstract: There is provided a method in a communication network system of e.g. IP type for live distribution of media content capable of node-to-node time-transfer for synchronizing a respective local clock of an originating server and at least one client device or other server by means of two-way time transfer. The media content is sent as a data stream using unicast or multicast via respective communication links over a network. The method comprises employing a mode in which two-way time transfer is selectively provided, selectively meaning that two-way time transfer is employed such that the amount of per client specific time information being exchanged by the server and client devices is controlled, e.g. by time limiting the two-way time transfer, or during that mode reducing the occurrence of full two-way time transfer based synchronization of the client devices.
Abstract: A frame trigger recreation method is provided. Said frame trigger recreation method comprises the steps of generating a periodic trigger on the basis of a receiver clock with at least one period adjustment and at least one offset based on a difference between the receiver clock and a transmitter clock.
Abstract: An apparatus and method for speech communication is described. An audio transmit processor captures at least two audio signals from an audio source, and processes the at least two audio signals to provide a mono audio signal and a non-audio signal comprising spatial information representative of the direction of the audio source. The audio transmit processor combines the non-audio signal with the mono audio signal by watermarking; and transmits the watermarked audio signal. An audio receive processor receives a watermarked audio signal and extracts a mono audio signal and a non-audio signal comprising spatial information from the watermarked audio signal. The audio receive processor processes the mono audio signal and spatial information to generate at least two output audio signals.
Abstract: Systems, apparatuses, and methods are described for auto-discovery of port-to-port connectivity through correlative analysis on performance metrics. Statistical data corresponding to each port of routers and transport devices may be collected. The collected data may be processed such that missing data may be patched and time frames may be aligned. Statistical analysis may be performed on the collected data. Such statistical analysis may comprise generating a waveform based on the data and determining, e.g., correlations in the data. If the analyzed data of one port matches analyzed data of another port, the two ports may be determined to be connected to one another. A match may be based on meeting various criteria and/or thresholds.
Type:
Grant
Filed:
January 11, 2019
Date of Patent:
March 23, 2021
Assignee:
Comcast Cable Communications, LLC
Inventors:
Balasubramanian Ramachandran, Eric Frishman, Mannan Venkatesan
Abstract: Embodiments are provided for syncing multiple electronic devices for collective audio playback. According to certain aspects, a master device connects (218) to a slave device via a wireless connection. The master device calculates (224) a network latency via a series of network latency pings with the slave device and sends (225) the network latency to the slave device. Further, the master devices sends (232) a portion of an audio file as well as a timing instruction including a system time to the slave device. The master device initiates (234) playback of the portion of the audio file and the slave devices initiates (236) playback of the portion of the audio file according to the timing instruction and a calculated system clock offset value.
Type:
Grant
Filed:
July 6, 2018
Date of Patent:
March 16, 2021
Assignee:
GOOGLE TECHNOLOGY HOLDINGS LLC
Inventors:
Michael J. Daley, Travis Bolinger, Heath O'Neal
Abstract: A synchronization method is suitable between a first electronic apparatus and a second electronic apparatus. The synchronization method include following steps. A first interrupt signal is generated to trigger a first timer on the first electronic apparatus. A radio frequency packet is transmitted from the first electronic apparatus to the second electronic apparatus. In response to that the radio frequency packet is received by the second electronic apparatus, a second interrupt signal is generated to trigger a second timer on the second electronic apparatus. The second timer is synchronized with the first timer or a timestamp of the first timer is estimated according to the second interrupt signal and the radio frequency packet.
Abstract: The time of transmission and reception between stations A and B is exchanged, and any deviation in time is calculated in a corresponding manner in the stations.
Type:
Grant
Filed:
January 18, 2017
Date of Patent:
March 9, 2021
Assignee:
NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY
Inventors:
Nobuyasu Shiga, Masugi Inoue, Satoshi Yasuda, Kohta Kido
Abstract: A transmitter circuit for use in a source synchronous type interface includes a flip-flop having a data input configured to receive serial data, a clock input configured to receive a source clock and a data output coupled to a data line. A first multiplexer has a first input configured to receive the source clock, a second input configured to receive a phase shifted clock (shifted by ninety degrees from the source clock), and a clock output coupled to a clock line. A control circuit operates to control selection by the first multiplexer of the source clock as a transmit clock sent over the clock line for a delay on clock at destination implementation. Alternatively, the control circuit causes selection by the first multiplexer of the phase shifted clock as the transmit clock sent over the clock line if the system is configured for a delay on clock at source implementation.