Abstract: A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer, floating gate layer, inter-layer dielectric and mask layer across all regions of the substrate. Subsequently these layers are removed from the peripheral regions and dielectrics of different thicknesses are formed in the peripheral regions according to the voltages of the circuits in these regions. A conductive layer is formed over the memory array and the peripheral circuits to form control gates in the memory array and form gate electrodes in the peripheral regions.

Abstract: A manufacturing method for a transistor of an ESD protection device. First, the method forms basic elements on a semiconductor base. Next, a patterned resist layer is used as a mask to perform ion implantation in the emerged drain region so that the dopant can be implanted into the semiconductor base under the drain region to form an extended drain heavy-doped region. Then, the patterned resist layer is removed and a heat tempering processing is performed. Finally, a self-aligned salicide is formed on the surfaces of the polysilicon gate and the heavy-ion doped region. The invention utilizes an extended drain heavy-doped region as a resistance ballast between the drain contact and the polysilicon contact surface, which allows high current generated by ESD to be discharged in a more homogeneous way so as to prevent the ESD structure from being damaged.

Abstract: Disclosed herein is a method for fabricating a memory device. According to the present invention, a device isolation film is etched using a mask partially exposing a channel region and the device isolation film adjacent thereto during the etching process of the recess gate region, and a semiconductor substrate in the recess gate region is etched. Accordingly, a silicon horn in the recess gate region is prevented from being formed, thereby increasing a margin of the etching process.

Abstract: The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).

Abstract: A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is laterally removed adjacent the source/drain regions in order to form recesses, which are subsequently filled with a material that is appropriate for charge-trapping. The device structure and production method are appropriate for an integration scheme comprising local interconnects of memory cells, a CMOS logic periphery and means to compensate differences of the layer levels in the array and the periphery.

Abstract: A memory function body has a medium interposed between a first conductor (e.g., a conductive substrate) and a second conductor (e.g., an electrode) and consisting of a first material (e.g., silicon oxide or silicon nitride). The medium contains particles. Each particle is covered with a second material (e.g., silver oxide) and formed of a third material (e.g., silver). The second material functions as a barrier against passage of electric charges, and the third material has a function of retaining electric charges. The third material is introduced into the medium by, for example, a negative ion implantation method.

Abstract: A method of forming an integrated circuit employable with a power converter. In one embodiment, the method of forming the integrated circuit includes forming a transistor employable as a switch of a power train of the power converter by forming a gate over a semiconductor substrate. The method of forming the transistor also includes forming a source/drain by forming a lightly doped region adjacent a channel region recessed into the semiconductor substrate, forming a heavily doped region adjacent the lightly doped region, and forming an oppositely doped well within the channel region. The method of forming the transistor further includes forming a doped region with a doping concentration profile less than the heavily doped region between the heavily doped region and the oppositely doped well. The method of forming the integrated circuit also includes forming a driver switch of a driver to provide a drive signal to the transistor.

Abstract: A semiconductor device is provided with a FET having a sufficiently small short channel effect and sufficiently small junction capacitance and junction leakage current. The FET includes a channel region formed in a silicon substrate, a gate electrode formed on the channel region through the intermediary of a gate insulting film, heavily doped regions, and pocket regions. The pocket regions are formed to extend from inside the heavily doped regions, respectively, over inside the channel region. Because a pocket sub-region inside the respective heavily doped regions is formed to be located in regions shallower than the respective lower end faces of the heavily doped regions, junction capacitance and junction leakage current are reduced. Further, because respective pocket sub-regions inside the channel region are formed in regions deeper than the respective pocket sub-regions inside the heavily doped regions, a short channel effect can be reduced.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.

Abstract: A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.

Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.

Abstract: Fabrication of metallic or non-metallic wires with nanometer widths and nanometer separation distances without the use of lithography. Wires are created in a two-step process involving forming the wires at the desired dimensions and transferring them to a planar substrate. The dimensions and separation of the wires are determined by the thicknesses of alternating layers of different materials that are in the form of a superlattice. Wires are created by evaporating the desired material onto the superlattice that has been selectively etched to provide height contrast between layers. The wires thus formed upon one set of superlattice layers are then transferred to a substrate.

Abstract: Active pixel sensors are defined on double silicon on insulator (SOI) substrates such that a first silicon layer is selected to define radiation detection regions, and a second silicon layer is selected to define readout circuitry. The first and second silicon layers are separated by an insulator layer, typically an oxide layer, and the layers can be independently doped. Doping can be provided in the silicon layers of the SOI substrate during assembly of the SOI substrate, or later during device processing. A semiconductor substrate that supports the first and second layers can be removed for, for example, back side radiation detection, using a second insulator layer (typically an oxide layer) as an etch stop.

Abstract: A method of fabricating a thin film germanium photodetector includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion of the germanium substrate from the bonded structure; forming a PIN diode in the germanium substrate; removing a portion of the germanium layer by etching; and completing the germanium photo detector.

Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

Abstract: Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. A least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices.

Abstract: The present invention relates to an isolation layer for CMOS image sensor and a fabrication method thereof, which are capable of improving a low light level characteristic of the CMOS image sensor. The isolation layer includes: a field insulating layer formed on a predetermined portion of a substrate in the logic area to thereby define an active area and a field area; a field stop ion implantation area formed on a predetermined portion of the substrate in the pixel area, the field stop ion implantation area having a predetermined depth from a surface of the substrate to define an active area and a field area; and an oxide layer deposited on a substrate surface corresponding to the field stop ion implantation area.

Abstract: A method for manufacturing a complementary metal-oxide semiconductor sensor is provided. The present method provides a semiconductor structure including a plurality of conductors thereon. An inter-metal dielectric layer is formed on the conductors. A silicon nitride film is applied on the inter-metal dielectric layer. An oxide layer is formed on the silicon nitride film. The oxide layer, the silicon nitride film and the inter-metal dielectric are etched to expose portions of the conductors. The oxide layer and the exposed conductors are cleaned in a cleaning step later.

Abstract: The fabrication an NMOS device featuring a shallow source/drain region, performed as part of an integrated process sequence employed to integrate the fabrication of other type devices with the fabrication of the NMOS device, has been developed. A critical feature of the integrated process sequence is the formation of the shallow source/drain region of the NMOS accomplished after formation of the other type devices, thus reducing the risk of exposure of the shallow source/drain region to possible damaging procedures used for the other type devices. In addition the process used to remove a photoresist shape, used to protect the completed other type devices from the shallow source/drain ion implantation procedure, has been modified again to reduce possible damage to the shallow source/drain region.

Abstract: An electro-optical device is provided having a pixel portion with a novel structure, and in which display irregularities such as crosstalk, which develop due to a drop in voltage caused by the wiring resistance of electric current supply lines in an electro-optical device, are improved upon. Attention is drawn to the fact that during a period in which write in of a signal to a pixel from a signal line is not performed, a signal is not input to a source signal line and to a gate signal line, but are at a fixed electric potential. An electric current supply line and a source signal line, or an electric current supply line and a gate signal line, are connected through a switching transistor. A signal is input to a connection control line during a sustain period, and the connection transistor is made conductive. The source signal line or the gate signal line is therefore utilized as a pathway for supplying electric current to the EL element.

Abstract: It is known to bring the surface into the inverted state in CCD imaging devices with buried channels during the integration period in order to keep the dark current low (All Gates Pinning). A desired potential profile, with wells in which the charge is integrated bounded by potential barriers, is obtained through, e.g. a doping profile in the channel. Line-shaped constrictions in the thickness or the doping concentration of the well enable charge-reset and function also as an anti-blooming barrier. In a charge coupled device according to the invention, the line-shaped constrictions in the thickness or the doping concentration of the second layer run perpendicular to the length direction of the channel and parallel to the gates and at least one line shaped constriction is positioned below each series of gates. In this way, an increased charge storage capacity and optical sensitivity are obtained while electronic shutter functionality is maintained.

Abstract: A method of forming a semiconductor device includes fabricating digital circuits comprising a programmable logic circuit on a substrate; selectively fabricating either a memory circuit or a conductive pattern substantially above the digital circuits to program said programmable logic circuit; and fabricating a common interconnect and routing layer substantially above the digital circuits and memory circuits to connect digital circuits and one of the memory circuit or the conductive pattern.

Abstract: In a method for fabricating a semiconductor device including a PIP capacitor and a MOS transistor, an isolator film is formed on a semiconductor substrate and then etched to expose an active region of the substrate. An epitaxial film is then formed by performing a selective epitaxial silicon growth process on the active region. A first polysilicon film, a dielectric film and a second polysilicon film are then sequentially formed. Next, an upper electrode is created by patterning the second polysilicon film. After a lower electrode and a gate electrode are formed by patterning the first polysilicon film, a source and a drain of a source/drain region are formed into the epitaxial film. Subsequently, after an interlayer insulation film is created on a resultant structure, contact holes are formed thereinto and contacts connected to the upper electrode, the lower electrode, the gate electrode and the source/drain region are formed.

Abstract: A high-voltage device structure disposed in a substrate of a first conductivity type includes a first well and a second well each of a second conductivity type, a source diffusion region and a drain diffusion region each of a first length located in the first well and the second well respectively, and a gate of a second length on the substrate surface. Since the gate of the second length is longer than the source diffusion region and the drain diffusion region of the first length, the two sides of the gate have two spare regions. Two windows are located in the spare regions.

Abstract: A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e.g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e.g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.

Abstract: A nonvolatile semiconductor memory device having a small layout area includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The memory cell array includes source line diffusion layers, each of the source line diffusion layers extending along the row direction and connecting in common with the memory cells arranged in the row direction, bitline diffusion layers, element isolation regions which separate each of the bitline diffusion layers, and word gate common connection sections. Each of the memory cells includes a word gate and a select gate. One of the bitline diffusion layers is formed between two word gates adjacent in the column direction Y. Each of the word gate common connection sections is connected with the two word gates above one of the element isolation regions.

Abstract: An active matrix organic electroluminescent display device of the present invention is fabricated through a six-mask process unlike the related art that uses eight masks. In the present invention, since the ground line and the power line are entirely disposed above the substrate, the resistance of the power line is reduced and the thermal damage that may occur in the power line during driving the device is prevented. Therefore, the image quality increases and the uniformity in the display can be obtained. Furthermore, due to the reduction of the mask process, the occurrence of defects is reduced and the production yield can be raised. Additionally, the principles of the present invention can be applied to either the top emission type organic electroluminescent display device or the bottom emission type organic electroluminescent display device. When it is utilized for the top emission type, the active matrix organic electroluminescent display device can have a high aperture ratio.

Abstract: A method for producing a solid-state imaging device comprising a plurality of unit pixel sections, including a first unit pixel section, is provided. The method includes the steps of forming a first conductivity type well region of the first unit pixel section on a second conductivity type semiconductor layer provided on a first conductivity type semiconductor layer, the first conductivity type well region including a light receiving region for generating charges corresponding to an amount of light incident thereon and a charge transfer region capable of transferring the charges; and generating a charge accumulation region, for accumulating the charges generated in the light receiving region, in the charge transfer region. The step of forming the first conductivity type well region includes the step of implanting impurities such that the light receiving region and the charge transfer region in the first conductivity type well region have a substantially uniform impurity concentration.

Abstract: The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in standard technology along with the tinier memory cell transistors.

Abstract: First to third logic circuits and first to third static random access memories (SRAMs) are formed on one chip. Power to the first and third logic circuits and their SRAMs is shut off as required, while power to the second logic circuit and its SRAM is kept supplied. The third SRAM has the largest memory capacity. The average channel width of the first to third SRAM cell arrays is set at a half or less of that of the other circuit blocks, and the channel impurity concentration of the second and third SRAM cell arrays, which operate at low speed, is set higher than that of the first SRAM cell array, which operates at high speed, by additional ion implantation. By these settings, MOS transistors of low threshold voltage (Vt) are provided for the first SRAM cell array, while MOS transistors of high Vt are provided for the second and third SRAM cell arrays for leakage reduction.

Abstract: The optical component includes a substrate made of a resin material, a silicon oxide film formed on a surface of the substrate, and a multilayer light reflection preventing film formed on the silicon oxide film, and having at least one layer of a low-refractive-index material and at least one layer of a high-refractive-index material being alternately formed. The silicon oxide film is thick and/or formed by introducing oxygen during film forming by vacuum deposition so that a preset elasticity is imparted to the silicon oxide film. Other optical component includes a substrate made of a resin material and a plurality of films formed by vacuum deposition, and directions of internal stresses in each adjacent pair of the plurality of films are different from each other or a thickness of an impurity existing on a surface of the substrate is 0.2 nm or less.

Abstract: The present invention relates to a method for fabricating a complementary metal oxide semiconductor (CMOS) image sensor. The method includes the step of: (a) forming a substrate of a first conductive type defined with a photodiode region and a native second conductive channel transistor region; and (b) forming a first conductive type impurity region by performing an ion-implantation process for forming a second conductive type channel stop region with a first conductive impurity ion, wherein the first conductive type impurity region is extended to the native second conductive type channel transistor region.

Abstract: In order to improve the performance of a semiconductor integrated circuit device wherein a capacitor provided between storage nodes of an SRAM and a device having an analog capacitor are formed on a single substrate, a plug is formed in a silicon oxide film on a pair of n channel type MISFETs in a memory cell forming area, and a local wiring LIc for connecting respective gate electrodes and drains of the pair of n channel type MISFETs is formed over the silicon oxide film and the plug. Thereafter, a capacitive insulating film and an upper electrode are further formed over the local wiring LIc. According to the same process step as the local wiring, capacitive insulating film and upper electrode formed in the memory cell forming area, a local wiring LIc, a capacitive insulating film and an upper electrode are formed over a silicon oxide film in an analog capacitor forming area and a plug in the silicon oxide film.

Abstract: An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.

Abstract: A mask read only memory (ROM) and a method of fabricating the same is provided. This mask ROM and related method is capable of reducing the pitch of buried impurity diffusion regions. In the mask ROM fabrication process, a gate insulation layer is formed over a semiconductor substrate, and parallel conductive layer patterns are formed on the gate insulation layer. These conductive layer patterns are separated from each other by a first predetermined interval and extend in the same direction. Ion implantation is then carried out using the conductive layer patterns as a mask to form buried impurity diffusion regions near the semiconductor substrate between the conductive layer patterns. A conductive layer for use in forming word lines is then formed over the entire surface of the resultant structure, and both the conductive layer and the conductive layer patterns are etched so as to form word lines and pad conductive layers.

Abstract: A method for manufacturing the semiconductor device of which a transistor and a MNOS type memory transistor, each of which has a different gate withstand voltage and drain withstand voltage, are included in the same semiconductor layer.

Abstract: The present invention relates to a method for fabricating a complementary metal-oxide semiconductor (CMOS) image sensor. Prior to forming an N-type ion implantation region and a first and a second P0-type ion implantation regions, an oxide layer and a nitride layer are sequentially formed on a substrate and are subsequently patterned to form a protective pattern structure with a specific arrangement with respect to a photodiode and a gate structure of a transfer transistor. Afterwards, the gate structure is formed on the substrate. In the existence of the protective pattern structure, an N-type ion implantation process for forming the N-type ion implantation region for use in the photodiode, a first P0-type ion implantation process for forming the first P0-type ion implantation region and a spacer formation process are consecutively performed. A second P0-type ion implantation process for forming the second P0-type ion implantation region is performed thereafter.

Abstract: A semiconductor device of the present invention includes a semiconductor layer 10, an insulation gate type heavy insulated transistor 200 and an insulation gate type light insulated transistor 300 having different drain-source breakdown voltages and formed on the semiconductor layer 10, and a resistive impurity layer 24 formed on the semiconductor layer 10.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage generator that selectively increases the voltage potential on the channel region of a transistor relative to the source region of the transistor. The voltage potential may be provided to a diffusion region in the well regions with transistors.

Abstract: A method for forming a silicon carbide film on a semiconductor substrate by plasma CVD includes: introducing a raw material gas containing silicon, carbon, and hydrogen, an inert gas, and optionally an hydrogen source gas, into a reaction chamber at a predetermined mixing formulation of the raw material gas to the inert gas; applying radio-frequency power at the mixing formulation, thereby forming a curable silicon carbide film having a dielectric constant of about 4.0 or higher; and continuously applying radio-frequency power at a mixing formulation reducing the raw material gas and the hydrogen source gas if any, thereby curing the silicon carbide film to give a dielectric constant and a leakage current lower than those of the curable silicon carbide film.

Abstract: An SRAM in a CMOS integrated circuit is subjected to stress on the channels of its transistors; compressive stress on the pull-up and pass gate transistors and tensile stress on the pull-down transistors in a version designed to improve stability; and compressive stress on the pull-up transistors and tensile stress on the pull-down and pass gate transistors in a version designed to reduce the cell size and increase speed of operation.

Abstract: An active pixel image sensor is formed on a P-type epitaxial layer on a P-type substrate. An active pixel array is in the P-type epitaxial layer. Each pixel includes an N-well functioning as a collection node, and a P-well adjacent the N-well. The P-well includes only NMOS transistors functioning as active elements. The in-pixel transistors cooperate with off-pixel PMOS transistors to form A-D converters.

Abstract: A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate 13. Each of the data storage cells includes a field effect transistor having a source 18, drain 22 and gate 28, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body 22 can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate 28 and the drain 22 and between the source 18 and the drain 22.

Abstract: A buried channel CMOS imager having an improved signal to noise ratio is disclosed. The buried channel CMOS imager provides reduced noise by keeping collected charge away from the surface of the substrate, thereby improving charge loss to the substrate. The buried channel CMOS imager thus exhibits a better signal-to-noise ratio. Also disclosed are processes for forming the buried channel CMOS imager.

Abstract: A bi-directional silicon controlled rectifier formed in a silicon layer and disposed over shallow trench isolations and therefore electrically isolated from the substrate to be insensitive to substrate noise for electrostatic discharge protection an electrostatic discharge protection device that includes a semiconductor substrate, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first p-type portion and the first n-type portion, a second n-type portion, a third p-type portion, a third n-type portion contiguous with the third p-type portion, and a fourth p-type portion contiguous with the third p-type portion and the third n-type portion, wherein at least one of the first p-type portion, second p-type portion, third p-type portion, fourth p-type portion, first n-type portion, second n-type portion, and third n-type portion overlaps the isolation structure.

Abstract: The present invention relates to a flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell. According to the present invention, a source region and a drain region are first formed and a tunnel oxide film is then formed. Therefore, it is possible to prevent damage of the tunnel oxide film due to an ion implantation process. Further, independent two channel regions are formed below the floating gate. Thus, it is possible to store data of two or more bits at a single cell. In addition, the tunnel oxide film, the floating gate and the dielectric film having an ONO structure are formed at a given regions. It is thus possible to reduce the steps of a process and improve an electrical characteristic and integration level of a device.

Abstract: A circuit adapted to dynamically activate an electro-optical display device is constructed from a thin-film gate-insulated semiconductor device. This device comprises PMOS TFTs producing only a small amount of leakage current. Besides the dynamic circuit, a CMOS circuit comprising both NMOS and PMOS thin-film transistors is constructed to drive the dynamic circuit.

Abstract: The invention encompasses methods of forming silicide interconnects over silicon comprising substrates. In one implementation, a first layer comprising a metal and a non-metal impurity is formed over a region of a silicon comprising substrate where a silicide interconnection is desired. An elemental metal comprising second layer is formed over the first layer. The substrate is annealed to cause a reaction between at least the elemental metal of the second layer and silicon of the substrate region to form a silicide of the elemental metal of the second layer. In another considered aspect, a method of forming a silicide interconnect over a silicon comprising substrate includes providing a buffering layer to silicon diffusion between a refractory metal comprising layer and a silicon containing region of a substrate.

Abstract: Certain embodiments of the present invention relate to a method for manufacturing a semiconductor device, in which, when a cell capacitor of a DRAM and a capacitor element in an analog element region are mix-mounted on the same chip, the manufacturing steps can be simplified. First, the lower electrodes 55a and 55b of the capacitor elements 600a and 600b, and the storage nodes 53a and 53b of the cell capacitors 700a and 700b are simultaneously formed. Next, a dielectric layer (ON layer 61) of the capacitor elements 600a and 600b, and a dielectric layer (ON layer 61) of the cell capacitors 700a and 700b are simultaneously formed. Then, the upper electrodes 69a and 69b of the capacitor elements 600a and 600b and the cell plate 67 of the cell capacitors 700a and 700b are simultaneously formed.

Abstract: Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.