Abstract: A process for integrating the fabrication of double diffused drain (DDD) MOSFET devices with the fabrication sub-micron CMOS devices, has been developed. The process features formation of an insulator hard mask shape on an underlying polysilicon gate structure shape in the DDD MOSFET region, while only a polysilicon gate structure shape is formed in the CMOS device region. High energy ion implantation procedures are employed to form the deep source/drain regions of the DDD MOSFET devices with the insulator hard mask shape preventing the high energy implantation procedure from disturbing the underlying channel region. An anneal procedure used activate and drive—in the implanted ions in the deep source/drain region of the DDD MOSFET device is followed by formation of the shallower source/drain regions of the sub-micron CMOS devices.

Abstract: A semiconductor component and a method for manufacturing the semiconductor component that mitigates electromigration and stress migration in a metallization system of the semiconductor component. A hardmask is formed over a dielectric layer and an opening is etched through the hardmask and into the dielectric layer. The opening is lined with a barrier layer and filled with an electrically conductive material. The electrically conductive material is planarized, where the planarization process stops on the barrier layer. Following planarization, the electrically conductive material is recessed using either an over-polishing process with highly selective copper slurry or a wet etching process to partially re-open the filled metal-filled trench or via. The recess process is performed such that the exposed portion of the electrically conductive material is below the dielectric layer.

Abstract: A method for fabricating a high voltage dual gate device is disclosed which limits damage to a device isolation layer by forming a high voltage oxide film after formation of a buffer nitride film.

Abstract: A method of nitriding an insulation film, includes the steps of forming nitrogen radicals by high-frequency plasma, and causing nitridation in a surface of an insulation film containing therein oxygen, by supplying the nitrogen radicals to the surface of the insulation film.

Abstract: A method for manufacturing the memory device by plasma decomposition of sulfur dioxide. A first copper electrode having a surface is provided. The surface of the first copper electrode may be made amorphous. A copper sulfide layer, CuxS, where 1?x?2, is disposed on the copper surface by decomposing sulfur dioxide in an ambient containing excess hydrogen. The copper sulfide layer may be is cuprous sulfide or cupric sulfide. A second copper electrode is coupled to the copper sulfide layer.

Abstract: A circuit element that includes a ferroelectric device connected to a substrate device. The circuit element is constructed by fabricating the substrate device in a semiconductor substrate and depositing a dielectric layer over the semiconductor substrate. A via is then etched in the dielectric layer to provide access to the substrate device and filled with copper or tungsten. A layer of a conducting metallic oxide is then deposited on the conducting plug, and a layer of ferroelectric material is deposited on the layer of conducting metal oxide. The layer of conducting metallic oxide is deposited at a temperature below 450° C., preferably at room temperature.

Abstract: A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.

Abstract: A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with a gate dielectric/etch stop layer stack. The N channel gate stack and the P channel gate stack are etched by a dry etch. Either the gate dielectric or etch stop can be in contact with the substrate. The etch stop layer prevents the dry etch of the first and second metal layers from etching through the gate dielectric and gouging the underlying substrate.

Abstract: A transistor of a semiconductor device has an increased driving capacity. The semiconductor device has a first gate insulation film formed by a selective oxidation, a second gate insulation film formed by thermal oxidation and a gate electrode formed across the first and the second gate insulation films. The second gate insulation film is composed of a thicker gate insulation film and a thinner gate insulation film.

Abstract: A method for making a semiconductor device is described. In that method, a metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the sides of the masking layer are lined with a sacrificial layer.

Abstract: A method for fabricating a p-n heterojunction device is provided, the device being preferably comprised of an n-type GaN layer co-doped with silicon and zinc and a p-type AlGaN layer. The device may also include a p-type GaN capping layer. The device can be grown on any of a variety of different base substrates, the base substrate comprised of either a single substrate or a single substrate and an intermediary layer. The device can be grown directly onto the surface of the substrate without the inclusion of a low temperature buffer layer.

Abstract: A device structure and a method of fabricating an electrostatic discharge (ESD) protection circuit on a semiconductor device. A substrate is provided. A layer of silicon oxide is formed on the substrate. A photoresist mask is formed on the layer of silicon oxide. A species of n-type ions is implanted into the surface to form source/drain regions in the ESD protection area. After removing the photoresist, a metal layer is blanket deposited over the surface. A thermal process is performed to form salicide layers on the source/drain regions. A patterned photoresist is respectively formed to cover a portion of the salicide layer. An etching process is performed to strip away the exposed portion of the salicide layer.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions by forming a conductive layer of material. Trenches are formed in the row direction across the active regions, and are filled with a conductive material to form blocks of conductive material that are the control gates. Sidewall spacers of conductive material are formed along the floating gate blocks to give the floating gates protruding portions that extend over the floating gate.

Abstract: In a method for fabricating a thin film transistor array substrate, a glass substrate undergoes an oxygen plasma treatment. A silver or silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a gate line assembly proceeding in the horizontal direction. The gate line assembly includes gate lines, gate electrodes, and gate pads. Thereafter, a silicon nitride-based gate insulating layer is deposited onto the substrate, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. The semiconductor layer and the ohmic contact layer are HF-treated. A silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads.

Abstract: A method to form transistors having improved ESD performance in the manufacture of an integrated circuit device is achieved. The method includes providing a SOI substrate with a doped silicon layer and a buried oxide layer. The doped silicon layer has a first conductivity type and overlies the buried oxide layer. Ions are implanted into the SOI substrate to form higher concentration regions in the doped silicon layer. The higher concentration regions have the first conductivity type and are formed substantially below the top surface of the doped silicon layer. MOS gates are formed. These MOS gates include an electrode layer overlying the doped silicon layer with a gate oxide layer therebetween. Source and drain regions are formed in the doped silicon layer to complete the transistors in the manufacture of the integrated circuit device. The source and drain regions contact the higher concentration regions and have a second conductivity type.

Abstract: The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations. A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, strip, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer is 31 can be prevented.

Abstract: A method for testing semiconductor chips, in particular semiconductor memory chips, is described. In which, in a chip to be tested, at least one test mode is set, the test mode is executed in the chip and test results are output from the chip. It is provided that, after the setting and before the performance of the test mode, a check mode is executed in which the status of the test mode set in the chip is read out in a defined format.

Abstract: A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die.

Abstract: An image sensor element includes a vertical overflow drain structure to eliminate substrate charge diffusion causing CMOS image sensor noise. An extra chemical mechanical polish step used to shorten the micro-lens to silicon surface distance in order to reduce optical cross talking. One embodiment uses N type substrate material with P? epitaxial layer to form a vertical overflow drain. Deep P well implantation is introduced to the standard CMOS process to prevent latch-up between an N well to an N type substrate. A photo diode is realized by stacked N well/Deep N well and stacked P well/Deep P well to improve performance.

Abstract: A semiconductor device having a composite dielectric layer, including a semiconductor substrate, alternating sub-layers including a first dielectric material and a second dielectric material on the semiconductor substrate, the sub-layers forming a composite dielectric layer having at least two sub-layers of at least one of the first dielectric material and the second dielectric material, in which one of the first dielectric material and the second dielectric material is a high-K dielectric material and an other of the first dielectric material and the second dielectric material is a standard-K dielectric material comprising aluminum oxide; and the composite dielectric layer includes a reaction product of the high-K dielectric material and the standard-K dielectric material. In one embodiment, the composite dielectric layer includes a substantially uniform layer of the reaction product of the first dielectric material and the second dielectric material.

Abstract: The present disclosure relates to a method for fabricating an image sensor capable of improving dark current characteristics.

Abstract: In a fabrication method of a flash memory device, a first oxide layer is formed on the substrate in the memory cell region and in the peripheral circuit region. A first conductive layer is formed and defined to form a plurality of floating gates in the memory cell region. A second oxide layer and a silicon nitride layer are sequentially formed in the memory cell region and in the peripheral circuit region. The first conductive layer, the second oxide layer and the silicon nitride layer in the peripheral circuit region are removed. A doped region is formed in the peripheral circuit region. A third oxide layer is formed in the memory cell region and in the peripheral circuit region by wet rapid thermal oxidation. Thereafter, a second conductive layer is deposited to form concurrently a control gate in the memory cell region and a gate in the peripheral circuit region.

Abstract: Novel light-emitting and/or light-responsive semiconductor devices utilize an electric field to selectively displace packets of charged carriers in an optically-active semiconductor medium. The invention, generally referred to as field aperture selecting transport or “FAST,” provides a new way to overcome the recombination-imposed speed limits associated with traditional light-emitting semiconductor devices.

Abstract: A parallel processor includes: two processor element groups each configured to simultaneously execute arithmetic operations for states of all logical values expressable by N bits (N is a natural number) and retain results of the arithmetic operation to execute an arithmetic operation equivalent to N qubits; and an exchange unit for data exchange between the two processor element groups, and the two processor element groups each configured to execute an arithmetic operation equivalent to N qubits are connected to each other via the exchange unit to constitute a processor element group configured to execute an arithmetic operation equivalent to (N+1) qubits with 1 qubit extension, and consequently, it becomes possible to execute a large-scale arithmetic operation at high speed without any increase in the time and effort required for designing an integrated circuit for executing the large-scale arithmetic operation.

Abstract: A method and apparatus is provided for depositing and planarizing a material layer on a substrate. In one embodiment, an apparatus is provided which includes a partial enclosure, a permeable disc, a diffuser plate and optionally an anode. A substrate carrier is positionable above the partial enclosure and is adapted to move a substrate into and out of contact or close proximity with the permeable disc. The partial enclosure and the substrate carrier are rotatable to provide relative motion between a substrate and the permeable disc. In another aspect, a method is provided in which a substrate is positioned in a partial enclosure having an electrolyte therein at a first distance from a permeable disc. A current is optionally applied to the surface of the substrate and a first thickness is deposited on the substrate. Next, the substrate is positioned closer to the permeable disc. During the deposition, the partial enclosure and the substrate are rotated relative one another.

Abstract: A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Abstract: A method for making a memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure which traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: A process gas constituted by a compound having a ring structure in its molecules is introduced into a chamber (12). In the meantime, an excitation gas such as argon, etc. is excited by an activator (34) and introduced into the chamber (12), so that the process gas is excited. The excited process gas is deposited on a process target substrate (19), forming a porous low dielectric constant film having ring structures in the film.

Abstract: A processor includes a processor core having a general-purpose register, an instruction decoder, and an execution unit. An extension unit includes another execution unit connected to the processor core; and, a direct memory access controller is connected to both the processor core and the extension unit.

Abstract: A method and structure for a method of manufacturing a device having different types of transistors, wherein gates of the different types of transistors in the device comprise different materials. The method comprises depositing a silicon layer on a gate dielectric layer, depositing a first-type gate material on the silicon layer, removing the first-type gate material from areas where a second-type gate is to be formed, depositing a second-type gate material on the silicon layer in areas where the first-type gate material was removed, and simultaneously patterning the first-type gate material and the second-type gate material into first-type and second-type gates, and anneal and transform the two types of gate materials.

Abstract: A method for selectively forming an epitaxial thin film on a semiconductor substrate by controlling a flow rate of a source gas supplied to a deposition ambient includes determining a relation between the growth rate of the epitaxial thin film and the gas flow rate by changing the flow rate of the gas supplied to the deposition ambient at a prescribed temperature. A mass transfer limited region, a kinetically limited region, and an intermediate region are identified. The method further includes supplying the source gas at the flow rate corresponding to the intermediate region to form the epitaxial thin film on the semiconductor substrate. Thus, a method for selectively forming a flat epitaxial thin film by controlling the growth temperature and the gas flow rate is provided.

Abstract: A contactless mask programmable read-only memory (Mask ROM) is described, comprising a plurality of word lines extending in row direction and a plurality of diffusions arranged in rows and columns in a substrate. In the Mask ROM, two rows of diffusions are separated by a word line. Two adjacent diffusions in the same column, the word line between the two diffusions, and the substrate between the two diffusions together constitute a memory cell. The memory cells include a plurality of first memory cells and a plurality of second memory cells. The channel length, the gate oxide width or the channel dopant concentration of the first memory cells is different from that of the second memory cells, such that the threshold voltage of the first memory cells is substantially different from that of the second memory cells.

Abstract: A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

Abstract: A crystal growth apparatus for a semiconductor thin film includes a first radiator for selectively radiating first laser light to the semiconductor thin film for allowing semiconductor thin film to crystallize through a super-lateral growth method and a second radiator for selectively radiating second laser light, which is transmitted through the semiconductor thin film better than the first laser light, to the glass substrate at a position corresponding to an area including a crystallization target area of semiconductor thin film. The second radiator includes a laser oscillator for producing the second laser light, an aperture stop plate being radiated with the second laser light to form a desired aperture image, and an objective lens for forming the aperture image on the main surface of the glass substrate. Thus, a polycrystalline semiconductor thin film having large crystal grains can easily and stably be obtained.

Abstract: In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value.

Abstract: A process for forming a superjunction device that includes a series of implants to form closely spaced implant regions which are linked together by a short thermal step, whereby deep and narrow regions can be formed within a semiconductor body.

Abstract: To provide an organic EL display capable of displaying an accurate color and reducing or preventing a decrease in light transmittance, an organic EL display includes a display portion having a plurality of organic EL elements arrayed therein, a circuit element portion having second thin film transistors serving as switching elements for the respective organic EL elements, and a first underlying protective film made of a silicon nitride film formed between the circuit element portion and the transparent substrate. The first underlying protecting film has a plurality of apertures formed corresponding to the positions of the respective organic EL elements.

Abstract: A field effect transistor with a dual-counterdoped channel is disclosed. The transistor features a channel comprising a first doped region (28) and a second doped region (26) underlying the first doped region. A source and drain (32) are formed adjacent to the channel. In one embodiment of the present invention, the first doped region (28) is doped with arsenic, while the second doped region (26) is doped with phosphorus. The high charge-carrier mobility of the subsurface channel layer (28) allowing a lower channel dopant concentration to be used, which in turn allows lower source/drain pocket doping. This reduces the capacitance and response time of the transistor.

Abstract: In a DRAM-incorporated semiconductor device (SOC) which has a DRAM section and a logic section being formed on one and the same substrate, with the object of providing, with low cost, a SOC having necessary and sufficient characteristics in the DRAM section, while attaining higher-speed performance of the whole elements, silicide is formed at least on all the surfaces of the source-drain regions (10) and the gate surfaces (6) of transistors in the DRAM section and the logic section, concurrently in one and the same step.

Abstract: The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by forming an opening into a structure that includes at least a first semiconductor layer and a second semiconductor layer that have different crystal orientations. The opening extends to the first semiconductor layer.

Abstract: The movement and mixing of microdroplets through microchannels is described employing silicon-based microscale devices, comprising microdroplet transport channels, reaction regions, electrophoresis modules, and radiation detectors. The discrete droplets are differentially heated and propelled through etched channels. Electronic components are fabricated on the same substrate material, allowing sensors and controlling circuitry to be incorporated in the same device.

Abstract: A process of forming a compound film includes formulating a nano-powder material with a controlled overall composition and including particles of one solid solution. The nano-powder material is deposited on a substrate to form a layer on the substrate, and the layer is reacted in at least one suitable atmosphere to form the compound film. The compound film may be used in fabrication of a radiation detector or solar cell.

Abstract: The present invention is related to a method for fabricating a semiconductor device capable of preventing occurrences of void and seam phenomena caused by a negative slope of an insulation layer or a bowing profile phenomenon in a cross-sectioned etch profile of a contact hole. To achieve this effect, the attack barrier layer or the capping layer is additionally deposited on the profile containing self-aligned contact holes in order to prevent an undercut of the inter-layer insulation layer, which is a main cause of the seam generations. Also, the attack barrier layer has a function of preventing the inter-layer insulation layer from being attacked during the wet cleaning/etching process. Ultimately, it is possible to improve device characteristics with the prevention of the seam generations.

Abstract: An extreme ultraviolet light generating device 1 arranged at the uppermost of an X-ray exposure apparatus is provided with a vacuum chamber 4, in which a central discharge electrode 2 and a peripheral discharge electrode 3 are arranged coaxially with each other. The central discharge electrode 2 is formed of tungsten, and a hollow portion 2a thereof is coated with a diamond thin film 10 having a thickness of 0.2 mm. In the hollow portion 2a, the distal end of a cooling water pipe 11 connected to a cooling water supplying device 12 is arranged. The temperature of the cooling water is always kept at about 20 degree C. and supplied to the hollow portion 2c of the central discharge electrode 2 through the cooling pipe 11. As the result, the temperature of the central discharge electrode 2 is quickly decreased resulting in preventing the rising of the temperature of the central discharge electrode 2, therefore to reduce the amount of the debris.

Abstract: The method for manufacturing a CMOS image sensor is employed to pattern uniformly an overlying layer on a gate structure regardless of a gate width. The method includes steps of: preparing a semiconductor substrate by a predetermined process where a pixel area, a peripheral area and an input/output (I/O) area are defined by FOX therebetween; forming a first, a second and a third gate structures in the pixel, the peripheral and the I/O areas, respectively; forming a salicide barrier layer and a BARC layer over the resultant structure in sequence; forming a first photoresist mask on the BARC layer in the I/O area; carrying out a first etchback process by using the first photoresist mask as an etch mask; forming a second photoresist mask on the BARC layer in the pixel area; carrying out a second etchback process by using the second photoresist mask as the etch mask; and carrying out a third etchback process so as to expose top faces of the first and the second gate structures.

Abstract: The invention relates to a molecular electronics arrangement comprising a substrate, at least one first strip conductor having a surface and being arranged in or on the substrate, a spacer which is arranged on the surface of the at least one first strip conductor and which partially covers the surface of the at least one first strip conductor, and at least one second strip conductor which is arranged on the spacer and comprises a surface which faces the surface of the at least one first strip conductor in a plane manner. The spacer partially covers the surface of the at least one second strip conductor, and defines a pre-determined distance between the at least one first strip conductor and the at least one second strip conductor.

Abstract: A method of forming a semiconductor device includes fabricating digital circuits comprising a programmable logic circuit on a substrate; selectively fabricating either a memory circuit or a conductive pattern substantially above the digital circuits to program said programmable logic circuit; and fabricating a common interconnect and routing layer substantially above the digital circuits and memory circuits to connect digital circuits and one of the memory circuit or the conductive pattern.

Abstract: The laser irradiation apparatus of the present invention is configured to include a laser and at least two mirrors each having a concave surface for unidirectionally homogenizing an energy density of laser light emitted from the laser. A focal position of a first mirror exists between the first mirror and an irradiation surface. A focal position of a second mirror does not exist between the second mirror and the irradiation surface, but exists behind the irradiation surface. The laser irradiation apparatus thus configured enables laser irradiation of, for example, semiconductor films.

Abstract: A method for forming on a substrate an electronic device including an electrically conductive or semiconductive material in a plurality or regions, the operation of the device utilising current flow from a first region to a second region, the method comprising: forming a mixture by mixing the material with a liquid; forming on the substrate a confinement structure including a first zone in a first area of the substrate and a second zone in a second area of the substrate, the first zone having a greater repellence for the mixture than the second zone, and a third zone in a third area of the substrate spaced from the second area by the first area, the first zone having a greater repellence for the mixture than the third zone, and depositing the material on the substrate by applying the mixture over the substrate whereby the deposited material may be confined by the relative repellence of the first zone to spaced apart regions defining the said first and second regions of the device and being electrically separa

Abstract: The present invention relates generally to a semiconductor device, and in particular, to a semiconductor device employing a method for forming a pattern for the formation of quantum dots or wires with 1˜50 nm dimension using the atomic array of a single or a poly crystalline material. The electron beam lithography method in accordance with the present invention uses the phase contrast atomic image of a single or a poly crystalline material itself.