Abstract: A bipolar complementary metal oxide semiconductor device has a c-well fabricated using profile engineering (a multi-energy implant using accurate dosages and energies determined by advance simulation) to provide a higher c-well implant dose while creating a narrow region with relatively low concentration in the collector depletion range to avoid low base-collector breakdown. This achieves a much lower collector series resistance to pull-up a frequency response, a collector sheet resistance which can be as low as 150 &OHgr;/sq., and fT may be increased to 20 GHz or higher.

Abstract: The present invention creates a useful BJT by increasing the gain associated with the parasitic BJT on an SOI or bulk type MOSFET. This is done by masking those manufacturing steps that minimize the BJT's beta value, by intentionally increasing the beta value of the BJT, and by driving the base of the BJT with the circuit. Once the gain is increased sufficiently, the BJT may be used productively in the circuit. Because the physical structure of the BJT is already part of the silicon water, its productive use does not require additional space.

Abstract: A low-power high-frequency bipolar transistor is formed to have a small self-aligned intrinsic base region, and small self-aligned extrinsic base and emitter regions that contact the intrinsic base region. The small regions reduce the base resistance, the base-to-collector capacitance, and the base-to-emitter capacitance.

Abstract: A semiconductor device having a bipolar transistor which is capable of high integration, and a semiconductor device in which the bipolar transistor has good characteristic properties. A process for producing said semiconductor device.

Abstract: An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

Abstract: The present invention relates to a method of manufacturing a capacitor in a BICMOS integrated circuit manufacturing technology, including the steps of depositing, on a thick oxide region, a polysilicon layer corresponding to a MOS transistor gate electrode; successively depositing a base polysilicon layer and a silicon oxide layer; forming an opening in these last two layers; performing a thermal anneal in an oxidizing atmosphere; depositing a silicon nitride layer and a spacer polysilicon layer; depositing an emitter polysilicon layer; and making a contact with the base polysilicon layer and a contact with the emitter polysilicon layer.

Abstract: According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a semiconductor substrate and a base polysilicon layer, forming a dielectric layer outwardly from the base polysilicon layer, and forming an emitter region by removing a portion of the dielectric layer and a portion of the base polysilicon layer. The method further includes removing a portion of the first oxide layer to form undercut regions adjacent the emitter region and to enlarge the emitter region, and forming an oxide pad outwardly from the semiconductor substrate in the emitter region.

Abstract: An N-type buried diffusion layer as a portion of the collector region of a bipolar transistor and an N-type buried diffusion layer of a memory cell region are simultaneously formed, and the buried diffusion layer of the memory cell region serves as a potential groove for electrons. The threshold voltage of a MOS transistor in the memory cell region is higher than the threshold voltage of a MOS transistor in a peripheral circuit region, preventing an increase in the standby current in the memory cell region. This increases the soft error resistance of the memory cell and prevents a decrease in the operating speed and an increase in the consumption power.

Abstract: A BiCMOS semiconductor device and a method of forming same are disclosed. A bipolar transistor region is formed adjacent a CMOS device region within a semiconductor substrate. Carbon is implanted in an amount ranging from about 1013 to about 1014 cm−2 before forming the base, emitter and collector within the bipolar transistor region to aid in suppressing transient enhanced diffusion. The bipolar transistor region is subject to rapid thermal annealing to aid in suppressing the transient enhanced diffusion.

Abstract: A method for fabricating a BiCMOS integrated circuit. The method includes the steps of forming in a single implantation step a base region 211 of a bipolar transistor and a p-well 212 of an n-channel MOS transistor; and forming in a single implantation step a collector contact well 213 of a bipolar transistor and an n-well 208 of a p-channel MOS transistor.

Abstract: To program a CMOS memory, an auxiliary bipolar transistor is formed in a P-well adjacent to the P-well of an NMOS device of the CMOS memory, the auxiliary transistor being capable of forcing a large magnitude current through a fusible link, so as to program the electronic state of the CMOS memory cell into a prescribed binary (1/0) condition. A separate implant mask for the emitter region of the auxiliary transistor allows the geometry and impurity concentration profile of the emitter region to be tailored by a deep dual implant, so that the impurity concentration of the emitter region is not decreased, and yields a reduced base width for the auxiliary transistor to provide a relatively large current gain to blow the fuse, while allowing the doping parameters of the source/drain regions of the CMOS structure to be separately established to prevent thyristor latch-up.

Abstract: The present invention provides a method for forming a storage electrode on a semiconductor substrate, and in particular to a storage electrode formation method which can prevent formation of a sharp upper edged cylindrical storage electrode, thereby improving a dielectric property and reliability of a capacitor.

Abstract: A memory cell is provided. The memory cell includes a field-effect transistor having a source region, a drain region and a gate coupled to a wordline. The memory cell also includes a vertical bipolar junction transistor that is biased for use of the reverse base current effect to store data. The bipolar junction transistor has an emitter region formed within a source/drain region of the field-effect transistor. The emitter region is self-aligned with a minimum dimension isolation region adjacent to the memory cell and is coupled to a ground line. A portion of the source/drain region acts as the base of the bipolar junction transistor.

Abstract: The disclosed high voltage device includes a semiconductor substrate, and a first semiconductor layer formed between an underlying first insulating layer and an overlying second insulating layer buried within the semiconductor substrate. The high voltage device includes first and second drift regions formed over the second insulating layer in the semiconductor substrate and spaced apart from each other, an emitter impurity region formed in the first drift region, and a collector impurity region formed in the second drift region. The high voltage device further includes a second semiconductor layer adjacent to and insulated from the collector impurity region, and connected to the first semiconductor layer, and a third semiconductor layer adjacent to and insulated from the emitter impurity region, and connected to the first semiconductor layer.

Abstract: A selective etching method in the fabrication of a semiconductor device is provided. The method involves the steps of: depositing an amorphous layer of semiconductor material on a monocrystalline substrate of the same semiconductor material; depositing at least one dielectric layer on the amorphous layer such as to prevent crystallization of said amorphous layer; patterning the resultant structure and thereafter etching away the dielectric layer and the amorphous semiconductor layer within a predetermined area or region; and heat-treating the resulting structure.

Abstract: A semiconductor device has pads that are arranged in such a manner as to easily accept manual needles to carry out a test. This technique is applicable to carry out a test with use of a boundary scan test circuit in synchronization with a cycle time defined by a normal operation clock signal. The semiconductor device has a first pad connected to a first one of registers that form a serial scan chain, to supply test data to the registers, a second pad connected to a last one of the registers, and a third pad to supply a test clock signal to the registers. The registers are arranged in a central part of the semiconductor device, and the first to third pads are arranged at the periphery of the semiconductor device.

Abstract: A method and apparatus for forming a dielectric layer. A dielectric precursor solution is deposited onto a surface of a substrate. The substrate is spun to spread the dielectric precursor solution over the surface of the substrate. A catalyst is introduced through a filter, wherein the filter causes a substantially homogenous distribution of the catalyst within the substrate, wherein a dielectric layer forms containing pores and wherein a solvent is contained in the pores. The solution is dried to form the dielectric layer using a carrier gas after introducing the catalyst, wherein the carrier gas places a positive pressure within the pores while removing the solvent to form a low-k dielectric layer.

Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.

Abstract: After an oxide film has been completely removed from the surface of a substrate by dip etching, the substrate is inserted into a furnace at a temperature as low as about 400° C. to deposit an amorphous silicon film thereon with almost no oxide film existing therebetween. The amorphous silicon film is then patterned into a base electrode and a dopant contained in the base electrode is diffused into the substrate through annealing to form an extrinsic base diffused layer. Thereafter, an intrinsic base diffused layer is formed by ion implantation and an emitter diffused layer is formed by diffusing a dopant from an emitter electrode. Since an oxide film existing between the base electrode and the substrate can be thinner, excessive expansion of the extrinsic base diffused layer due to the diffusion of the dopant can be suppressed.

Abstract: Disclosed is a method of fabricating a semiconductor device in which at least an LDD type insulated-gate field effect transistor and a bipolar transistor are formed on a common base substrate. An insulating layer for forming side walls of an LDD type insulated-gate field effect transistor is formed by a stack of first and second insulating films. An opening is formed in the lower first insulating film at a position in a bipolar transistor forming area, and a single crystal semiconductor layer is formed on a base substrate through the opening. With this configuration, the fabrication steps can be simplified and the reliability of the semiconductor device can be enhanced.

Abstract: A device layout is disclosed for an ESD device for protecting NMOS high voltage transistors where the SCR protection device and the two NMOS transistors are integrated. The two NMOS transistors share an n-type doped drain (ndd) area which has implanted two n+ drains, one for each of the two transistors and a p+ diffusion separates the two n+ drains. Furthermore, the ndd area has implanted an n-well which extends from halfway under the first n+ drain to halfway under the second n+ drain. In addition, the depth of the n-well exceeds the depth of the ndd area. The added p+diffusion together with the ndd area and the p-substrate of the silicon wafer create the parasitic pnp transistors of the SCR. The shared ndd area together with the n+ sources of the NMOS transistors creates the SCR's two parasitic npn transistors.

Abstract: In a logic circuit having PMOS pull-up devices and NMOS pull-down devices, the PMOS pull-up devices are sized relative to the NMOS pull-down devices according to the number of transistors that simultaneously turn on. In one embodiment, the PMOS transistor width is determined by multiplying the effective NMOS transistor width by a predetermined factor indicative of a current carrying ratio between one of the PMOS pull-up transistors and one of the NMOS pull-down transistors and dividing by the number of PMOS pull-up transistors that simultaneously turn on to charge the output node high. Where the PMOS pull-up devices are parallel-connected, the NMOS transistor width is divided by the number of NMOS transistors.

Abstract: A transistor manufacturing process includes the formation, on a layer (15) that will form the base of the transistor, of a stack of an SiGe alloy layer (16), a silicon oxide layer (17) and a silicon nitride layer (18), so as to form in this layer, a false emitter (20), to form, in the layer (15) that will form the base, an extrinsic base region (22) and to siliconize the surface of this extrinsic base region, to cover the extrinsic base region (22) and the false emitter (20) with a silicon dioxide layer (24) which is chemically and mechanically polished down to the level of the false emitter (20), to etch the false emitter (20) in order to form a window (25) and to form, in the window (25) and on the silicon dioxide layer (24), a polysilicon emitter (27). This process has particular application to manufacturing heterojunction bipolar transistors.

Abstract: Complementary metal-oxide-semiconductor (CMOS) transistors (18,22) are formed with vertical channel regions (30,52) on an insulator substrate (14). Highly doped polysilicon gates (44,68) are formed in trenches (36,58) to extend laterally around the channel regions (30,52) as insulatively displaced therefrom by gate insulators (41,62) that are grown on the sidewalls of the trenches (36,58). The transistors (18,22), which are formed in respective mesas (20,24) have deeply implanted source regions (28,50) that are ohmically connected to the semiconductor surface via respective source connector regions (34,70).

Abstract: A method for forming a field effect vertical bipolar transistor that includes a semiconductive body that has at its top surface a plurality of emitter zones of one conductivity type, each surrounded by a base zone of the opposite conductivity type, and gate electrodes for creating a channel at the surface through the base zone into the bulk inner portion of the one conduction type and at a bottom surface a collector zone that includes a collector electrode overlying a collector layer of the opposite conduction type overlying a field stop layer heavily doped of the opposite conduction type overlying the inner portion lightly doped of the one conduction type. Each of the collector layer and the field stop layer is less than 2 microns in thickness and the collector layer is used to inject minority carriers into the inner zone when appropriately biased.

Abstract: A method for forming integrated circuit bipolar junction transistors for mixed signal circuits. The implants used to form the well regions of the CMOS circuits 20, 40 form the collector regions of bipolar junction transistors. The CMOS transistor pocket implants form the base region of the bipolar junction transistor, and the CMOS drain extension implants form the emitter region of the bipolar junction transistor.

Abstract: A process for fabricating a BiCMOS device, on a semiconductor substrate, featuring PFET and NFET devices, and an NPN bipolar junction transistor, has been developed. The process features the integration, or the sharing of process steps, used for both the CMOS and bipolar devices, such as the creation of an N type buried layer, used in one region for isolation of PFET devices, and used in a second region, of the semiconductor substrate, as a subcollector region, for the bipolar device. Features of the BiCMOS process include the formation of N well, and P well regions, for CMOS device, as well as the use of an epitaxial silicon layer, to allow optimum bipolar characteristics to be achieved.

Abstract: A semiconductor integrated circuit device comprises a multiple-stage amplifier including a plurality of transistors. The multiple-stage amplifier has a first stage comprising a plurality of bipolar transistors each having a single emitter structure. The bipolar transistors are connected parallel to each other. The semiconductor integrated circuit device can easily be designed, is of a self-aligned structure, and has a single transistor size. The semiconductor integrated circuit device may be used as a low-noise, high-power-gain high-frequency amplifier.

Abstract: Form a semiconductor device with dielectric, isolation structures in a top surface of a silicon semiconductor substrate, separating the substrate into emitter, NMOS and PMOS areas. Form a gate oxide layer above the isolation structures on the top surface of the silicon semiconductor substrate. Form a conductive polysilicon layer above the thin silicon oxide layer. Mask the NMOS and PMOS regions of the substrate with an emitter mask having a window over the emitter area of the substrate. Ion implant emitter dopant into a portion of the conductive polysilicon layer over the emitter area of the substrate through the window in the emitter mask. Strip the emitter mask. Anneal the substrate including the thin silicon oxide layer, and the polysilicon layer to drive the dopant into an emitter region in the emitter area in the substrate. Form doped source/drain regions and a base in the emitter area of the substrate.

Abstract: A method of forming a metal oxide semiconductor (MOS)-controlled bipolar transistor includes tilt angle implanting a first impurity into a semiconductor substrate and implanting a second impurity into the semiconductor substrate to form an emitter and a collector. A corresponding transistor arranged as to combine the large current drive capacity of a bipolar junction transistor (BJT) with the smaller device size of a metal oxide semiconductor field effect transistor (MOSFET) is also provided. The transistor includes a semiconductor structure, a gate located proximate the semiconductor structure, a gate insulator disposed intermediate the semiconductor structure and the gate, a source region located in the semiconductor structure, a drain region located in the semiconductor structure, and a buffer region located in the semiconductor structure proximate the drain region.

Abstract: In order to define region in which a bipolar transistor is formed, region in which a MOS transistor is formed, and another predetermined region upon a substrate of p-type silicon, the substrate is selectively oxidized (by the LOCOS method). An element isolation region 200-500 nm thick is thereby formed. Then, a silicon oxide film 550 nm thick on the substrate, a silicon nitride film (an oxidation-resistant film) 100-300 nm thick, and a silicon oxide film 5-50 nm thick are formed. Thereafter, a publicly known photolithographic technique is used to form a photoresist pattern having an opening, and then, using the pattern as a mask, the silicon oxide film on the opening is removed. The bipolar transistor and the MOS transistor are thereby integrated in a monolithic manner without degrading the characteristics of the respective elements.

Abstract: A structure of a BiCMOS transistor hindering over-etching of source/drain regions of a MOS transistor and a manufacturing method thereof are provided. A polysilicon film that is to be a gate electrode lower layer of a MOS transistor is formed, and thereon, another polysilicon film that is to be a gate electrode upper layer of the MOS transistor as well as to be a base electrode of a bipolar transistor is formed. Thereafter, etching is conducted to form the polysilicon film to be the base electrode of the bipolar transistor and the gate electrode at the same time. Here, an oxide film shown in FIG. 4 serves as a protective film, thereby hindering over-etching of n type and p type wells to be active regions of respective MOS transistors.

Abstract: The present invention discloses a method for fabricating isolation trenches applied in BiCMOS processes. The isolation trenches are formed initially by defining an oxide layer formed on a semiconductor substrate. Then an epitaxy layer is formed on the substrate and a polysilicon layer is formed on the oxide layer by selective epitaxial growth (SEG). After forming well regions and a collector region in the epitaxy layer, the polysilicon layer is etched and stopped at the oxide layer such that trenches are formed. Subsequently, an isolating material is filled into the trenches to form isolation trenches. It is noted that the oxide layer definition, the epitaxy layer and the polysilicon layer growth by SEG, and the polysilicon etching processes simplify the process of forming isolation trenches. In addition, the integration of the semiconductor is increased, and the isolating effect is good.

Abstract: A memory cell is provided. The memory cell includes a field-effect transistor having a source region, a drain region and a gate coupled to a wordline. The memory cell also includes a vertical bipolar junction transistor that is biased for use of the reverse base current effect to store data. The bipolar junction transistor has an emitter region formed within a source/drain region of the field-effect transistor. The emitter region is self-aligned with a minimum dimension isolation region adjacent to the memory cell and is coupled to a ground line. A portion of the source/drain region acts as the base of the bipolar junction transistor.

Abstract: A method and a related circuit structure are described for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate overlaid with an epitaxial layer and including at least one ESD protection lateral bipolar transistor realized in the surface of the epitaxial layer. The method consists of forming under the transistor an isolating well that isolates the transistor from the substrate.

Abstract: The present invention relates to a method for semiconductor manufacturing of one semiconductor circuit, having a multiple of transistors NMOS1, NMOS2, NPN1, NPN2 of one type. The method comprises the steps of arranging a first region 4, 16 on a semiconductor substrate 1, and implementing two transistors of said type, having different sets of characteristics, in said first region 4, 16. The step of implementing said active devices comprises a step of creating a first 6′, 10′ and a second 6″, 10″ subregion within said first region 4, 16, and said step further comprising a step of introducing dopants having different sets of dose parameters, into a first and a second area, respectively, of said first region, said dopants being of a similar type, and a step of annealing said substrate 1 to create said first 6′, 10′ and second 6″, 10″ subregion, respectively, whereby two subregions, having different doping profiles, can be manufactured on a single integrated circuit.

Abstract: A BiCMOS integrated circuit is fabricated using a minimum number of wafer processing steps and yet offers the IC circuit designer five (5) different transistor types. These types include P-channel and N-channel MOS transistors and three different bipolar transistors whose emitters are all formed by a different process and all are characterized by different current gains and different breakdown voltages. A differential silicon dioxide/silicon nitride masking technique is used in the IC fabrication process wherein both P-type buried layers (PBL) and N-type buried layers (NBL) are formed in a silicon substrate using a single mask set and further wherein P-type wells and N-type wells are formed above these buried layers in an epitaxial layer, also using a single SiO2/Si3N4 differential mask set. Two of the bipolar transistor emitters are formed by out diffusion from first and second levels of polysilicon, whereas the emitter of the third bipolar transistor is formed by ion implantation doping.

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract: A method of fabricating an SRAM cell having a first conductivity type substrate includes the steps of forming a well of a second conductivity type in the first conductivity type substrate, forming a first active region of a first access transistor and a second active region of a second access transistor in the well, the first and second active regions being in parallel with each other, forming a first trench in the first active region and a second trench in the second active region, wherein the first and second trenches extend into the substrate through the well, forming gate electrodes of the first and second access transistors on the active regions, forming gate electrodes of first and second drive transistors in the first and second trenches, respectively, implanting first conductivity type impurity ions into the active regions of the first and second access transistors, respectively, forming first and second load devices on the substrate, the first and second load devices electrically contacting first ter

Abstract: A BiCMOS integrated circuit is formed with CMOS transistors on an SOI substrate in a silicon layer having a standard thickness of 0.1 &mgr;m to 0.2 &mgr;m and with Bipolar SiGe transistors formed in an epitaxial layer nominally 0.5 &mgr;m thick. The CMOS transistors are formed first with standard processing, then covered with an insulating film. The insulating film is stripped in the bipolar areas and an epitaxial SiGe layer is deposited on the Si substrate. The bipolar transistors are formed using the SiGe epi layer for the base and having an encapsulated structure for device isolation using shallow isolation trenches and the buried oxide.

Abstract: A method of fabricating a complementary metal-oxide semiconductor. A semiconductor substrate having a first conductive type region and a second conductive type region is provided. A conductive layer is formed on the substrate. A patterned insulating layer is formed on the conductive layer. A first photoresist layer is formed over the substrate to cover the first region. A portion of the conductive layer on the second region is removed until the substrate is exposed using the insulating layer as a hard mask. A first doping process is performed to the substrate using the first photoresist layer as a mask. The first photoresist layer is removed. A second photoresist layer is formed to cover the second region. A portion of the conductive layer in the first region is removed until the substrate is exposed using the insulating layer as a hard mask. A second doping process is performed on the substrate using the second photoresist layer as a mask. The second photoresist layer is removed.

Abstract: A method of manufacturing a semiconductor device is provided in which a semiconductor device including a plurality of FETs having different threshold voltages and gate insulating films with different film thicknesses can be manufactured in a simplified process. Specifically, a first gate insulating film is formed on the main surface of a semiconductor substrate. On the first gate insulating film, a first protection film is formed. In regions A and B in each of which an FET having a second gate insulating film with a film thickness different from that of the first gate insulating film is to be formed, the first gate insulating film and the first protection film are removed to expose the surface of the semiconductor substrate. At the same time, the first protection film is left in regions other than the regions A and B. Using the first protection film as a mask, an impurity is implanted into the semiconductor substrate in the regions A and B.

Abstract: A method of manufacturing a transistor capable of obtaining a BICMOS while making the difference in the number of manufacturing processes from a CMOS smaller, includes the steps of: separating an element region in a semiconductor substrate; forming a emitter opening for deciding upon an emitter layer in an insulating film on the semiconductor substrate, forming a polysilicon film on the insulating film and in the emitter opening; implanting selectively impurity ions into the semiconductor substrate through the polysilicon film and the insulating film to form a collector layer and a base layer; and performing heat treatment for activating impurities in the base layer and the collector layer and diffusing impurities into the semiconductor substrate from the polysilicon film to form an emitter diffused layer.

Abstract: A method for fabricating a BiCDMOS device where bipolar, CMOS and DMOS transistors are formed on a single wafer is provided. A semiconductor region of a second conductivity type is formed on a semiconductor substrate of a first conductivity type. Well regions of first and second conductivity types are formed within the semiconductor region. Then, an oxidation passivation layer pattern defining a region where a pad oxide layer and a field oxide layer are to be formed is formed on a surface of the substrate where the well regions have been formed. Impurity ions of the first conductivity type are implanted into the entire surface of a region where the field oxide layer is to be formed, using the oxidation passivation layer pattern as an ion implantation mask. An ion implantation mask pattern defining a field region of the second conductivity type is formed on the substrate where the oxidation passivation layer has been formed.

Abstract: An SRAM memory cell is provided in which a pair of cross-coupled n-type MOS pull-down transistors are coupled to respective parasitically formed bipolar pull-up transistors. The memory cell is formed within a semiconductor layer which extends over a buried layer. The bipolar transistors are formed parasitically from the buried layer and the semiconductor layer used to form the pull-down transistors. The bases of the bipolar transistors may also be dynamically controlled. An SRAM memory array having a plurality of such memory cells and a computer system incorporating the SRAM memory array are also provided.

Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.

Abstract: In one embodiment, the present invention is provided for higher BJT gain and more quality device. Providing a substrate incorporating a device, wherein the device is defined MOS region and BJT region. Conductivity-type well region is formed on the substrate, and then a gate oxide layer is formed on the conductivity-type well region of MOS region. Consequently, a polysilicon layer is deposited on the gate oxide layer of MOS region. Using photolithographic and etching process to define a gate, wherein the polysilicon layer is used as the gate of MOS region. Further implanting ions of a first conductive type into the substrate of MOS region. A first dielectric layer is forming on sidewall of the gate, wherein the first dielectric layer is used as a spacer of MOS region. Sequentially, a first photoresist layer is formed over substrate of BJT region to define an emitter of BJT.

Abstract: A method of manufacturing a BICMOS integrated circuit including an NPN transistor in a heavily-doped P-type wafer coated with a lightly-doped P-type layer, including the steps of forming an N well of collector of a bipolar transistor; coating the structure with a polysilicon seed layer and opening above collector well portions; growing undoped silicon, then P-type doped silicon to form a single-crystal silicon base region; depositing an insulating layer and opening it; depositing N-type emitter polysilicon and etching it outside useful areas; etching the base silicon outside useful areas; forming spacers; and forming a collector contact area at the same time as the drain implantation of the N-channel MOS transistors.

Abstract: The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, opening the protection layer at the base-emitter location of the bipolar transistor, forming a first P-type doped layer of polysilicon, a second layer of silicon nitride and a second oxide layer, opening these last three layers at the center of the emitter-base region of the bipolar transistor, and depositing a third silicon nitride layer, forming spacers, removing the apparent parts of the third layer of silicon nitride, and depositing a third N-type doped polysilicon layer.

Abstract: Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called “smart power” type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: The drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures.