Including Bipolar Transistor (i.e., Bicmos) Patents (Class 438/202)
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Patent number: 6803634Abstract: In the manufacturing process of a Bi-CMOS semiconductor device, which includes a CMOSFET and a bipolar transistor, the steps for forming a well region, source regions, and drain regions of the CMOSFET are also used for forming the bipolar transistor. One of the steps is used for introducing impurities of the same conductivity type in a surface of a base region of the bipolar transistor in order to form a high impurity concentration region in the surface. The high impurity concentration region is formed such that the distance between an emitter region of the bipolar transistor and the high impurity concentration region becomes 1 to 2 &mgr;m. The shift in device characteristics of the bipolar transistor is improved by the high impurity concentration region even if the impurity concentration is relatively low at the surface of the base region of the bipolar transistor.Type: GrantFiled: November 7, 2002Date of Patent: October 12, 2004Assignee: Denso CorporationInventors: Takuya Okuno, Shoji Mizuno, Toshitaka Kanemaru
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Publication number: 20040197980Abstract: A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon nitride film formed at least on a side wall of a conductive pattern including at least one layer of metal or metal silicide, and the second insulating film being a silicon nitride film formed to cover the first insulating film and the upper surface and side wall of the conductive pattern. The first insulating film may be formed to cover the upper surface and side wall of the conductive pattern. A semiconductor device and its manufacture method are provided which can realize high integrated DRAMs of 256 M or larger without degrading reliability and stability.Type: ApplicationFiled: April 20, 2004Publication date: October 7, 2004Applicant: Fujitsu LimitedInventors: Shinichiroh Ikemasu, Narumi Okawa
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Publication number: 20040197978Abstract: A housing, in particular for semiconductor devices, a semiconductor device pin, and a method for the manufacturing of pins wherein at least one pin is punched out from a basic body, in particular a lead framed, by means of one or a plurality of punching process steps, wherein the pin is coated with a separate metal layer after the final punching out of said pin.Type: ApplicationFiled: January 15, 2004Publication date: October 7, 2004Applicant: Infineon Technologies AGInventors: Manfred Dobler, Georg Erhard Eggers, Christian Stocken
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Publication number: 20040197979Abstract: A reinforced solder bump connector structure is formed between a contact pad arranged on a semiconductor chip and a ball pad arranged on a mounting substrate. The semiconductor chip includes at least one reinforcing protrusion extending upwardly from a surface of an intermediate layer. The mounting substrate includes at least one reinforcing protrusion extending upwardly from a ball pad, the protrusions from both the chip and the substrate being embedded within the solder bump connector. In some configurations, the reinforcing protrusion from the contact pad and the ball pad are sized and arranged to have overlapping under portions. These overlapping portions may assume a wide variety of configurations that allow the protrusions to overlap without contacting each other including pin arrays and combinations of surrounding and surrounded elements. In each configuration, the reinforcing protrusions will tend to suppress crack formation and/or crack propagation thereby improving reliability.Type: ApplicationFiled: April 16, 2004Publication date: October 7, 2004Inventors: Se-young Jeong, Nam-seog Kim, Oh-se Yong, Soon-bum Kim, Sun-young Park, Ju-hyun Lyu, In-young Lee
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Publication number: 20040197977Abstract: The invention relates to a field-effect transistor comprising: an active area forming a channel (50); a first active gate (40) which is associated with a first face of the active area; source and drain areas (52, 54) which are formed in the active area and which are self-aligned on the first gate; a second insulated gate (70) which is associated with a second face of the active region opposite the first face of the active region. According to the invention, the second gate (70) is self-aligned on the first gate (40) and, together with the first gate, forms a mesa structure on a support substrate.Type: ApplicationFiled: March 2, 2004Publication date: October 7, 2004Inventor: Simon Deleonibus
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Patent number: 6797580Abstract: According to one exemplary embodiment, a method for fabricating a bipolar transistor in a BiCMOS process comprises a step of forming an emitter window stack by sequentially depositing a base oxide layer and an antireflective coating layer on a top surface of a base, where the emitter window stack does not comprise a polysilicon layer. The method further comprises etching an emitter window opening in the emitter window stack. The method further comprises depositing an emitter layer in the emitter window opening and over the antireflective coating layer and etching the emitter layer to form an emitter. The method further comprises etching a first portion of the base oxide layer not covered by the emitter using a first etchant, thereby causing the first portion of the base oxide layer to have a thickness less than a thickness of a second portion of the base oxide layer covered by the emitter.Type: GrantFiled: February 21, 2003Date of Patent: September 28, 2004Assignee: Newport Fab, LLCInventors: Kevin Q. Yin, Amol Kalburge, Kenneth M. Ring
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Patent number: 6797553Abstract: A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.Type: GrantFiled: July 24, 2002Date of Patent: September 28, 2004Assignee: International Business Machines CorporationInventors: James W Adkisson, Arne W. Ballantine, Ramachandra Divakaruni, Jeffrey B. Johnson, Erin C. Jones, Hon-Sum P. Wong
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Patent number: 6790722Abstract: A method and structure for forming an emitter in a vertical bipolar transistor includes providing a substrate having a collector layer and a base layer over the collector layer, forming a patterning mask over the collector layer, and filling openings in the mask with emitter material in a damascene process. The CMOS/vertical bipolar structure has the collector, base regions, and emitter regions vertically disposed on one another, the collector region having a peak dopant concentration adjacent the inter-substrate isolation oxide.Type: GrantFiled: November 22, 2000Date of Patent: September 14, 2004Assignee: International Business Machines CorporationInventors: Ramachandra Divakaruni, Russell J. Houghton, Jack A. Mandelman, Wilbur D. Pricer, William R. Tonti
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Publication number: 20040166625Abstract: A method for improving the Beta (&bgr;) of a parasitic PNP bipolar junction transistor (BJT) in a conventional CMOS process includes the steps of: providing a P-type substrate having a shallow region corresponding to the P+ electrode of the parasitic PNP BJT and the P+ electrode is located within and in contact with an N-well; forming an electrostatic discharge (ESD) mask layer on the P-type substrate, wherein the mask layer has a pattern exposing an area corresponding to the P+ electrode of the PNP parasitic BJT, and exposing one electrode of an ESD device; and implanting P+ ions to the P-type substrate, thereby deepening a P/N junction of the P+ electrode of the parasitic BJT and the N-well.Type: ApplicationFiled: February 26, 2003Publication date: August 26, 2004Applicant: UNITED MICROELECTRONICS CORPInventor: Tong-Hsin Lee
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Patent number: 6780695Abstract: A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area.Type: GrantFiled: April 18, 2003Date of Patent: August 24, 2004Assignee: International Business Machines CorporationInventors: Huajie Chen, Seshadri Subbanna, Basanth Jagannathan, Gregory G. Freeman, David C. Ahlgren, David Angell, Kathryn T. Schonenberg, Kenneth J. Stein, Fen F. Jamin
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Publication number: 20040157387Abstract: Provided is a method for manufacturing a self-aligned BiCMOS including a SiGe heterojunction bipolar transistor (HBT) for performing high-frequency operations. In this method, an extrinsic base and a selective ion-implanted collector (SIC) are formed by a self-alignment process.Type: ApplicationFiled: December 31, 2003Publication date: August 12, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-don Yi, Heon-jong Shin
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Patent number: 6773973Abstract: A polysilicon-emitter-type transistor has a substrate with a collector region, a base region on the collector region, and an oxide layer on the base region with an emitter window therein exposing part of the base region. The polysilicon emitter is formed by forming a first polysilicon layer of approximately 30 to 100 Angstroms at least within the emitter window and at least on the exposed base region. Then, an interfacial oxide layer being approximately 5 to 50 Angstroms thick is formed in an upper portion of the first polysilicon layer, for example, by exposing the first polysilicon layer to oxygen and annealing. Then, a second polysilicon layer is formed on the interfacial oxide layer. The thickness of the second polysilicon layer may be approximately 500 to 5000 Angstroms thick. Subsequent annealing diffuses dopants in the emitter more uniformly into the base region.Type: GrantFiled: August 13, 2001Date of Patent: August 10, 2004Assignee: Maxim Integrated Products, Inc.Inventors: Alexander Kalnitsky, Sudarsan Uppili, Sang Park
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Patent number: 6767784Abstract: An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.Type: GrantFiled: December 18, 2000Date of Patent: July 27, 2004Assignee: Micron Technology, Inc.Inventors: John D. Porter, William N. Thompson
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Publication number: 20040129983Abstract: An electrostatic discharge (ESD) protection circuit that includes an transistor with a gate electrode isolated from the semiconductor substrate. The transistor can be an insulated gate bipolar transistor (IGBT) connected between an integrated circuit (IC) pad and ground. The IGBT includes a parasitic thyristor that latches when the voltage at the pad exceeds a threshold level and does not turn off until the charge at the pad is dissipated, thereby preventing electrostatic damage to the IC.Type: ApplicationFiled: September 19, 2003Publication date: July 8, 2004Applicant: Micrel, IncorporatedInventor: Shekar Mallikarjunaswamy
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Patent number: 6759696Abstract: The bipolar transistor comprises a collector region (1) of a semiconductor material having a first doping type, a base region (2) of a semiconductor material having a second doping type, and an emitter region (3) having the first doping type. A junction is present between the emitter region (3) and the base region (2), and, viewed from the junction (4), a depletion region (5) extends into the emitter region (3). The emitter region (3) comprises a layer (6) of a first semiconductor material and a layer (7) of a second semiconductor material. The first semiconductor material has a higher intrinsic carrier concentration than the second semiconductor material. The layer (7) of said second semiconductor material is positioned outside the depletion region (5). The second semiconductor material has such a doping concentration that Auger recombination occurs. The invention also relates to a semiconductor device comprising such a bipolar transistor.Type: GrantFiled: August 1, 2002Date of Patent: July 6, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Hendrik Gezienus Albert Huizing, Jan Willem Slotboom, Doede Terpstra, Johan Hendrik Klootwijk, Eyup Aksen
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Publication number: 20040115879Abstract: A memory comprises at least one array of memory elements, a partition of the at least one array into a plurality of sub-arrays of the memory elements, and an array configuration circuit for selectively putting the at least one array in one of two operating configurations. In a first operating configuration, the memory elements of the at least one array are coupled one to another to form a monodimensional sequentially-accessible memory, while in a second operating configuration the memory elements in each sub-array are coupled to one another so as to form an independent monodimensional sequentially-accessible memory block, a data content of any memory element of the sub-array being rotatable by shifts through the memory elements of the sub-array. A sub-array selector, responsive to a first memory address, selects one among the at least two sub-arrays according to the first memory address, and enables access to the selected sub-array.Type: ApplicationFiled: September 12, 2003Publication date: June 17, 2004Applicant: STMicroelectronics Asia Pacific Pte LtdInventors: Bernard Plessier, Ming Kiat Yap
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Publication number: 20040115878Abstract: The present disclosure provides a method for forming and manufacturing a silicon germanium (SiGe) based device. After forming a substrate of the device and forming one or more layers of semiconductor processing materials in one or more predetermined locations to establish an opening for depositing one or more SiGe material layers, a pre-baking process is applied to the device under a low pressure not to exceed 79 torr and 900° C. Once completed, the one or more SiGe material layers are deposited and other conventional steps are taken to complete the manufacturing of the device.Type: ApplicationFiled: December 13, 2002Publication date: June 17, 2004Applicant: Taiwan Semiconductor Manufacturing Co., LTDInventors: Kuen-Chyr Lee, Liang-Gi Yao, Chi-Chun Chen, Shin-Chang Chen, Mong-Song Liang
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Publication number: 20040110335Abstract: Disclosed is a treatment method of annealing and doping a semiconductor comprising steps of irradiating a semiconductor layer (13) formed on a substrate (11) with a laser beam (a), thereby melting at least a part of the semiconductor layer; irradiating a target material (2) including atoms with which the semiconductor layer is to be doped with the laser beam (a′), thereby ablating the atoms of the target material; and doping the melted semiconductor layer with the ablated atoms.Type: ApplicationFiled: March 21, 2003Publication date: June 10, 2004Inventor: Masayuki Jyumonji
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Publication number: 20040092094Abstract: The present invention provides a unique methodology for device and process technology that results in significant improvements in the parameters of the active devices of all integrated technologies including: bipolar, CMOS, BiCmos, BCD (Bipolar, Cmos, DMOS), and DMOS. The approach results in fewer process steps than the standard approach in each of these technologies, while providing lower capacitance, higher speed, lower power dissipation, lower Ron, lower ground resistance, lower output resistance, reduced de-biasing at high current, higher breakdown voltage, higher beta and over a broader current range while providing significant reduction in die size. Use of this approach also results in improved Schottky diodes and solar cells.Type: ApplicationFiled: September 24, 2003Publication date: May 13, 2004Inventor: John Durbin Husher
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Publication number: 20040077139Abstract: An optical fiber terminator package (300) has a chip with a surface with one or more light emitting devices (314) and at least one photoreceptor (312) formed on or in the surface. A cap (302) is bonded to the surface of the chip to encapsulate the devices (312, 314). The cap (302) has one or more regions (316, 318) transparent to light passing to or from the devices (312, 314). The cap (302) has been bonded to the semiconductor chip at the wafer stage prior to separation of the wafer into individual packages.Type: ApplicationFiled: July 10, 2003Publication date: April 22, 2004Inventor: Kia Silverbrook
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Patent number: 6723594Abstract: A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 &mgr;m2 to about 10 &mgr;m2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.Type: GrantFiled: March 4, 2002Date of Patent: April 20, 2004Inventor: Howard E. Rhodes
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Publication number: 20040072399Abstract: The present invention discloses a method for fabricating a BiCMOS transistor, which improves the high frequency characteristics of a bipolar transistor by reducing base resistance and a parasitic capacitance between the base and collector.Type: ApplicationFiled: July 30, 2003Publication date: April 15, 2004Inventor: Jae-Han Cha
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Publication number: 20040063268Abstract: A manufacturing method of a semiconductor device of this invention includes forming metal pads on a Si substrate through a first oxide film, bonding the Si substrate and a holding substrate which bolsters the Si substrate through a bonding film, forming an opening by etching the Si substrate followed by forming a second oxide film on a back surface of the Si substrate and in the opening, forming a wiring connected to the metal pads after etching the second oxide film, forming a conductive terminal on the wiring, dicing from the back surface of the Si substrate to the bonding film and separating the Si substrate and the holding substrate.Type: ApplicationFiled: June 17, 2003Publication date: April 1, 2004Applicant: Sanyo Electric Co., Ltd.Inventors: Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao
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Publication number: 20040063267Abstract: The invention relates to an organic fieId-effect transistor, to a method for structuring an OFET and to an integrated circuit with improved structuring of the functional polymer layers. The improved structuring is obtained by introducing, using a doctor blade, the functional polymer in the mold layer in which recesses are initially produced by imprinting.Type: ApplicationFiled: November 17, 2003Publication date: April 1, 2004Inventors: Adolf Bernds, Wolfgang Clemens, Peter Haring, Heinrich Kurz, Borislav Vratzov
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Publication number: 20040051147Abstract: An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reachthrough) and the P wells are used to form the base. N doped third wells are formed under the N wells, P wells, and shallow trench isolation regions to provide subcollectors. Since the P wells are not implanted through the STI, basewidths are reduced and current gain is increased. Gate electrode masking elements, formed over the base, separate the emitter and base contact regions, improving the emitter-to-base breakdown voltage. The CMOS source/drain N type implants then form emitters in the emitter regions and ohmic contacts in the collector contacts. The source/drain P type implants form the ohmic base contacts to complete the bipolar transistor.Type: ApplicationFiled: September 4, 2003Publication date: March 18, 2004Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Shesh Mani Panday, Alan Shafi, Yona Ju
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Publication number: 20040043553Abstract: A method of forming a programmable conductor memory cell array is disclosed wherein metal and chalcogenide glass are co-sputtered to fill an array of cell vias in a prepared substrate. The prepared substrate is heated above room temperature before the metal and chalcogenide glass film is deposited, and the heating is maintained throughout the deposition. The resulting metal/chalcogenide glass film has good homogeneity, a desired ratio of components, and has a regular surface.Type: ApplicationFiled: August 29, 2003Publication date: March 4, 2004Inventors: Jiutao Li, Allen McTeer
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Patent number: 6700144Abstract: A semiconductor device includes the following: a semiconductor substrate of a first conduction type; an intrinsic semiconductor layer of the first conduction type formed on the semiconductor substrate; a first semiconductor layer of a second conduction type formed on the intrinsic semiconductor layer; a first impurity layer of the first conduction type formed in the first semiconductor layer of the second conduction type; and a bipolar transistor and a MIS transistor formed in the first semiconductor layer of the second conduction type. The laminated structure of the semiconductor substrate, the intrinsic semiconductor layer, and the first semiconductor layer provides a diode for photoelectric conversion. A first insulator layer and a second insulator layer are formed respectively in at least a portion below the bipolar transistor and the MIS transistor.Type: GrantFiled: May 24, 2002Date of Patent: March 2, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toyoyuki Shimazaki, Katuichi Ohsawa, Tetsuo Chato, Yuzo Shimizu
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Publication number: 20040038473Abstract: The present invention relates to integrated circuits having symmetric inducting devices with a ground shield. In one embodiment, a symmetric inducting device for an integrated circuit comprises a substrate, a main metal layer and a shield. The substrate has a working surface. The main metal layer has at least one pair of current path regions. Each of the current path region pairs is formed in generally a regular polygonal shape that is generally symmetric about a plane of symmetry that is perpendicular to the working surface of the substrate. The shield is patterned into segments that are generally symmetric about the plane of symmetry. Medial portions of at least some segments of the shield are formed generally perpendicular to the plane of symmetry as the medial portions cross the plane of symmetry.Type: ApplicationFiled: August 21, 2003Publication date: February 26, 2004Applicant: Intersil Americas Inc.Inventors: Rex Everett Lowther, William R. Young
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Publication number: 20040033653Abstract: A tunnel dielectric layer is formed on a semiconductor device. A floating gate layer is formed on the tunnel dielectric layer. An intergate dielectric layer (ONO layer) is formed on the floating gate layer. An in-situ doped silicon is deposited on the intergate dielectric layer to form a control gate layer and then, an annealing is carried out. The control gate layer, the intergate dielectric layer, and the floating gate layer are patterned through a photolithographic process. The phase transformation of the control gate silicon layer does not occur during a subsequent gate oxidation process to reduce the thickness variation of the ONO layer, thereby improving endurance and bake retention characteristics of the semiconductor device.Type: ApplicationFiled: August 6, 2003Publication date: February 19, 2004Inventors: Bong-Hyun Kim, Hun-Hyeoung Lim, Hyeon-Deok Lee, Yong-Woo Hyung
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Publication number: 20040033652Abstract: A method referred to as a “cellular damascene method” utilizes a multiplicity of regularly arranged closed cavities referred to as “cells”, which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.Type: ApplicationFiled: June 25, 2003Publication date: February 19, 2004Inventors: Zvonimir Gabric, Werner Pamler, Siegfried Schwarzl
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Publication number: 20040033651Abstract: A method for separating a film and a substrate, the method comprising the following stops: a) on the film at least a part of a foil is provided, whereby an adhesive contact between the film and the foil is effected; b) the foil and the film being in adhesive contact therewith are bent away from the substrate; and c) the film is uninterruptedly separated from the substrate, characterized in that at least a part of the foil is attached to a circumferential surface of a roller, which circumferential surface virtually touches the substrate, and wherein during step b) the substrate with the film roller, while the roller is rotated such that during step c) and increasing part of the film is bent around the circumferential surface, while an increasing part of the substrate from which the film has been separated is led, relative to the roller, away from the roller.Type: ApplicationFiled: July 30, 2003Publication date: February 19, 2004Inventor: Johannes Jacobus Schermer
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Publication number: 20040033654Abstract: SiP (System-in-Package) having large-capacity passive elements incorporated therein or mounted thereon is provided. On an interposer made of a silicon substrate, metal substrate or glass substrate having via-holes formed therein, IC chips, or a plurality of chips, which are passive elements formed on a silicon substrate, metal substrate or glass substrate, are mounted in a face-up manner and re-wired en bloc on the chip. Because all of the silicon substrate, metal substrate and glass substrate are durable against high-temperature annealing for crystallizing a high-dielectric-constant material, a large-capacity passive elements can be formed on the substrate which serves as an interposer or on the re-wiring of the chips to be mounted. It is also allowable that large-capacity passive elements formed on the silicon substrate, metal substrate or glass substrate is divided into chips, and that the resultant chips are mounted together with the IC chips.Type: ApplicationFiled: August 11, 2003Publication date: February 19, 2004Inventor: Osamu Yamagata
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Publication number: 20040029338Abstract: There is provided a semiconductor device including a storage capacitor having sufficient capacity and a minimum area. The storage capacitor of a pixel region has such a structure that a first storage capacitor and a second storage capacitor are stacked one on top of the other and are connected in parallel with each other. At that time, the first storage capacitor comprises a first capacitance electrode formed in the same layer as a drain region, a first dielectric, and a second capacitance electrode formed in the same layer as a gate wiring. The second storage capacitor comprises the second capacitance electrode, a second dielectric, and a third capacitance electrode formed in the same layer as a light-shielding film.Type: ApplicationFiled: June 24, 2003Publication date: February 12, 2004Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Takayuki Ikeda, Takeshi Fukunaga
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Publication number: 20040029337Abstract: The present invention provides a semiconductive zirconia sintering material comprising more than 2% by weight of aluminum oxide and sintered zirconia material derived therefrom as well as a method of producing the sintered material. The sintered semiconductive zirconia materials of the present invention have a better physical and mechanical properties than conventional sintered semiconductive zirconia materials.Type: ApplicationFiled: April 25, 2003Publication date: February 12, 2004Applicant: CoorsTek, Inc.Inventors: Matthew W. Schaefer, Frank E. Anderson, Brian Seegmiller
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Publication number: 20040029336Abstract: Bonding methods and articles produced thereby are provided wherein an insulator, such as glass, is bonded to a solder with the assistance of an electric field.Type: ApplicationFiled: April 16, 2003Publication date: February 12, 2004Inventors: Timothy J. Harpster, Khalil Najafi
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Publication number: 20040023453Abstract: Supercritical fluid-assisted deposition of materials on substrates, such as semiconductor substrates for integrated circuit device manufacture. The deposition is effected using a supercritical fluid-based composition containing the precursor(s) of the material to be deposited on the substrate surface. Such approach permits use of precursors that otherwise would be wholly unsuitable for deposition applications, as lacking requisite volatility and transport characteristics for vapor phase deposition processes.Type: ApplicationFiled: July 31, 2003Publication date: February 5, 2004Inventors: Chongying Xu, Thomas H. Baum, Michael B. Korzenski
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Publication number: 20040023452Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz.Type: ApplicationFiled: July 29, 2003Publication date: February 5, 2004Applicant: MICRON TECHNOLOGY, INC.Inventors: Zhongze Wang, Li Li, Yongjun Jeff Hu
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Patent number: 6686233Abstract: The invention relates to a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, in an n-well CMOS process by adding solely two additional process steps to a conventional CMOS process: (i) a masking step, and (ii) an ion implantation step for forming a doped channel region for the high voltage MOS transistor in the substrate self-aligned to the edge of the high voltage MOS transistor gate region. The ion implantation is performed through the mask in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create the doped channel region partly underneath the gate region of the high voltage MOS transistor.Type: GrantFiled: November 2, 2001Date of Patent: February 3, 2004Assignee: Telefonaktiebolaget LM EricssonInventors: Anders Söderbärg, Peter Olofsson, Andrej Litwin
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Publication number: 20040018675Abstract: A flexible plating method by continuously controlling the hydrogen concentration of the plating bath by adding controlled amounts of hydrogen gas. The control of the hydrogen concentration is provided by selected distribution and number of nozzles and size of orifices; and predetermined pressure and duration of hydrogen gas flowing through the nozzles, wherein pressure and duration may be variable with time.Type: ApplicationFiled: July 1, 2003Publication date: January 29, 2004Inventors: Howard R. Test, Homer B. Klonis
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Publication number: 20040014270Abstract: In preferred embodiments, a compact a hybrid integrated circuit device 1 can be provided. A conductive pattern 12 is formed on the top surface of a circuit substrate 10, on the top surface of which an insulating layer 11 has been provided. Conductive pattern 12 is formed over the entirety of the top surface of the circuit substrate. Specifically, conductive pattern 12 is also formed at parts within 2 mm from the peripheral ends of circuit substrate 10. Also, a heat sink 13 A or other circuit element 13 with some height can be positioned near a peripheral end part of circuit substrate 10. By arranging hybrid integrated circuit device 1, the degree of integration of hybrid integrated circuit is improved. Thus, in a case where the same circuit as a prior-art example is formed, the size of the entire hybrid integrated circuit device can be made small.Type: ApplicationFiled: April 24, 2003Publication date: January 22, 2004Applicant: SANYO ELECTRIC CO., LTD.Inventors: Masahiko Mizutani, Sadamichi Takakusaki, Motoichi Nezu, Kazutoshi Motegi
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Publication number: 20040009638Abstract: A semiconductor device includes spaced-apart first and second element formation regions which are formed in a main surface of a semiconductor substrate, a dielectric film which is formed on the main surface of the semiconductor substrate at a location between the first and second element formation regions, first electrode patterns which are formed above the first and second element formation regions respectively and each of which has an end portion extended to overlie the dielectric film, the first electrode patterns being formed by patterning of a first electrode layer, second electrode patterns formed above the first electrode patterns respectively, and a passivation film which is formed above the first electrode patterns to be positioned adjacent to the second electrode patterns while covering part of the dielectric film which is exposed during patterning of the first electrode layer.Type: ApplicationFiled: May 14, 2003Publication date: January 15, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Masahiro Tanaka
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Patent number: 6673703Abstract: A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method annealing is performed at a temperature and for a time such that a first dopant diffuses into a first zone and a second dopant diffuses into a second zone larger than the first zone.Type: GrantFiled: June 13, 2002Date of Patent: January 6, 2004Assignee: STMicroelectronics S.A.Inventors: Olivier Menut, Herve Jaouen
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Patent number: 6670228Abstract: A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.Type: GrantFiled: January 9, 2003Date of Patent: December 30, 2003Assignee: International Business Machines CorporationInventors: Douglas Duane Coolbaugh, Gregory Gower Freeman, Seshadri Subbanna
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Patent number: 6667202Abstract: A semiconductor device which has: a bipolar transistor having a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the surface of the collector region, and an emitter region of a second conductivity type formed from the surface of the base region; a collector extraction region that is separated by an insulating layer and is formed in the collector region except the base region; a concave portion in the collector extraction region that is formed up to a depth where the collector region has a peak concentration in impurity distribution; and a collector extraction electrode that is connected with the collector region to extract ohmic-connecting to the bottom of the concave portion.Type: GrantFiled: May 11, 2001Date of Patent: December 23, 2003Assignee: NEC Electronics CorporationInventor: Hisamitsu Suzuki
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Patent number: 6657262Abstract: An electronic device, integrated monolithically in a semiconductor substrate and comprising a bipolar transistor connected in series to at least one MOS transistor, the bipolar transistor having a base region that includes a first buried region and a first diffused region extending continuously from the substrate surface down to the buried region, and the diffused region is bordered by an isolation trench region extending in the buried region.Type: GrantFiled: March 30, 2001Date of Patent: December 2, 2003Assignee: STMicroelectronics S.r.l.Inventor: Davide Patti
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Publication number: 20030203558Abstract: A phase change memory may have reduced reverse bias current by providing a N-channel field effect transistor coupled between a bipolar transistor and a conductive line such a row line. By coupling the gate of the MOS transistor to the row line, reverse bias current in unselected cells or in the standby mode may be reduced.Type: ApplicationFiled: April 9, 2003Publication date: October 30, 2003Inventor: Tyler Lowrey
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Publication number: 20030203559Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.Type: ApplicationFiled: May 1, 2003Publication date: October 30, 2003Inventor: Steven S. Lee
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Patent number: 6638806Abstract: A collector region is formed on a semiconductor substrate. An emitter electrode, an external base electrode and a gate electrode are formed on the semiconductor substrate. The position of the interface between the gate electrode and the semiconductor substrate is rendered higher than the position of the interface between the external base electrode and the semiconductor substrate. Thus provided is a semiconductor device so improved that dispersion of the withstand voltage of a gate oxide film and dispersion of characteristics such as a threshold voltage and a drain-to-source current are reduced.Type: GrantFiled: May 9, 2002Date of Patent: October 28, 2003Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Takayuki Igarashi, Yoshitaka Ootsu
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Patent number: 6633069Abstract: A bipolar transistor has metal silicide as a base lead-out electrode instead of conventional polysilicon, and the metal silicide film extends to an edge of an etching stopper layer, to reduce an emitter resistance and restrain an occurrence of an emitter plug effect. Such bipolar transistor can be utilized in a CMOS semiconductor device.Type: GrantFiled: May 20, 1998Date of Patent: October 14, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hideaki Nii, Chihiro Yoshino
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Patent number: 6630377Abstract: An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reachthrough) and the P wells are used to form the base. N doped third wells are formed under the N wells, P wells, and shallow trench isolation regions to provide subcollectors. Since the P wells are not implanted through the STI, basewidths are reduced and current gain is increased. Gate electrode masking elements, formed over the base, separate the emitter and base contact regions, improving the emitter-to-base breakdown voltage. The CMOS source/drain N type implants then form emitters in the emitter regions and ohmic contacts in the collector contacts. The source/drain P type implants form the ohmic base contacts to complete the bipolar transistor.Type: GrantFiled: September 18, 2002Date of Patent: October 7, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Shesh Mani Panday, Alan Shafi, Yong Ju