Abstract: A semiconductor device is fabricated by forming a trench in a semiconductor body. A region of dielectric material is formed within at least a lower portion of the trench. An upper portion of the semiconductor body is doped. A cutout is formed in the semiconductor material such that a vertical strip of semiconductor material remains along a sidewall of the dielectric material. A lower portion of the semiconductor body adjacent the sidewall of the dielectric material is doped. A gate dielectric layer is formed over the vertical strip of semiconductor material and a gate electrode is arranged in the cutout.

Abstract: A method of manufacturing a flash memory device includes etching portions of a tunnel oxide layer, a first polysilicon layer, a hard mask layer and a semiconductor substrate all of which are laminated over a semiconductor substrate to form trenches. The trenches are filled with an insulating layer thereby forming isolation layers. A portion of top surfaces of the isolation layers is removed, thereby controlling an effective field height (EFH) of the isolation layers while partially exposing sides of the first polysilicon layer. An oxide layer for spacers is formed on the surface of each isolation layer including the exposed first polysilicon layer by using DCS as a source gas. An etch process is performed so that the oxide layer remains only on the sides of the first polysilicon layer, thereby forming spacers. The isolation layers between the spacers are etched to a thickness. The spacers are removed. A dielectric layer and a second polysilicon layer are formed on the surface of each isolation layer.

Abstract: A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.

Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.

Abstract: In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern.

Abstract: A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.

Abstract: A metal-oxide-semiconductor transistor device comprises a semiconductor substrate comprising an active region and an insulation region, a selective epitaxial layer between the active region and a gate structure, wherein a peripheral portion of the epitaxial layer is over a peripheral portion of the insulation region, such that the width of the channel is increased and a drain current is improved.

Abstract: The semiconductor device includes a lower device isolation structure formed in a semiconductor substrate to define an active region. The lower device isolation structure has a first compressive stress. An upper device isolation structure is disposed over the lower device isolation structure. The upper device isolation structure has a second compressive stress greater than the first compressive stress. A gate structure is disposed over the active region between the neighboring upper device isolation structures.

Abstract: Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon surface, in gate electrode region extending from PMOS to NMOS regions across PN film. Polysilicon layer is patterned with second insulating film, and first gate electrode extends from PMOS region surface to PN and second gate electrode extends from NMOS region to PN connecting to first gate electrode. At main surface, opposed first source and drain regions are formed by placing first gate electrode therebetween in plan view. At main surface, opposed second source and drain regions are formed by placing second gate electrode therebetween in plan view. The second insulating film, covering first and second gate electrodes is patterned and exposed on PN. Exposed first and second gate electrodes are silicidized.

Abstract: A semiconductor device and a method for manufacturing the same are provided. A gate insulating film is formed under a vacuum condition to prevent deterioration of reliability of the device due to degradation of a gate insulating material and to have stable operating characteristics. The semiconductor device includes an element isolating film formed at element isolating regions of a semiconductor substrate, which is divided into active regions and the element isolating regions; a gate insulating film having openings with a designated width formed at the active regions of the semiconductor substrate; gate electrodes formed on the gate insulating film; and lightly doped drain regions and source/drain impurity regions formed in the surface of the semiconductor substrate at both sides of the gate electrodes.

Abstract: A method of manufacturing a semiconductor device includes forming first and second active regions and a field region in a surface of a substrate; forming a first gate insulating film in the first and second active regions; covering the surface of the substrate with a first polycrystalline silicon film; exposing the first gate insulating film on the second active region by forming an aperture in the first polycrystalline silicon film over the second active region; removing the first gate insulating film in the second active region; forming a second gate insulating film which is thicker than the first gate insulating film in the second active region; covering the surface of the substrate with a second polycrystalline silicon film; removing the second polycrystalline silicon film on the first active region until it becomes a predetermined film thickness; and forming gate electrodes on the first and second active regions.

Abstract: The present invention pertains to a high-voltage MOS device. The high-voltage MOS device includes a substrate, a first well, a first field oxide layer enclosing a drain region, a second field oxide enclosing a source region, and a third field oxide layer encompassing the first and second field layers with a device isolation region in between. A channel region is situated between the first and second field oxide layers. A gate oxide layer is provided on the channel region. A gate is stacked on the gate oxide layer. A device isolation diffusion layer is provided in the device isolation region.

Abstract: Isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of an image sensor. The isolation methods also include forming an isolation gate over substantial portions of a field isolation region to isolate pixels in an array of pixels.

Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

Abstract: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.

Abstract: The present invention discloses a triple well structure, which includes a substrate of a first conductive type, a deep buried well of a second conductive type, a well of a first conductive type, a well ring of a second conductive type, and a well ring of a first conductive type. The deep buried well of the second conductive type is in the substrate. The well of the first conductive type is disposed over the deep buried well of the second conductive type in the substrate. The well ring of the second conductive type surrounds the well of the first conductive type. The well ring of the first conductive type is between the well of the first conductive type and the well ring of the second conductive type.

Abstract: According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

Abstract: A method for forming a portion of a semiconductor device structure comprises providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate. A first isolation trench is formed within the semiconductor active layer and a stressor material is deposited on a bottom of the first trench, wherein the stressor material includes a dual-use film. A second isolation trench is formed within the semiconductor active layer, wherein the second isolation trench is absent of the stressor material on a bottom of the second trench. The presence and absence of stressor material in the first and second isolation trenches, respectively, provides differential stress: (i) on one or more of N-type or P-type devices of the semiconductor device structure, (ii) for one or more of width direction or channel direction orientations, and (iii) to customize stress benefits of one or more of a <100> or <110> semiconductor-on-insulator substrate.

Abstract: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.

Abstract: A method of manufacturing transistors of a first and second type on a substrate includes producing doped semiconductor areas with a first conductivity type in eventual contact areas of a first type of transistors, depositing a first intrinsic semiconductor layer over an entire surface, activating dopants in the semiconductor areas such that a contact area with the first conductivity type is produced in the intrincing semiconductor layer, depositing a gate dielectric, producing a gate electrode by depositing a first conductive layer and patterning the first conductive layer, performing ion doping with dopants to produce contact areas with a second conductivity type for a second type of transistor, depositing a passivation layer, opening contact openings, and depositing and patterning a second conductive layer.

Abstract: Methods of forming a device isolation structure in a semiconductor device are disclosed. A disclosed method comprises forming a p-type well and an n-type well in a semiconductor substrate; sequentially depositing a gate insulating layer and a gate electrode material layer; depositing a protective layer on the gate electrode material layer; removing a portion of the protective layer, a portion of the gate electrode material layer, and a portion of the gate insulating layer to expose a surface area of the semiconductor substrate; performing ion implantation and heat treatment processes to form a device isolation structure; forming a gate electrode by removing a portion of the gate electrode material layer; forming an LDD region by implanting low concentration impurity ions in the semiconductor substrate; forming a spacers on a sidewall of the gate electrode; and forming a source/drain region by implanting high concentration impurity ions.

Abstract: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.

Abstract: The silicon-on-insulator (SOI) arrangement provides dual SOI film thicknesses for body-resistance control and provides a bulk silicon substrate on which a buried oxide (BOX) layer is provided. The BOX layer has recesses formed therein and unrecessed portions. The silicon layer is formed on the BOX layer and closes the recesses and covers the unrecessed portions of the BOX layer. Shallow trench isolation regions define and isolate first silicon regions from second silicon regions that each include one of the recesses. Floating-body devices are formed within the first silicon regions, which exhibit a first thickness, and body-tied devices are formed within the second silicon regions that include the thicker silicon of the recesses.

Abstract: A method of forming a thin gate insulator layer comprises forming an active region surrounded by STI regions; forming a first insulator layer on the active device region; forming a patterned photoresist layer over the first insulator layer and a at least a portion of the STI regions; etching the first insulator layer to expose a portion of the active device region, wherein the photoresist layer substantially protects the STI regions during etching; forming a thin gate insulator layer on the exposed portion of the active device region, wherein said first insulator layer located on a remaining portion of said active device region is converted to a thicker second insulator layer; and forming a conductive gate structure overlying a first portion of the thin gate insulator layer while a second portion of the thin gate insulator layer not covered by the conductive gate structure is removed.

Abstract: A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on the NMOS side, for stack etch, channel-stop implant, and silicon recess etch (optional); the other masking step is exactly complementary, and performs the analogous operations on the PMOS side. After these two steps are performed (in either order), an additional nitride layer can optionally be deposited and etched to cover the sidewall of the active stack. Field oxide is then formed, and processing then proceeds in conventional fashion.

Abstract: A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an oxide of aluminum. The silicon nitride and the oxide is exposed to an etching solution comprising HF and an organic HF solvent under conditions effective to etch the silicon nitride substantially selectively relative to the oxide. Other aspects and implementations are contemplated.

Abstract: In one embodiment, a semiconductor device comprises a semiconductor material having a first conductivity type with a body region of a second conductivity type disposed in the semiconductor material. The body region is adjacent a JFET region. A source region of the first conductivity type is disposed in the body region. A gate layer is disposed over the semiconductor material and has a first opening over the JFET region and a second opening over the body region.

Abstract: A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate electrode film provided on the gate insulating film of the N-channel MISFET and composed of a first metal silicide, a second gate electrode film provided on the gate insulating film of the P-channel MISFET and composed of a second metal silicide made of a second metal material different from a first metal material composing the first metal silicide, and a work function of the first gate electrode film being lower than that of the second gate electrode film.

Abstract: A method of forming a semiconductor structure includes forming an isolation region in a semiconductor substrate. A first oxide layer is on the substrate, a first sacrificial layer is on the first oxide layer, and a first nitride layer is on the first sacrificial layer. The first oxide layer may be a screen oxide layer, and the method provides consistency in the thickness of the screen oxide layer.

Abstract: A semiconductor device comprises a semiconductor substrate having a high voltage region and a low voltage region, at least a pair of adjacent high voltage MOS transistors disposed on the high voltage region of the semiconductor substrate, and low voltage MOS transistors disposed on the low voltage region of the semiconductor substrate. A first element isolator comprises a first shallow trench disposed on a surface of the low voltage, region of the semiconductor substrate, and a first dielectric embedded in the first shallow trench. A pair of second element isolators comprises two second shallow trenches spaced apart at an interval between a source region or a drain region of the pair of the adjacent high voltage MOS transistors and a source or a drain region of the other of the pair of the adjacent high voltage MOS transistors, and a second dielectric embedded in each of the second shallow trenches.

Abstract: Methods of forming a shallow trench isolation structure are disclosed. A disclosed method comprises: depositing pad oxide over a silicon substrate; implanting ions; removing a portion of the pad oxide using an STI pattern; depositing a polysilicon layer; implanting ions to make N+ polysilicon; depositing a bottom anti-reflection coat (BARC) over the polysilicon layer; forming a gate pattern over the BARC; etching the polysilicon layer to make a gate and form a device isolation area; depositing a nitride layer over the gate and the device isolation area; etching the nitride layer; filling the device isolation area with photoresist; forming silicide; and depositing an oxide layer and performing a planarization process.

Abstract: Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.

Abstract: A method for forming a split-gate flash memory structure includes etching a first gate layer to form one or more floating gates and forming an isolation layer over the floating gates. An insulation layer is deposited over the isolation layer and planarized.

Abstract: The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask having at least one opening on a surface of Si-containing material, recessing the Si-containing material through the at least one opening using an etching process to provide a structure having at least one recess region and a non-recessed region, and forming a first buried insulating region in the non-recessed region and a second buried insulating region in the recessed region. In accordance with the present invention, the first buried insulating region in the non-recessed region is located above the second buried isolation region in the recessed region. A lift-off step can be employed to remove the first buried insulating region and the material that lies above to provide a substrate containing both SOI and non-SOI regions.

Abstract: The present invention provides a system for limiting degradation of a first semiconductor structure (304) caused by an electric field (314), generated from within the semiconductor substrate (302) by high voltage on a second semiconductor structure (310). A semiconductor device (300) is adapted to reduce the effective magnitude of the field—as realized at structure 304—to some fractional component (320), or to render the angle (322)—at which the field approaches the first structure through a first substrate region (306)—acute. Certain embodiments of the present invention provide for: lateral recession of the first semiconductor structure to abut an isolation structure (312), which is disposed between the second semiconductor structure and the first substrate region; lateral recession of the first semiconductor structure from the isolation structure, so as to form a moat therebetween; and a counter-doped region (316) within the first substrate region.

Abstract: The present invention provides a method of forming devices having different operation voltages. First, a substrate having an HV region, an MV region, and an LV region is provided. Then, at least a deep well encompassing the LV region and the MV region is formed in the substrate. Afterward, a plurality of n-wells and a plurality of p-wells are in the HV region, the MV region, and the LV region. Following that, a plurality of HV devices are formed in the HV region, a plurality of MV devices are formed in the MV region, and a plurality of LV devices are formed in the LV region.

Abstract: In a FinFET integrated circuit, the fins are formed with a reduced body thickness in the body area and then thickened in the S/D area outside the body to improve conductivity. The thickening is performed with epitaxial deposition while the lower portion of the gates are covered by a gate cover layer to prevent thickening of the gates at the fin level, which may short the gate to the S/D.

Abstract: A method of creating two or more semiconductor elements of different characteristics in one and the same semiconductor substrate. Two antimony-diffused regions are formed in a p-type semiconductor region (of a semiconductor substrate for providing embedded layers for two field-effect transistors of unlike characteristics. Then the substrate is overlaid with a mask bearing two different patterns of windows. Then phosphor is introduced into the substrate through the mask windows to create phosphor-diffused regions in overlying relationship to the antimony-diffused regions. The two window patterns of the mask are such that the two phosphor-diffused regions differ in mean phosphor concentration. The embedded layers for the two FETs are obtained as an n-type epitaxial layer is subsequently formed on the p-type semiconductor region in which have been created the antimony-diffused regions and phosphor-diffused regions.

Abstract: A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type; a second semiconductor pillar layer of a second conductivity type; a third semiconductor pillar layer of the first conductivity type; a forth semiconductor pillar layer of the second conductivity type; a fifth semiconductor pillar layer of the first conductivity type provided on the major surface of the semiconductor layer; a first semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a second semiconductor base layer of the second conductivity type provided on the forth semiconductor pillar layer; first semiconductor region of the first conductivity type selectively provided on a surface of the first semiconductor base layer; second semiconductor region of the first conductivity type selectively provided on a surface of the second semiconductor base layer; gate insulating film provided on the first semico

Abstract: Disclosed is a method for reducing poly-depletion in a dual gate CMOS fabrication process. The method reduces the poly-depletion in a dual gate CMOS fabrication process by increasing the doping efficiency in a gate polysilicon film. In order to increase the doping efficiency, the method employs the following four technical principles. First, the doping efficiency is increased when the dose of N+ ion implantation is increased. Second, the doping efficiency is increased when the thickness of N+ polysilicon is reduced. Third, the increase of depletion caused by the reduction of the channel width is inhibited when the EFH is adjusted to be less than 0. Fourth, the overall doping efficiency is increased when each step of polysilicon deposition and ion implantation is divided into multiple steps.

Abstract: An improved high-voltage process is disclosed. In order to improve the performance in terms of breakdown voltage and to maintain the integrity of the STI structures, the thick gate oxide layer of the high-voltage device area is not etched back before a high-dosage ion doping process. One photo mask is therefore omitted.

Abstract: A method of fabricating a read only memory cell array is described. A patterned film is formed over the substrate to define the predetermined positions of bit lines on the substrate and exposing a plurality of predetermined portions of the substrate. A plurality of field oxide layers is formed on the exposed portions of the substrate to define the positions of channels. After removing the patterned film, ions are implanted into the substrate to form the bit lines by using the field oxide layer as implanting mask. The field oxide layer is removed to form several recesses on the substrate. Thereafter, a gate insulating layer and word lines are formed over the substrate, and the recess channels are formed underneath the gate-insulating layer. The length of the recess channel is large enough to reduce the short channel effect.

Abstract: Disclosed are a chain gate line structure of a semiconductor device, and a method for manufacturing the same. The semiconductor device having a gate line structure comprises device isolation films formed on a semiconductor substrate for defining active regions and inactive regions; stack type gate electrodes formed on top of the active regions of the semiconductor substrate; at least one layer of an interlayer insulating film formed on the entire surface of the resultant material having the stack type gate electrodes; gate contacts formed on contact holes of the interlayer insulating film and connected to the stack type gate electrodes; and chain type gate lines for connecting the gate contacts formed in the active regions arrayed in a row among a plurality of active regions on the top of the interlayer insulating film in a concave-convex type chain structure.

Abstract: A method of fabricating a trench capacitor of a mixed mode integrated circuit includes forming shallow trench isolation regions for isolating active/passive devices on a semiconductor substrate. The lower electrode layer of the polysilicon layer, the dielectric layer, and the upper electrode layer are formed in sequence in a plurality of shallow trench isolation regions to form a trench capacitor. The present invention uses a trench capacitor to substitute for the 3-dimensional structure capacitor to overcome the disadvantages of the conventional capacitor, resulting in increasing the surface area of electrode and the capacitance.

Abstract: A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug.

Abstract: A semiconductor integrated circuit device having a capacitor element, including a lower electrode provided over an element isolation region of a principal surface of a semiconductor substrate, and an upper electrode provided over the lower electrode with a dielectric film interposed therebetween, has oxidation resistant films disposed between the element isolation region of the principal surface of the semiconductor substrate and the lower electrode, and between the lower electrode and the upper electrode.

Abstract: A word line structure with a single-sided partially recessed gate structure. The word line structure includes a gate structure, a first gate spacer, and a second gate spacer. The gate structure includes a gate dielectric layer, a first gate layer, a second gate layer, and a gate capping layer and has a recess region adjacent to one of opposing sidewalls of the second gate layer. The first gate spacer is disposed over opposing sidewalls of the gate dielectric layer and the first gate layer. The second gate spacer is disposed over opposing sidewalls of the gate structure and covers the first gate spacer. A method for forming a word line structure with a single-sided partially recessed gate structure is also disclosed.

Abstract: A method of forming a MEMS device produces a device layer wafer having a pre-formed conductive pathway before coupling it with a handle wafer. To that end, the method produces the noted device layer wafer by 1) providing a material layer, 2) coupling a conductor to the material layer, and 3) forming at least two conductive paths through at least a portion of the material layer to the conductor. The method then provides the noted handle wafer, and couples the device layer wafer to the handle wafer. The wafers are coupled so that the conductor is contained between the material layer and the handle wafer.

Abstract: Disclosed is a method of forming the floating gate in the flash memory device. After the first polysilicon film is deposited on the semiconductor substrate, the trench is formed on the first polysilicon film with the pad nitride film not deposited. The HDP oxide film is then deposited to bury the trench. Next, the HDP oxide film is etched to define a portion where the second polysilicon film will be deposited in advance. The second polysilicon film is then deposited on the entire top surface, thus forming the floating gate. Thus, it is possible to completely remove a moat and an affect on EFH (effective field oxide height), solve a wafer stress by simplified process and a nitride film, and effectively improve the coupling ratio of the flash memory device.

Abstract: A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.