Abstract: A method of fabricating an image sensor which reduces fabricating costs through simultaneous formation of capacitor structures and contact structures may be provided. The method may include forming a lower electrode on a substrate, forming an interlayer insulating film on the substrate, the interlayer insulating film may have a capacitor hole to expose a first portion of the lower electrode.

Abstract: A semiconductor device includes: a semiconductor substrate including a trench; a capacitor electrode formed in the trench; a first insulation film formed on a bottom of the trench and between the semiconductor substrate and the capacitor electrode; a second insulation film formed on a side wall of the trench and between the semiconductor substrate and the capacitor electrode; and a first metal oxide film formed at the bottom of the trench and between the capacitor electrode and the first insulation film.

Abstract: The invention concerns a capacitor whereof one first electrode consists of a highly doped active region (D) of a semiconductor component (T) formed on one side of a surface of a semiconductor body, and whereof the second electrode consists of a conductive region (BR) coated with insulation (IL) formed beneath said active region and embedded in the semiconductor body.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A method for fabricating a semiconductor memory device. A pair of neighboring trench capacitors is formed in a substrate. An insulating layer having a pair of connecting structures therein is formed on the substrate, in which the pair of connecting structures is electrically connected to the pair of neighboring trench capacitors. An active layer is formed on the insulating layer between the pair of connecting structures so as to cover the pair of connecting structures. A pair of gate structures is formed on the active layer to electrically connect to the pair of trench capacitors. A semiconductor memory device is also disclosed.

Abstract: A method of manufacturing a DRAM includes firstly providing a substrate. Many transistors are then formed on the substrate. Next, a first and a second LPCs are formed between the transistors. A first dielectric layer is then formed on the substrate, and a first opening exposing the first LPC is formed in the first dielectric layer. Thereafter, a barrier layer is formed on the first dielectric layer. Afterwards, a BLC is formed in the first opening, and a BL is formed on the first dielectric layer. A liner layer is then formed on a sidewall of the BL. Next, a second dielectric layer having a dry etching rate substantially equal to that of the liner layer and having a wet etching rate larger than that of the liner layer is formed on the substrate. Finally, an SNC is formed in the first and the second dielectric layers.

Abstract: Disclosed herein is a DRAM memory cell featuring a reduced size, increased retention time, and compatibility with standard logic manufacturing processes, making it well-suited for use as embedded DRAM. The memory cell disclosed herein includes a pass-gate transistor and a storage region. The transistor includes a gate and a drain. The storage region includes a trench, which is preferably a Shallow Trench Isolation (STI). A non-insulating structure, e.g., formed of polysilicon or metal, is located in the trench as serves as a capacitor node. The trench is partially defined by a doped sidewall that serves as a source for the transistor. The poly structure and the trench sidewall are separated by a dielectric layer. The write operation involves charge transport to the non-insulating structure by direct tunneling through the dielectric layer. The read operation is assisted by Gate Induced Drain Leakage (GIDL) current generated on the surface of the sidewall.

Abstract: A method of manufacturing a semiconductor device, includes: forming a first and a second trench regions adjacent from each other in a first conductivity type semiconductor base; forming a second conductivity type semiconductor region in the semiconductor base between the first and second trench regions; forming a mask on the second conductivity type semiconductor region, the mask covering a central portion between the first and second trench regions; performing ion implantation of a first conductivity type impurity in the second conductivity type semiconductor region with the mask to form a first conductivity type first region and a first conductivity type second region separated from the first conductivity type first region; and performing heat treatment to diffuse the impurity in the first and second regions and to form a connection region between the first and second regions, connection region being shallower than the first and second regions after the heat treatment.

Abstract: The invention discloses a method of forming a finFET device. A hard mask layer is formed on an active area of a semiconductor substrate. A portion of the hard mask layer is etched to form a recess. A conformal gate defining layer is deposited on the recess and a tilt angle ion implantation process is performed. A part of the gate defining layer is removed to define a fin pattern. The fin pattern is subsequently transferred to the hard mask layer. The patterned hard mask layer having the fin pattern is utilized as an etching mask, and the semiconductor substrate is etched to form a fin structure.

Abstract: A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.

Abstract: A thin-film device comprises: a substrate; a flattening film made of an insulating material and disposed on the substrate; and a capacitor provided on the flattening film. The capacitor incorporates: a lower conductor layer disposed on the flattening film; a dielectric film disposed on the lower conductor layer; and an upper conductor layer disposed on the dielectric film. The thickness of the dielectric film falls within a range of 0.02 to 1 ?m inclusive and is smaller than the thickness of the lower conductor layer. The surface roughness in maximum height of the top surface of the flattening film is smaller than that of the top surface of the substrate and equal to or smaller than the thickness of the dielectric film. The surface roughness in maximum height of the top surface of the lower conductor layer is equal to or smaller than the thickness of the dielectric film.

Abstract: A conductive strap spacer is formed within a buried strap cavity above an inner electrode recessed below a top surface of a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A portion of the conductive strap spacer is metallized by reacting with a metal to form a strap metal semiconductor alloy region, which is contiguous over the conductive strap spacer and a source region, and may extend to a top surface of the buried insulator layer along a substantially vertical sidewall of the conductive strap spacer. The conductive strap spacer and the strap metal semiconductor alloy region provide a stable electrical connection between the inner electrode of the deep trench capacitor and the source region of the access transistor.

Abstract: A node dielectric, an inner electrode, and a buried strap cavity are formed in the deep trench in an SOI substrate. A buried layer contact cavity is formed by lithographic methods. The buried strap cavity and the buried layer contact cavity are filled simultaneously by deposition of a conductive material, which is subsequently planarized to form a buried strap in the deep trench and a buried contact via outside the deep trench. The simultaneous formation of the buried strap and the buried contact via enables formation of a deep trench capacitor in the SOI substrate in an economic and efficient manner.

Abstract: Provided is a semiconductor device manufacturing method including the steps of: forming an n-type impurity diffusion region by ion-implanting arsenic into a capacitor formation region of a silicon substrate under a condition that a beam current is not less than 1 ?A but less than 3 mA; forming a capacitor dielectric film on the capacitor formation region of the silicon substrate; and forming a capacitor upper electrode on the capacitor dielectric film.

Abstract: A short circuit with an adjacent hole is prevented. By enlarging a hole diameter in the lower part of the hole, a stable storage node is formed without causing a decrease in capacitance. Provided is a method for production of a semiconductor device, comprising the steps of: forming the second hole in the second insulating film to a depth at which a bowing shape does not occur by carrying out anisotropic etching; forming the fourth film on the side surfaces of the first and the second holes; forming the second hole of an aspect ratio greater than 12 by extending the second hole until the first insulating film is exposed by carrying out anisotropic etching; and extending by isotropic etching a side surface portion of the second hole on which the fourth film is not formed.

Abstract: A method of manufacturing a semiconductor device includes forming a first trench in a capacitor device region of a semiconductor substrate, forming a capacitor insulation film over a sidewall surface of the first trench, forming a semiconductor film to cover the first trench, a resistor device region of the semiconductor substrate and a logic device region of the semiconductor substrate, introducing a first impurity element into the semiconductor film formed over the first trench, patterning the semiconductor film to form a top electrode in the capacitor device region, a resistor in the resistor device region and a gate electrode in the logic device region, annealing the semiconductor substrate, and introducing a second impurity element in the resistor.

Abstract: A deep trench containing a doped semiconductor fill portion having a first conductivity type doping and surrounded by a buried plate layer having a second conductivity type doping at a lower portion is formed in a semiconductor layer having a doping of the first conductivity type. A doped well of the second conductivity type abutting the buried plate layer is formed. The doped semiconductor fill portion functions as a temporary reservoir for electrical charges of the first conductivity type that are generated by a radiation particle, and the buried plate layer functions as a temporary reservoir for electrical charges of the second conductivity type. The buried plate layer and the doped semiconductor fill portion forms a capacitor, and provides protection from soft errors to devices formed in the semiconductor layer or the doped well.

Abstract: A semiconductor device having a metal-insulator-metal (MIM) capacitor is provided and can include a lower line formed in a semiconductor substrate; a first interlayer insulating layer formed over the semiconductor substrate, the first interlayer insulating layer having a first conductor and a second conductor electrically connected to the lower line; a second interlayer insulating layer formed over the first interlayer insulating layer, the second interlayer insulating layer including a first via hole and a second via hole connected to the first conductor and the second conductor, respectively; a lower electrode line formed in the first via hole, the lower electrode including a first barrier metal layer, a second barrier metal layer, a second copper seed layer, and a copper layer; and a capacitor formed in the second via hole, the capacitor including the first barrier metal layer, a dielectric layer, the second barrier metal layer and the second copper seed layer.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: forming an inter-layer insulation layer on a substrate; forming storage node contact plugs penetrating into the inter-layer insulation layer; forming a stack structure formed by stacking a first protective barrier layer and a sacrificial layer on the inter-layer insulation layer; performing an etching process to the first protective barrier layer and the sacrificial layer in a manner to have a trenches opening upper portions of the storage node contact plugs; forming storage nodes having a cylinder type inside of the trenches; forming a second protective barrier layer filling the inside of the storage nodes having the cylinder type; removing the sacrificial layer through performing a wet dip-out process; removing the first protective barrier layer and the second protective barrier layer; and sequentially forming a dielectric layer and a plate node on the storage nodes.

Abstract: A method for fabricating line type recess channel MOS transistors utilizes a lithography process to form line type gate trenches in the line type recess channel MOS transistors before finishing a STI process. The method can further control the critical dimension variation in a range required in precision semiconductor processes. Therefore, the short problem between the transistors can be avoided.

Abstract: According to some embodiments, a capacitor includes a storage conductive pattern, a storage electrode having a complementary member enclosing a storage conductive pattern so as to complement an etch loss of the storage electrode, a dielectric layer disposed on the storage electrode, and a plate electrode disposed on the dielectric layer. Because the complementary member compensates for the etch loss of the storage electrode during several etching processes, the deterioration of the structural stability of the storage electrode may be prevented. Additionally, because the complementary member is formed on an upper portion of the storage electrode, the storage electrode may have a sufficient thickness to enhance the electrical characteristics of the capacitor that includes the storage electrode.

Abstract: An electronic device can include a substrate including a fin lying between a first trench and a second trench, wherein the fin is no more than approximately 90 nm wide. The electronic device can also include a first gate electrode within the first trench and adjacent to the fin, and a second gate electrode within the second trench and adjacent to the fin. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and the fin, and the second set of the discontinuous storage elements lies between the second gate electrode and the fin. Processes of forming and using the electronic device are also described.

Abstract: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

Abstract: A method of fabricating an isolation shallow trench contains providing a substrate with at least a deep trench, forming a cap layer on the upper portion of the deep trench, forming a crust layer on a portion of the cap layer, defining a trench extending through the cap layer and the conductive layer, and forming an isolation layer in the shallow trench.

Abstract: A semiconductor structure and a method for forming the same. The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region.

Abstract: Disclosed are a capacitor of a semiconductor device and a method of fabricating the same. The capacitor includes a capacitor top electrode, a capacitor bottom electrode aligned with a bottom surface and three lateral sides of the capacitor top electrode, and a capacitor insulating layer between the capacitor top electrode and the capacitor bottom electrode.

Abstract: A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.

Abstract: A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used to define the required pattern on the photoresist. The hard mask layer and the STI are used as an etching mask to etch a plurality of deep trenches. Then diffusion regions, capacitor dielectric layer, and polysilicon filled to form the capacitor bottom electrode are sequentially formed to complete the forming for trench capacitors. After removing the hard mask layer and performing a logic process, the memory cells are completed.

Abstract: Integrated circuit devices including metal-insulator-metal (MIM) capacitors are provided. The MIM capacitors may include an upper electrode having first and second layers. The first layer of the upper electrode includes a physical vapor deposition (PVD) upper electrode and the second layer of the upper electrode includes an ionized PVD (IPVD) upper electrode on the PVD upper electrode. Related methods are also provided.

Abstract: An integrated circuit device having a capacitor structure. In one form of the invention, an integrated circuit device includes a capacitor structure formed along a surface of a semiconductor layer. The capacitor structure includes a region formed in the semiconductor surface, a layer of dielectric material formed along a trench wall of the trench region and a first layer of doped polysilicon formed over the layer of dielectric material in the trench region. The capacitor structure further includes a second layer of doped polysilicon formed over the first layer of polysilicon.

Abstract: A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming an interface layer, removing a portion of the interface layer, annealing the interface layer, and forming a dielectric material over the interface layer.

Abstract: DRAM cell arrays having a cell area of less than about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.

Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.

Abstract: In general, in one aspect, a method includes forming a semiconductor fin. A first insulating layer is formed adjacent to the semiconductor fin. A second insulating layer is formed over the first insulating layer and the semiconductor fin. A first trench is formed in the second insulating layer and the first insulating layer therebelow. The first trench is filed with a polymer. A third insulating layer is formed over the polymer. A second trench is formed in the third insulating layer, wherein the second trench is above the first trench and extends laterally therefrom. The polymer is removed from the first trench. A capacitor is formed within the first and the second trenches.

Abstract: A method for fabricating silicon-on-insulator (SOI) trench memory includes forming a trench on a substrate, wherein a buried oxide layer is disposed on the substrate, a SOI layer is disposed on the buried oxide layer, and a hardmask layer is disposed on the SOI layer, implanting ions into the substrate and the SOI layer on a first opposing side of the trench and a second opposing side the trench to partially form a capacitor, depositing a node dielectric in the trench, filling the trench with a first polysilicon, removing a portion of the first polysilicon from the trench, removing an exposed portion of the node dielectric, filling the trench with a second polysilicon, masking to define an active region on the hardmask layer, forming shallow trench isolation (STI) such that the STI contacts a portion of the buried oxide layer, removing the hardmask layer, and forming a transistor.

Abstract: A method for fabricating a capacitor in a semiconductor device includes forming a first insulation layer over a substrate, forming storage node contact plugs in the first insulation layer, contacting predetermined portions of the substrate, forming a second insulation layer over the first insulation layer and the storage node contact plugs, forming trenches exposing the storage node contact plugs, forming storage nodes in the trenches, forming a plasma barrier layer over the second insulation layer and the storage nodes, forming a capping layer over the plasma barrier layer and filled in the trenches, removing the capping layer, the plasma barrier layer, and the second insulation layer, forming a dielectric layer over the storage nodes, and forming a plate electrode over the dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

Abstract: A method for forming a recessed channel device includes providing a substrate with a plurality of trench capacitors formed therein, each of the trench capacitors including a plug protruding above the substrate; forming a spacer on each of the plugs; forming a plurality of trench isolations along a first direction in the substrate adjacent to the trench capacitors so as to define an active area exposing the substrate; removing a portion of the substrate by using the spacers and the trench isolations as a mask to form a recessed channel; and trimming the recessed channel so that a surface profile of the recessed channel presents a three-dimensional shape. A recessed channel device with a rounded channel profile is also provided.

Abstract: A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.

Abstract: As an oxygen diffusion prevention layer, a multilayer film formed by a metal nitride and a noble metal element. As an interlayer insulation film on the oxygen diffusion prevention layer, a plasma CVD oxide film is used. Moreover, as an interlayer insulation film on a capacitor, an ozone TEOS film is used.

Abstract: An integrated circuit includes a substrate and at least one active region. A transistor produced in the active region separated from the substrate. This transistor includes a source or drain first region and a drain or source second region which are connected by a channel. A gate structure is position on top of said channel and operates to control the channel. The gate structure is formed in a trench whose sidewalls have a shape which converges (narrows) in the width dimension towards the substrate. A capacitor is also formed having a first electrode, a second electrode and a dielectric layer between the electrodes. This capacitor is also formed in a trench. An electrode line is connected to the first electrode of the capacitor. The second electrode of the capacitor is formed in a layer shared in common with at least part of the drain or source second region of the transistor. A bit line is located beneath the gate structure. The integrated circuit may, for example, be a DRAM memory cell.

Abstract: An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.

Abstract: A method of forming a vertical transistor trench memory cell having an insulating ring is provided. The method includes forming a semiconductor material region in an etched portion of a semiconductor substrate; partially etching the semiconductor material region to form a deep trench, where the deep trench extends beyond the semiconductor material region, and where the remaining of the partially etched semiconductor material region defines an insulating ring. A vertical transistor is then formed in the deep trench, such that the vertical transistor is isolated by the insulating ring. A semiconductor structure is also provided. The semiconductor structure includes a first and a second trench memory cells formed on a semiconductor substrate; and an insulating ring surrounding each of the first and second trench memory cells. The insulating ring is configured for significantly enclosing out diffusions from the trench memory cells.

Abstract: A trench capacitor is formed in a semiconductor substrate with a capacitor insulating film. The trench has a conductive layer as storage node electrode buried in a trench. The conductive layer includes a first, a second, and third conductive layer. The first conductive layer is buried in a lower portion of the trench. The second conductive layer is buried in a recess on the upper surface of the first conductive layer. The third conductive layer is buried to contact with the first and second conductive layers.

Abstract: A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad layer. A first dielectric layer is formed over the dummy gate structure and a protruding portion of the dummy trench fill and then planarized. The dummy structures are removed. The deep trench and a cavity formed by removal of the dummy gate structure are filled with a high dielectric constant material layer and a metallic layer, which form a high-k node dielectric and a metallic inner electrode of a deep trench capacitor in the deep trench and a high-k gate dielectric and a metal gate in the device region.

Abstract: A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface level of the filling electrode layer. A vertical transistor is disposed at the upper portion of the trench, comprising a doped region disposed in a portion of the trench adjacent to the trench. A buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped. The trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer.

Abstract: Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS architecture and a second wafer for PMOS transistors in the CMOS architecture, with the first wafer being bonded and electrically coupled to the second wafer to form at least one CMOS device. Another embodiment includes a number of DRAM capacitors formed on a first wafer and support circuitry associated with the DRAM capacitors formed on a second wafer, with the first wafer being bonded and electrically coupled to the second wafer to form a number of DRAM cells. Another embodiment includes a first wafer having a number of vertical transistors coupled to a data line and a second wafer having amplifier circuitry associated with the number of vertical transistors, with the first wafer being bonded and electrically coupled to the second wafer.

Abstract: A method of fabricating self-aligned gate trench utilizing trench top oxide (TTO) poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a TTO that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.