Abstract: Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such devices. Selectively controlling the temperature changes in different devices during a rapid thermal anneal is accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures. Alternatively, it is accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed.

Abstract: The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated on the silicon substrate. And the present invention is provided with the FIN type transistor with which the gate electrode coiled around the body region formed in the SOI layer, and the planar type transistor which was separated using partial isolation and full isolation together to element isolation, and was formed in the SOI layer.

Abstract: A system and method is disclosed for providing improved trench isolation of semiconductor devices. An isolation trench of the present invention is manufactured as follows. A substrate of a semiconductor device is provided and a trench is etched in the substrate. Then a silicon liner is grown in the trench. The trench is then filled with polysilicon material. Polysilicon material is also deposited on top of the filled trench to protect the silicon dioxide liner from the effects of subsequent etch procedures and oxidation procedures. The initial height of the polysilicon material is selected to be large enough to allow the polysilicon material to survive the subsequent etch procedures and oxidation procedures.

Abstract: A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the bottom. A first removal preventing film is formed on the side wall of the opening and the residual film is removed at a state where the projecting part of the second film protruding from the side wall to the opening remains. The first film exposed in the opening is removed. A second removal preventing film is formed on the first removal preventing film and the surface of the semiconductor substrate exposed in the opening is removed at a state where the projecting part of the semiconductor substrate protruding from the side wall to the opening remains and a round part is formed at the projecting part of the semiconductor substrate. The semiconductor substrate exposed in the opening is further removed.

Abstract: In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed.

Abstract: An interconnect structure is provided that includes a dielectric material 52? having a dielectric constant of 4.0 or less and including a plurality of conductive features 56 embedded therein. The dielectric material 52? has an upper surface 52r that is located beneath an upper surface of each of the plurality of conductive features 56. A first dielectric cap 58 is located on the upper surface of the dielectric material 52? and extends onto at least a portion of the upper surface of each of the plurality of conductive features 56. As shown, the first dielectric cap 58 forms an interface 59 with each of the plurality of conductive features 56 that is opposite to an electrical field that is generated by neighboring conductive features. The inventive structure also includes a second dielectric cap 60 located on an exposed portion of the upper surface of each of the plurality of conductive features 56 not covered with the first dielectric cap 58.

Abstract: A pad oxide layer is formed on a substrate. A pad nitride layer is formed on the pad oxide layer. The pad nitride layer and the pad oxide layer are patterned. Predetermined portions of the substrate are etched using the pad nitride layer as an etch barrier to thereby form trenches used as device isolation regions. The trenches are filled with an insulation layer to thereby form device isolation regions. The pad nitride layer is removed. Recesses are formed by etching predetermined portions of the pad oxide layer and the substrate. The pad oxide layer is removed. A gate oxide layer is formed on the recesses and on the substrate. Gate structures of which bottom portions are buried in the recesses on the gate oxide layer are formed.

Abstract: One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.

Abstract: A starting substrate in the form of a semiconductor wafer (1) has a first side and a second side, the sides being plane-parallel with respect to each other, and has a thickness rendering it suitable for processing without significant risk of being damaged, for the fabrication of combined analogue and digital designs, the wafer including at least two partitions (A1, A2; DIGITAL, ANALOGUE) electrically insulated from each other by insulating material (2; 38; 81; L) extending entirely through the wafer. A method for making such substrates including etching trenches in a wafer, and filling trenches with insulating material is also described.

Abstract: A semiconductor device includes a substrate, and a semiconductor thin film bonded to the substrate, wherein the semiconductor thin film includes a plurality of discrete operating regions and an element isolating region which isolates the plurality of discrete operating regions, and the element isolating region is etched to a shallower depth than a thickness of the semiconductor thin film, and is a thinner region than the plurality of discrete operating regions.

Abstract: A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semiconductor layer, and a second semiconductor layer on the BOX, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively, and wherein the substrate comprises a first region and a second region. An isolation structure is formed in the second region extending to the first semiconductor layer. A trench is then formed in the isolation structure, exposing the first semiconductor layer. A semiconductor material is epitaxially grown in the trench. The method further includes forming a MOSFET of a first type on the second semiconductor layer and a MOSFET of an opposite type than the first type on the epitaxially grown semiconductor material.

Abstract: Methods for fabricating a device structure in a semiconductor-on-insulator substrate. The method includes forming a first isolation region in the substrate device layer that extends from a top surface of the device layer to a first depth and forming a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth. The method further includes forming a doped region of the device structure in the semiconductor layer that is located vertically between the first isolation region and the insulating layer.

Abstract: Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low voltage unit surrounding the high voltage unit, and a junction termination formed between the high voltage unit and the low voltage unit and surrounding the high voltage unit to electrically isolate the high voltage unit from the low voltage unit. The junction termination includes at least one level shifter which level shifts signals from the low voltage unit and supplies the same to the high voltage unit, a first device isolation region surrounding the high voltage unit to electrically isolate the high voltage unit from the level shifter, and a resistor layer electrically connecting neighboring level shifters.

Abstract: A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer.

Abstract: According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode. Each resistivity changing memory element is at least partially surrounded by a thermal insulating structure. The thermal insulating structures are arranged such that the dissipation of heat generated within the resistivity changing memory elements into the environment of the resistivity changing memory elements is lowered.

Abstract: A method for forming shallow trench isolation in a semiconductor device including forming a pad oxide, a pad nitride, and a pore-generating layer on an entire surface of a semiconductor substrate in successive order; etching the pore-generating layer, the pad nitride, the pad oxide and the substrate to form a trench in the substrate; forming a trench oxide over the entire surface of the substrate by a CVD process to fill the trench; and removing the trench oxide in an active device area while retaining the trench oxide in the trench.

Abstract: Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.

Abstract: A material for forming an insulating film with low dielectric constant of this invention is a solution including a fine particle principally composed of a silicon atom and an oxygen atom and having a large number of pores, a resin and a solvent.

Abstract: The present invention provides a SOI wafer produced by an ion implantation delamination method wherein a width of a SOI island region in a terrace portion generated in an edge portion of the SOI wafer where a surface of a base wafer is exposed is narrower than 1 mm and a density of pit-shaped defects having a size of 0.19 ?m or more existing in a surface of a SOI layer detected by a LPD inspection is 1 counts/cm2 or less, and also provides a method for producing the SOI wafer. Thereby, there is provided a SOI wafer produced by an ion implantation delamination method wherein generation of SOI islands generated in delamination can be suppressed and a defect density of LPDs existing in a surface of the SOI wafer can be reduced, and a method for producing the same, so that device failure can be reduced.

Abstract: A method for fabricating a semiconductor element on a semiconductor substrate having a support substrate and a semiconductor layer above the support substrate. The method includes preparing the semiconductor substrate having a transistor formation region and an element isolation region both defined thereon; forming a pad oxide film on the semiconductor layer of the semiconductor substrate; forming an oxidation-resistant mask layer on the pad oxide film; forming a resist mask to cover the transistor formation region on the oxidation-resistant mask layer; performing a first etching process for etching the oxidation-resistant mask layer using the resist mask as a mask to expose the pad oxide film of the element isolation region; and removing the resist mask and oxidizing the semiconductor layer below the exposed pad oxide film by LOCOS using the exposed oxidation-resistant mask layer as a mask to form an element isolation layer.

Abstract: The present invention relates to an isolator and a method of manufacturing the same. An isolator according to the present invention includes a silicon wafer, protective devices formed in predetermined regions of the silicon wafer, and a transformer formed in a predetermined region on the silicon wafer, the transformer having at least two coil patterns spaced apart from each other. According to the present invention, an isolator can be protected from impulses generated by ESD and surge, so that its reliability can be improved, and its size can be considerably decreased. Further, the number of wire bonding times is decreased, so that performance of a chip can be enhanced, and packaging efficiency can be improved, thereby increasing productivity.

Abstract: A dielectric isolation type semiconductor device includes a dielectric isolation type substrate in which a support substrate, an embedded dielectric layer, and a first conductive type semiconductor substrate of a low impurity concentration are laminated one over another. The semiconductor substrate includes a first semiconductor region of a first conductive type having a high impurity concentration, a second semiconductor region of a second conductive type having a high impurity concentration arranged so as to surround the first semiconductor region, a first main electrode joined to a surface of the first semiconductor region, and a second main electrode joined to a surface of the second semiconductor region. A first dielectric portion is arranged adjacent the embedded dielectric layer so as to surround a region of the support substrate superposed on the first semiconductor region in a direction of lamination thereof, and a wire connected with the first main electrode.

Abstract: Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below.

Abstract: A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.

Abstract: A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.

Abstract: A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include depositing a nitride layer within the opening, wherein depositing is performed using a PECVD technique. The process can further include densifying the nitride layer. The process can still further include removing a part of the nitride layer, wherein a remaining portion of the nitride layer can lie within the opening and be spaced apart from the surface.

Abstract: A method of manufacturing a high voltage semiconductor device including forming a P-type region implanted with P-type impurities and an N-type region implanted with N-type impurities in a silicon substrate. The method further includes forming a silicon nitride layer pattern and a pad oxide layer pattern to expose a surface of the silicon substrate, forming a trench by etching the exposed silicon substrate using the silicon nitride layer pattern as an etch mask, forming a trench oxide layer pattern in the trench by removing the silicon nitride layer pattern and the pad oxide layer pattern, and simultaneously forming a deep P-well and a deep N-well by driving P-type impurities in the P-type region and N-type impurities in the N-type region into the silicon substrate, while forming a gate oxide layer on a silicon substrate including the trench oxide layer pattern.

Abstract: A method for manufacturing a semiconductor device having flexibility by separating an element that is manufactured by a comparatively low-temperature (temperature of less than 500° C.) process from a substrate is provided. The element is separated from a glass substrate by the following steps: forming a silicone layer over a glass substrate; performing plasma treatment to the surface of the silicone layer to weaken the surface of the silicone layer; stacking an organic compound layer over the silicone layer; and forming an element that is manufactured through a process at a comparatively low-temperature, typically, a temperature that the organic compound can withstand, over the compound layer.

Abstract: A method of forming an isolation layer structure for a semiconductor device includes forming a first structure on a substrate, the first structure including an insulation layer pattern having a sacrificial pattern therein, the sacrificial pattern having an etching rate that is different from the insulation layer pattern, partially removing the insulation layer pattern until the sacrificial pattern is exposed to form a second structure, partially removing the sacrificial pattern from the insulation layer pattern to form a third structure having a recessed portion at a central portion thereof, and removing an upper portion of the third structure such that a top surface of the third structure is concave with respect to a top surface of the substrate.

Abstract: A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure.

Abstract: A substrate with which a semiconductor device with excellent electric characteristics and high reliability can be manufactured is provided. An aspect of the invention is a method for manufacturing a substrate for manufacturing a semiconductor device: a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are stacked in this order over a surface of a semiconductor substrate by a thermal CVD method, and then a weakened layer is formed at a given depth of the semiconductor substrate; the semiconductor substrate and a substrate having an insulating surface are arranged to face each other, and the second silicon oxide film provided for the semiconductor substrate and a supporting substrate are bonded to each other; and the semiconductor substrate is separated at the weakened layer by heat treatment, whereby a semiconductor film separated from the semiconductor substrate is left over the substrate having the insulating surface.

Abstract: Active devices in a thin film diode (TFD) liquid crystal display (LCD) panel used to control liquid crystal are formed by a metal layer, a transparent conductive layer, and an insulating layer sequentially on a substrate, wherein the metal layer is used as transmitting signal and the transparent conductive layer is used as bottom metal layer of metal-insulator-metal (MIM) thin film diode. The metal layer, the transparent conductive layer, and the insulating layer are defined with desired patterns. Further, a dielectric layer is formed over the substrate, metal layer, the transparent conductive layer, and the insulating layer, and defined to form the locations of electrode terminal and MIM thin film diode by using lithographic process. Next, another transparent conductive layer is formed on the dielectric layer and defined to form a pixel electrode and top metal layer of the MIM thin film diode by using lithographic process.

Abstract: A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included angle formed by the sidewall of the protruding portion and the surface of the substrate is an obtuse angle. The conductor pattern is disposed in the trench and fills the trench up. The dielectric layer is disposed between the conductor pattern and the substrate.

Abstract: The invention relates to a method for producing structures which make it possible to form a trench insulation and to bring into contact SOI wafers provided with active thick layers and which are easily processable. For this purpose, a carrier wafer electric contact and the insulation trench are provided with components exhibiting high-blocking capability of insertion into an integrated circuit SOI wafer. A narrow trench for an insulating trench (8) and a large trench for a carrier wafer contact (9) are etched up to an insulating oxide layer (2) and are buried by a masking layer which is thicker than the buried oxide layer (2). In the large trench (9), a polysilicon spacer (12) remains on the sidewalls, respectively, in the form of a predeposited polysilicon layer (11) rest. The adjustment of the polysilicon etching makes it possible to obtain the spacer (12) provided with a desired height.

Abstract: A method for manufacturing a semiconductor substrate having a silicon-on-insulator (SOI) structure region isolated by a local oxidation of silicon (LOCOS) film and an SOI structure in the region includes forming the LOCOS film so as to make a height from an uppermost surface of a semiconductor member to a top surface of the LOCOS film be higher than a height from the uppermost surface of the semiconductor member to a top surface of the SOI structure, forming a silicon germanium layer and a silicon layer on the SOI structure region on the semiconductor member by epitaxial growth and forming a polysilicon film on a surface of the LOCOS film, forming a recess for a support to support the silicon layer to be a part of the SOI structure, forming the support on the semiconductor member, exposing a side of the silicon germanium layer and the silicon layer underneath the support, forming a cavity by removing the silicon germanium layer having the side exposed, forming the SOI structure by embedding an insulating laye

Abstract: A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.

Abstract: Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS fabrication without encountering problems caused by forming STI regions after epitaxy. A preferred device includes an NFET on a {100} crystal orientation and a PFET on a {110} crystal orientation. An NMOS channel may be oriented along the <100> direction, which is the direction of maximum electron mobility for a {100} substrate. A PMOS channel may be oriented along the <110> direction, which is the direction where hole mobility is maximum for a {110} substrate.

Abstract: A method for manufacturing a semiconductor device having a silicon-on-insulator region and a bulk region in a same semiconductor substrate, the method includes: (a) etching the semiconductor substrate in the silicon-on-insulator region so as to form a concave; (b) forming a first semiconductor layer and subsequently a second semiconductor layer on the semiconductor substrate in the silicon-on-insulator region, so as to bury the concave; (c) etching the second semiconductor layer and the first semiconductor layer partially, so as to form a trench which exposes a side surface of the first semiconductor substrate in the silicon-on-insulator region; (d) etching the first semiconductor layer through the trench with an etching condition in which the first semiconductor layer is easier to be etched than the second semiconductor layer, so as to form a cavity between the semiconductor substrate and the second semiconductor layer in the silicon-on-insulator region; and (e) forming a buried insulating film inside the ca

Abstract: A method of manufacturing a semiconductor substrate and semiconductor device is disclosed and comprises forming a first monocrystalline semiconductor layer on a semiconductor base material, forming a second monocrystalline semiconductor layer covering the first monocrystalline semiconductor layer, and forming a support hole exposing the semiconductor base. A support layer is formed on the active surface of the semiconductor base material to fill the support hole and covers the second polycrystalline semiconductor layer. A cavity is formed between the second monocrystalline semiconductor layer and the semiconductor base material by selectively etching the first monocrystalline semiconductor layer through the opening surface. A buried insulating layer is formed in the cavity. A planarizing layer is formed on the semiconductor base material and planarized using the second polycrystalline semiconductor layer as an etch stop layer.

Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.

Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.

Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

Abstract: The method of the invention for producing a group III-V semiconductor device includes forming, on a base, a plurality of semiconductor devices isolated from one another, each semiconductor device having at least an n-layer proximal to the base, and a p-layer distal to the base, and having a p-electrode formed on the top surface of the p-layer, and a first low-melting-point metal diffusion preventing layer, the low-melting-point metal diffusion preventing layer being formed on the top surface of the p-electrode; forming, from a dielectric material, a side-surface protective film so as to cover a side surface of each semiconductor device; bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer; and removing the base through the laser lift-off process.

Abstract: In order to fabricate a semiconductor device that can perform at its full capacity, in which (i) a single-crystal silicon integrated circuit is formed on an insulating substrate without an adhesive agent, and (ii) an active region of the single-crystal integrated circuit is not damaged by implantation of hydrogen ions, (a) the single-crystal silicon integrated circuit is formed on the insulating substrate, and (b) the single-crystal silicon integrated circuit is surrounded by an oxide (buried oxide layer made of silicon dioxide).

Abstract: The construction of Shallow Trench Isolation, STI, regions is integrated in to a SIMOX fabrication process for a Silicon On Insulator, SOI, wafer. Prior to the beginning of the SOI process, a preferred nitrogen (N2) implant is applied to the silicon wafer in areas designated as active regions. The nitrogen modifies the oxidation rate of later implanted oxygen. Regions where the N2 is implanted result in thinner oxide layers. The SIMOX process can begin following the implantation of nitrogen. This results in buried regions of thick and thin oxide layers at fixed depths in the Si substrate. Excess Si on top of the buried thick and thin oxide regions can be polished down to the thick oxide regions to form the active device regions over the thin oxide regions. Thus, the SOI wafer exhibits an STI structure upon completion of the SOI process without a need for additional STI manufacturing steps.

Abstract: A method and device are for anchoring fixed structural elements and, e.g., for anchoring electrodes for components, e.g., SOI wafer components, whose component structure is formed in a silicon layer on top of a substrate used as support. The fixed element may be mechanically connected to the substrate via at least one anchoring element made of an anchoring material and extending through the silicon layer. In the case of an SOI wafer, the anchoring element may extend through the silicon layer and the sacrificial layer of the SOI wafer. To this end, in the area of the surface of the fixed element, at least one recess is made in the silicon layer, which may extend through the entire silicon layer and the sacrificial layer down to the substrate. The recess may then be filled with an anchoring material, so that the fixed element is mechanically connected to the substrate via the anchoring element that is thereby created.

Abstract: A process of forming an electronic device can include providing a semiconductor-on-insulator substrate including a substrate, a first semiconductor layer, and a buried insulating layer lying between the first semiconductor layer and the substrate. The process can also include forming a field isolation region within the semiconductor layer, and forming an opening extending through the semiconductor layer and the buried insulating layer to expose the substrate. The process can further include forming a conductive structure within the opening, wherein the conductive structure abuts the substrate.

Abstract: A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A thermal oxidation completes the vertical isolation by use of a minifield oxidation process. The recess is filled to form a shallow trench isolation structure. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

Abstract: A bonded SOI wafer and a method for forming a bonded SOI wafer are provided. According to the disclosed method, a first semiconductor wafer is provided, having a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric filled trenches extending from the outer surface inwardly into the semiconductor. The outer surface of the first wafer is bonded to the outer surface of a second semiconductor wafer to form a bonded wafer having a bulk semiconductor region, a buried dielectric layer overlying the bulk semiconductor region, and a semiconductor-on-insulator layer overlying the buried dielectric layer, with the dielectric filled trenches extending upwardly from the buried dielectric layer into the semiconductor-on-insulator layer. The thickness of the semiconductor-on-insulator layer is then reduced until uppermost surfaces of at least some of the dielectric filled trenches are at least partially exposed.

Abstract: Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.