Abstract: A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer.

Abstract: Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication. In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be set in place prior to performing a high aspect ratio word line etch for forming the NAND strings. The one or more mechanical support structures may comprise one or more fin supports that are arranged in a bit line direction. In another example, the one or more mechanical support structures may be developed during the word line etch for forming the NAND strings.

Abstract: A method of filling shallow trenches is disclosed. The method includes: successively forming a first oxide layer and a second oxide layer over the surface of a silicon substrate where shallow trenches are formed in; etching the second oxide layer to form inner sidewalls with an etchant which has a high etching selectivity ratio of the second oxide layer to the first oxide layer; growing a high-quality pad oxide layer by thermal oxidation after the inner sidewalls are removed; and filling the trenches with an isolation dielectric material. By using this method, the risk of occurrence of junction spiking and electrical leakage during a subsequent process of forming a metal silicide can be reduced.

Abstract: Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are/is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided.

Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

Abstract: Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are/is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided.

Abstract: A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.

Abstract: A method for fin field effect transistor (finFET) device formation includes forming a plurality of fins on a substrate; forming a gate region over the plurality of fins; and forming isolation areas for the finFET device after formation of the gate region, wherein forming the isolation areas for the finFET device comprises performing one of oxidation or removal of a subset of the plurality of fins.

Abstract: A fin is formed over a first barrier layer over a substrate. The first barrier layer has a band gap greater than the band gap of the fin. In one embodiment, a gate dielectric layer is deposited on the top surface and opposing sidewalls of the fin and is adjacent to a second barrier layer deposited on the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin and an isolating layer is formed adjacent to the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin, and an isolating layer is formed adjacent to the second barrier layer deposited between the fin and the first barrier layer.

Abstract: A method for fin field effect transistor (finFET) device formation includes forming a plurality of fins on a substrate; forming a gate region over the plurality of fins; and forming isolation areas for the finFET device after formation of the gate region, wherein forming the isolation areas for the finFET device comprises performing one of oxidation or removal of a subset of the plurality of fins.

Abstract: An apparatus of and method for making a semiconductor structure having a shallow trench isolation (STI) trench with a substantially v-shaped profile, that is the distance between top portions is greater than the distance between bottom portions of shallow trench isolation (STI) structure sidewalls adjacent to the trench, provides for substantially seamless and substantially void-free gate structures. The semiconductor structures are formed by implanting an implantation species into the sidewalls, which allows for the top portions of the sidewalls to be etched away at a greater rate than that of the bottom portions, resulting in the substantially v-shaped profile. And the substantially v-shaped profile allows for subsequent device layers to more easily and smoothly fill in the v-shaped trenches, due to a wider opening toward the tops of the trenches.

Abstract: Provided herein are etching, cleaning and drying methods using a supercritical fluid, and a chamber system for conducting the same. The etching method includes etching the material layer using a supercritical carbon dioxide in which an etching chemical is dissolved, and removing an etching by-product created from a reaction between the material layer and the etching chemical using a supercritical carbon dioxide in which a cleaning chemical is dissolved. Methods of manufacturing a semiconductor device are also provided.

Abstract: A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided.

Abstract: Provided are a high voltage semiconductor device in which a field shaping layer is formed on the entire surface of a semiconductor substrate and a method of fabricating the same. Specifically, the high voltage semiconductor device includes a first conductivity-type semiconductor substrate. A second conductivity-type semiconductor layer is disposed on a surface of the semiconductor substrate, and a first conductivity-type body region is formed in semiconductor layer. A second conductivity-type source region is formed in the body region. A drain region is formed in the semiconductor layer and is separated from the body region. The field shaping layer is formed on the entire surface of the semiconductor layer facing the semiconductor layer.

Abstract: Disclosed herein is a semiconductor device including an element isolation region configured to be formed on a semiconductor substrate, wherein the element isolation region is formed of a multistep trench in which trenches having different diameters are stacked and diameter of an opening part of the lower trench is smaller than diameter of a bottom of the upper trench.

Abstract: Provided are semiconductor devices having through electrodes and methods of fabricating the same. The method includes providing a substrate including top and bottom surfaces facing each other, forming a hole and a gap extending from the top surface of the substrate toward the bottom surface of the substrate, the gap surrounding the hole and being shallower than the hole, filling the hole with an insulating material, forming a metal interconnection line on the top surface of the substrate on the insulating material, recessing the bottom surface of the substrate to expose the insulating material, removing the insulating material to expose the metal interconnection line via the hole, filling the hole with a conductive material to form a through electrode connected to the metal interconnection line, recessing the bottom surface of the substrate again to expose the gap, and forming a lower insulating layer on the bottom surface of the substrate.

Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes forming a lower mask film on a semiconductor substrate. The method includes forming a barrier film in a first area. The method includes forming an upper mask film. The method includes removing an upper mask member and leaving a lower mask member in the first area and removing the upper mask member and the lower mask member in the second area. The removing is performed by etching in a condition in which an etching rate of the upper mask member and an etching rate of the lower mask member are higher than that of the barrier member. The method includes forming a conductive film. The method includes selectively removing the conductive film by performing etching in a condition in which an etching rate of the conductive film is higher than that of the lower mask member.

Abstract: A method for manufacturing components on a mixed substrate. The method comprises the following steps: providing a substrate of the semiconductor-on-insulator (SeOI) type comprising a buried oxide layer between a supporting substrate and a thin layer, forming in this substrate a plurality of trenches opening out at a free surface of the thin layer and extending over a depth such that each trench passes through the thin layer and the buried oxide layer, these primary trenches delimiting at least one island of the SeOI substrate, forming a mask inside the primary trenches and as a layer covering the areas of the free surface of the thin layer located outside the islands, proceeding with heat treatment for dissolving the buried oxide layer present at the island, so as to reduce the thickness thereof.

Abstract: In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to an exposed surface of the first layer; heating the structure to a first temperature to enable the filling material to homogeneously fill the plurality of pores; after filling the plurality of pores, performing at least one first process on the structure; after performing the at least one first process, removing the filling material from the plurality of pores by heating the structure to a second temperature to decompose the filling material; and after removing the filling material from the plurality of pores, performing at least one second process on the structure, where the at least one second process is performed at a third temperature that is greater than the second temperature.

Abstract: A structure and method for fabricating a spacer structure for semiconductor devices, such as a multi-gate structure, is provided. The dummy gate structure is formed by depositing a dielectric layer, forming a mask over the dielectric layer, and patterning the dielectric layer. The mask is formed to have a tapered edge. In an embodiment, the tapered edge is formed in a post-patterning process, such as a baking process. In another embodiment, a relatively thick mask layer is utilized such that during patterning a tapered results. The profile of the tapered mask is transferred to the dielectric layer, thereby providing a tapered edge on the dielectric layer.

Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.

Abstract: Semiconductor devices using a group III-V material, and methods of manufacturing the same, include a substrate having a groove, a group III-V material layer filling in the groove and having a height the same as a height of the substrate, a first semiconductor device on the group III-V material layer, and a second semiconductor device on the substrate near the groove. The group III-V material layer is spaced apart from inner side surfaces of the groove.

Abstract: A method includes forming first insulating films on first and second faces of a substrate, removing the first insulating film on the second face, forming polysilicon films on the first insulating film on the first face and the second face, forming second insulating films on the polysilicon films on the first face and the second face, etching the second insulating film on the first face using a mask including an opening, removing the second insulating films on the first face and the second face, removing the polysilicon film on the side of the first face and forming a passivation film which protects the polysilicon film on the side of the second face so that the polysilicon film on the side of the second face is not removed in the polysilicon film removing step, after the polysilicon film forming step and before the polysilicon film removing step.

Abstract: In one embodiment, a method of forming an insulating spacer includes providing a base layer, providing an intermediate layer above an upper surface of the base layer, etching a first trench in the intermediate layer, depositing a first insulating material portion within the first trench, depositing a second insulating material portion above an upper surface of the intermediate layer, forming an upper layer above an upper surface of the second insulating material portion, etching a second trench in the upper layer, and depositing a third insulating material portion within the second trench and on the upper surface of the second insulating material portion.

Abstract: An industrial-scale high throughput wafer bonding apparatus includes a wafer bonder chamber extending along a main axis and comprising a plurality of chamber zones, a plurality of heater/isolator plates, a guide rod system extending along the main axis, a pair of parallel track rods extending along the main axis, and first pressure means. The chamber zones are separated from each other and thermally isolated from each other by the heater/isolator plates. The heater/isolator plates are oriented perpendicular to the main axis, are movably supported and guided by the guide rod system and are configured to move along the direction of the main axis. Each of the chamber zones is dimensioned to accommodate an aligned wafer pair and the wafer pairs are configured to be supported by the parallel track rods. The first pressure means is configured to apply a first force perpendicular to a first end heater/isolator plate.

Abstract: A method of fabricating semiconductor devices is disclosed. The method comprises providing a wafer comprising a substrate with a plurality of epitaxial layers mounted on the substrate. Patterns are formed above the plurality of epitaxial layers remote from the substrate. A second substrate of a conductive metal is formed on the plurality of epitaxial layers remote from the substrate and between the patterns. The second substrate, the plurality of epitaxial layers and the substrate are at least partially encapsulated with a soft buffer material. The substrate is separated from the plurality of epitaxial layers at the wafer level and while the plurality of epitaxial layers are intact while preserving electrical and mechanical properties of the plurality of epitaxial layers by applying a laser beam through the substrate to an interface of the substrate and the plurality of epitaxial layers, the laser beam having well defined edges.

Abstract: A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates.

Abstract: A high withstand voltage transistor is formed in a high withstand voltage region, and a low withstand voltage transistor is formed in a low withstand voltage region in a method of manufacturing a semiconductor device. The method includes forming a thermal oxide film and a silicon nitride film over the surface of a silicon substrate; forming an opening to the thermal oxide film and the silicon nitride film in each of the high withstand voltage region and the low withstand voltage region; etching the silicon substrate to form trenches; burying a buried oxide film in each of the trenches; removing the thermal oxide film and the silicon nitride film; and forming a thick gate oxide film and a thin oxide film. The depth of a tapered portion of the trench in the low withstand voltage region is shallower than that in the high withstand voltage region.

Abstract: According to one embodiment, a semiconductor memory includes a memory cell provided in a first active area surrounded with a first isolation insulating film, a first transistor provided in a second active area surrounded with a second isolation insulating film, a shield gate electrode on the second isolation insulating film. The bottom surface of the shield gate electrode is positioned more closely to a semiconductor substrate side as compared with the highest upper surface of the second isolation insulating film.

Abstract: A semiconductor memory device includes a first active region, a second active region, a first element isolating region and a second element isolating region. The first active region is formed in a semiconductor substrate. The second active region is formed in the semiconductor substrate. The first element isolating region electrically separates the first active regions adjacent to each other. The second element isolating region electrically separates the second active regions adjacent to each other. An impurity concentration in a part of the second active region in contact with a side face of the second element isolating region is higher than that in the central part of the second active region, and a impurity concentration in a part of the first active region in contact with a side face of the first element isolating region is equal to that in the first active region.

Abstract: A method includes providing a substrate having insulating layers thereon; forming a first trench in a first region of the substrate and a second trench in a second region of the substrate; thermally growing layers of oxide along the sides of the trenches; filling the first trench and the second trench with a polysilicon material, planarizing the polysilicon material, and creating a shallow trench isolation between the first region and the second region, wherein the step f) of creating the shallow trench isolation is performed only after the steps of d) filling and e) planarizing.

Abstract: Novel conjugates of nanoparticles are provided and have particular utility in the detection of latent fingerprints by their ability to bind to a fingerprint residue. The conjugate comprises a nanoparticle attached to a linker group having a terminal reactive moiety, wherein said nanoparticle comprises a core of a first semiconductor material having a first luminescence and a shell of a second material which at least partially surrounds the core. The conjugated nanoparticle can bind to the fingerprint residue and can be detected using fluorescence.

Abstract: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material.

Abstract: A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.

Abstract: Problems with a conventional mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of an insulation film on an inner wall of a mesa groove corresponding to a PN junction, are solved using an inexpensive material, and a mesa type semiconductor device of high withstand voltage and high reliability is offered together with its manufacturing method. A stable protection film made of a thermal oxide film is formed on the inner wall of the mesa groove in the mesa type semiconductor device to cover and protect the PN junction, and an insulation film having negative electric charges is formed to fill a space in the mesa groove covered with the thermal oxide film so that an electron accumulation layer is not easily formed at an interface between an N? type semiconductor layer and the thermal oxide film.

Abstract: In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to an exposed surface of the first layer; heating the structure to a first temperature to enable the filling material to homogeneously fill the plurality of pores; after filling the plurality of pores, performing at least one process on the structure; and after performing the at least one process, removing the filling material from the plurality of pores by heating the structure to a second temperature to decompose the filling material.

Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

Abstract: A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide.

Abstract: A method for forming a lateral passive device including a dual annular electrode is disclosed. The annular electrodes formed from the method include an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate (substrate) is greatly reduced.

Abstract: A method for producing an encapsulation module and/or for encapsulating a micromechanical arrangement, wherein electronic connection provisions are formed from a blank of electrically conductive semiconductor material, by one or more structuring processes and/or etching processes, wherein, in the course of forming the electronic connection provisions, a pedestal of the semiconductor material arises, on which the electronic connection provisions are arranged, wherein the latter are subsequently embedded with an embedding material and the embedding material and/or the semiconductor pedestal are removed after the embedding to an extent such that a defined number of the electronic connection provisions have electrical contacts on at least one of the outer surfaces of the encapsulation module thus produced, wherein upon forming the electronic connection provisions, on the pedestal of the semiconductor material, an insular material hump is formed, on which a plated-through hole is arranged in each case, and which e

Abstract: FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of second element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a second cell array region into a band shape. Each first element isolation insulating film has a level from a surface of the semiconductor substrate, the first charge storage layer has a level from the surface of the semiconductor substrate, and each second element isolation insulating film has a level from the surface of the semiconductor substrate, the level of each first element isolation insulating film being lower than the level of the first charge storage layer and higher than the level of each second element isolation insulating film.

Abstract: A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (?). This results in a lower parasitic capacitance at the body contact region.

Abstract: A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.

Abstract: The present invention relates to an electronic device for providing improved heat transporting capability for protecting heat sensitive electronics and a method for producing the same. The present invention also relates to uses of the electronic device for various applications such as in LED lamps for signalizing, signage, automative and illumination applications or a display apparatus or any combinations thereof.

Abstract: A copper conducting wire structure is for use in the thin-film-transistor liquid crystal display (LCD) device. The copper conducting wire structure includes at least a buffer layer and a copper layer. A fabricating method of the copper conducting wire structure includes the following steps. At first, a glass substrate is provided. Next, the buffer layer is formed on the glass substrate. The buffer layer is comprised of a copper nitride. At last, the copper layer is formed on the buffer layer.

Abstract: A method for forming a semiconductor device with stressed trench isolation is provided, comprising: providing a silicon substrate (S11); forming at least two first trenches in parallel on the silicon substrate and forming a first dielectric layer which is under tensile stress in the first trenches (S12); forming at least two second trenches, which have an extension direction perpendicular to that of the first trenches, in parallel on the silicon substrate, and forming a second dielectric layer in the second trenches (S13); and after forming the first trenches, forming a gate stack on a part of the silicon substrate between two adjacent first trenches, wherein the channel length direction under the gate stack is parallel to the extension direction of the first trenches (S14). The present invention supply tensile stress in the channel width direction of a MOS transistor, so as to improve performance of PMOS and/or NMOS transistors.

Abstract: The fabrication of a touch sensor panel having co-planar single-layer touch sensors fabricated on the back side of a cover glass is disclosed. It can be desirable from a manufacturing perspective to perform all thin-film processing steps on a motherglass before separating it into separate parts. To perform thin-film processing on a motherglass before separation, a removable sacrificial layer such as a photoresist can be applied over the thin-film layers. Next, the motherglass can be scribed and separated, and grinding and polishing steps can be performed prior to removing the sacrificial layer. In alternative embodiments, after the protective sacrificial layer is applied, the bulk of the coverglass can be dry-etched using a very aggressive anisotropic etching that etches primarily in the z-direction. In this embodiment, the etching can be patterned using photolithography to create rounded corners or any other shape. The photoresist can then be removed.