Abstract: A semiconductor device includes a first insulating layer which is formed above a semiconductor substrate including a plurality of semiconductor elements and which includes lower-layer damascene wiring, a second insulating layer which is formed on the first insulating layer and which includes a second damascene wiring and an aligning wiring pattern forming a first step, and a first aligning surface wiring pattern including a surface wiring pattern to cover the second damascene wiring and a first aligning surface wiring pattern which is formed on the aligning wiring pattern and which has a second step reflecting the first step. The surface wiring pattern and the first aligning surface wiring pattern are formed using one surface wiring layer. A novel multilayer wiring structure thus obtained is suitably manufactured by the damascene process.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen.

Abstract: A first insulating film is formed on an underlying substrate, the first insulating film being made of a first insulating material. A second insulating film is formed on the first insulating film, the second insulating film being made of a second insulating material different from the first insulating material. A trench is formed through the second and first insulating film, the trench reaching at least an intermediate depth of the first insulating film. A wiring layer made of a conductive material is deposited on the second insulating film, the wiring layer burying the trench. The wiring layer is polished to leave the wiring layer in the trench. The wiring layer and second insulating film are polished until the first insulating film is exposed. Irregularity such as dishing and erosion can be suppressed from being formed.

Abstract: One aspect of the present invention relates to a method of dual damascene processing, involving forming a plurality of via openings in the insulation structure containing a single layer of a dielectric material; and simultaneously (i) forming a plurality of trenches in the insulation structure, each trench positioned along the substantially straight line of a group of via openings, and (ii) monitoring the formation of trenches using a scatterometry system to determine trench depth, and terminating forming the trenches when a desired trench depth is attained.

Abstract: Disclosed is a method of forming a copper wiring in a semiconductor device. A copper barrier metal layer and a copper seed layer are sequentially formed along the surface of an interlayer insulating film including damascene patterns. In a state that a wafer is then loaded onto an electrical plating apparatus in which a copper plating solution is filled and a negative (−) power supply is also applied to the wafer, copper is plated so that the damascene patterns are sufficiently filled, thereby forming a copper layer. Next, the copper layer is polished in the plating solution by means of the electro-polishing process by changing the negative (−) power supply to the positive (+) power supply. Due to this, the surface of the copper layer is flat over the entire wafer. Thereafter, a chemical mechanical polishing process is performed until the surface of the interlayer insulating film is exposed, thereby forming copper wirings within the damascene patterns.

Abstract: A method of forming a dual-implanted gate and a structure formed by the same. Stack structures comprising a polysilicon layer, a sacrificial layer and a mask layer are formed over a substrate with a gate oxide layer thereon. A dielectric layer is formed over the substrate covering the stack structures. The dielectric layer is planarized to expose the upper surface of the mask layer in the first and the second structure. The mask layer is removed to form a plurality of trenches. The stack structures are selectively implanted using ions having different electrical states. The sacrificial layer is removed. Thereafter, a barrier layer is formed over the interior surface of the trenches. A metallic layer is formed over the substrate completely filling the trenches. The dielectric layer is removed to form a plurality of gate structures. Spacers may on the sidewalls of the gate structures as well.

Abstract: A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.

Abstract: A method is described for reducing dishing in a chemical mechanical polishing process performed on a semiconductor wafer having a dielectric layer with trenches and a copper layer deposited over the dielectric layer and filling the trenches in the dielectric layer. The method comprises steps of removing excess copper above the plane of the dielectric surface using a main polishing operation, whereby copper residues are formed above the plane of the dielectric surface, and applying chemical treatment to the surface of the semiconductor wafer in the initial stage of an overpolishing operation, wherein a protective layer over the copper residues and surfaces of copper-filled trenches is formed. The method further comprises steps of removing the copper residues and protective layer thereon above the plane of the dielectric layer in the overpolishing operation, and removing the protective layer over the surfaces of the copper-filled trenches in the overpolishing operation.

Abstract: A method of forming a planarized final copper structure including the following steps. A structure is provided having a patterned dielectric layer formed thereover. The patterned dielectric layer having an opening formed therein. A barrier layer is formed over the patterned dielectric layer, lining the opening. An initial planarized copper structure is formed within the barrier layer lined opening, and is planar with the barrier layer overlying the patterned dielectric layer. The initial planarized copper structure is recessed below the barrier layer overlying the patterned dielectric layer a distance to form a recessed copper structure. Any copper oxide formed upon the recessed copper structure is removed. A conductor film is formed over the recessed, copper oxide-free initial copper structure and the barrier layer.

Abstract: A method of chemical mechanical polishing of a metal damascene structure which includes an insulation layer having trenches on a wafer and a metal layer having a lower portion located in trenches of the insulation layer and an upper portion overlying the lower portion and the insulation layer is provided. The method comprises a first step of planarizing the upper portion of the metal layer and a second step of polishing the insulation layer and the lower portion of the metal layer. In the first step of planarizing the upper portion of the metal layer, the wafer and a polishing pad is urged at an applied pressure p and a relative velocity v in a contact mode between the wafer and the polishing pad to promote an increased metal removal rate. In the second, the insulation layer and the lower portion of the metal layer are polished in a steady-state mode to form individual metal lines in the trenches with minimal dishing of the metal lines and overpolishing of the insulation layer.

Abstract: A silicon substrate on which a silicon dioxide film having a groove is formed is placed on a sample stage disposed in a vacuum chamber. Subsequently, a titanium film and a tungsten film are deposited sequentially on the silicon dioxide film. The surface of the tungsten film is nitrided by using a plasma under the pressure maintained at 10 Pa or higher inside the vacuum chamber, so as to form a tungsten nitride film. After a copper film is deposited on the tungsten nitride film, the portions of the titanium film, tungsten film, tungsten nitride film, and copper film located outside the groove are removed, thus forming a buried interconnecting wire made of copper.

Abstract: Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.

Abstract: The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon. The diffusion barrier layer is then deposited on the copper silicide layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the copper silicide layer thereon, and depositing a silicon nitride diffusion barrier layer on the copper silicide layer.

Abstract: After a plurality of grooves are formed in an insulating film and in an anti-reflection film on the insulating film, a barrier metal film and a conductive film are deposited on the anti-reflection film such that each of the wiring grooves is filled therewith. Subsequently, the portions of the conductive film outside the grooves are removed by polishing and then the portions of the barrier metal film outside the wiring are removed by polishing. Thereafter, a foreign matter adhered to a surface to be polished during polishing is removed and then a surface of the anti-reflection film is polished.

Abstract: A metal interconnect structure and method for making the same provides an alloying elements layer that lines a via in a dielectric layer. The alloying element layer is therefore inserted at a critical electromigration failure site, i.e., at the fast diffusion site below the via in the underlying metal. Once the copper fill is performed in the via, an annealing step allows the alloying element to go into solid solution with the copper in and around the via. The solid solution of the alloying element and copper at the bottom of the via in the copper line improves the electromigration reliability of the structure.

Abstract: This invention relates to a method of dual damascene integration for manufacture of integrating circuits using three top hard mask layers having alternating etch selectivity characteristics.

Abstract: A new method for forming a high quality cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A thermal oxide layer is grown overlying the semiconductor substrate. A titanium layer is deposited overlying the thermal oxide layer. A cobalt layer is deposited overlying the titanium layer. A titanium nitride capping layer is deposited over the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. The substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide to complete formation of a cobalt disilicide film in the manufacture of an integrated circuit.

Abstract: Methods for fabricating semiconductor structures having LowK dielectric properties are provided. In one example, a copper dual damascene structure is fabricated in a LowK dielectric insulator including forming a capping film over the insulator before features are defined therein. After the copper is formed in the features, the copper overburden is removed using ultra-gentle CMP, and then the barrier is removed using a dry etch process. Following barrier removal, a second etch is performed to thin the capping film. The thinning is configured to reduce the thickness of the capping film without removal, and thereby reducing the K-value of the LowK dielectric structure.

Abstract: The present invention relates to a method for fabricating a semiconductor device having a diffusion barrier layer with a Cu line to prevent degradation in performance of the diffusion barrier layer. The present invention provides a method for fabricating a semiconductor device, including the steps of: depositing a tertiary nitride containing Ti, W and N on a substrate loaded inside of a reactive deposition chamber; and densifying the tertiary nitride and performing a reforming process for filling a surface of the tertiary nitride with oxygen. Also, the present invention provides a method for fabricating a semiconductor device, including the steps of: forming a conductive layer on top of a substrate; forming a diffusion barrier layer constructed with titanium (Ti), tungsten (W) and nitrogen (N) on the conductive layer; and forming a Cu line on the diffusion barrier layer.

Abstract: Systems and methods to remove a first material located on a top surface of a workpiece are presented according to one aspect of the present invention. According to an exemplary method, the pad including a second material is positioned proximate to the workpiece so that a front surface of the pad contacts an exposed surface of the first material. The front surface of the pad is mechanically moved against the exposed surface of the first material to initiate a chemical reaction between the first material and the second material that yields a reaction product. The reaction product may be removed by using a chemical solution, by using the mechanical movement of the pad against the exposed surface of the first material or both.

Abstract: A semiconductor device (118) and method of fabrication thereof, wherein a plurality of conductive lines (124) are formed over a workpiece, a surface-smoothing conductive material (140) is disposed over the conductive lines 124), and a magnetic material (132) disposed is over the surface-smoothing conductive material (140). The surface-smoothing conductive material (140) has a smaller grain structure than the underlying conductive lines (124). The surface-smoothing conductive material (140) is polished so that the surface-smoothing conductive material (140) has a texturally smoother surface than the surface of the conductive lines (124).

Abstract: In a method for the production of semiconductor devices of the type in which a layer of Ti/TiN overlies a layer of fluoro-silicate glass, a layer of material of low dielectric constant is deposited between the layer of Ti/TiN and the layer of fluoro-silicate glass.

Abstract: The present invention generally relates to a dual damascene processing method using a silicon rich oxide (SRO) layer thereof and its structure. In the dual damascene process, a first dielectric layer, an etching stop layer, such as a silicon rich oxide layer, and a second dielectric layer are sequentially formed on a semiconductor substrate, which is provided with metal connections therein. Then, the present invention utilizes photolithography and etching technique to obtain a dual damascene structure profile having a trench and a via hole. The present invention uses the silicon rich oxide layer as the etching stop layer so as the present invention can achieve a better trench microloading and better bottom profile. Beside, the present invention does not increase the dielectric constant index (K) of the inter metal dielectric (IMD).

Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally liable groups with nitrous oxide, oxygen, ozone, or other source of reactive oxygen in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.

Abstract: A method for fabricating vias and trenches in a dual-damascene multilevel interconnection structure of an integration circuit is provided. The method uses chemical vapor deposition and flowfill dielectric technology to deposit a dielectric material at low temperature for fabricating interconnection structure in an integration circuit. It comprises the following steps: (a) forming photo-resist patterns; (b) depositing a dielectric layer at low temperature by chemical vapor deposition and flowfill dielectric technologies; (c) removing the dielectric layer by chemical-mechanical polishing to expose the photo-resist patterns; (d) removing the photo-resist patterns by chemical-mechanical polishing; and (e) stabilizing the dielectric layer by thermal curing.

Abstract: In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.

Abstract: A method for improving a photolithographic patterning process to avoid undeveloped photoresist contamination in a semiconductor manufacturing process including providing a semiconductor wafer having a process surface including a first anisotropically etched opening extending through a semiconductor wafer thickness portion including an underlying dielectric insulating layer; blanket depositing a polymeric resinous layer over the semiconductor wafer process surface to include filling the first anisotropically etched opening; curing the polymeric resinous layer by exposing the polymeric resinous layer to at least one of thermal or photonic energy to initiate polymer cross linking; chemically mechanically polishing (CMP) the polymeric resinous layer to substantially remove the polymeric resinous layer thickness above the process surface; and, forming a photolithographically patterned photoresist layer over the process surface for forming a second anisotropically etched opening overlying and encompassing the first

Abstract: Methods for making an aluminum-containing metallization structure, methods and solutions for cleaning a polished aluminum-containing layer, and the structures formed by these methods. The methods for making the aluminum-containing metallization structure are practiced by providing a substrate, forming a metal layer with an upper surface containing aluminum over the substrate, polishing the metal layer, and contacting the polished surface of the metal layer with a solution comprising water and at least one corrosion-inhibiting agent. The method for cleaning the polished aluminum-containing layer is practiced by contacting a polished aluminum-containing layer with a solution comprising water and a corrosion-inhibiting agent. In these methods and solutions, the water may be deionized water, the corrosion-inhibiting agent may be citric acid or one of its salts, and the solution may contain additional additives, such as chelating agents, buffers, oxidants, anti-oxidants, and surfactants.

Abstract: The present invention is a semiconductor wafer, and a method of fabricating the semiconductor wafer, that reduces dishing over large area features in chemical-mechanical polishing processes. The semiconductor wafer has a substrate with an upper surface, a large area feature formed on the substrate, and a separation layer deposited on the substrate. The separation layer has a top surface and a cavity extending from the top surface towards the upper surface of the substrate. The large area feature is positioned in the cavity of the separation layer, and a support pillar is positioned in the cavity. In one embodiment, the pillar has a base positioned between components of the large area feature and a crown positioned proximate to a plane defined by the top surface of the separation layer. In operation, the pillar substantially prevents the polishing pad of a polishing machine from penetrating into the cavity beyond the top surface of the separation layer.

Abstract: Formed on a substrate are an inorganic interlayer film, an organic interlayer film, a lower mask made of silicon oxide and an upper mask made of silicon nitride in this order. An opening is formed in the upper mask. Then, a cover mask made of silicon oxynitride and having a film thickness of 20 to 100 nm is formed on the upper mask. Thereafter, an Anti-Reflection Coating film and a resist film are formed thereon. Subsequently, the Anti-Reflection Coating film, the cover mask and the lower mask is etched using the resist film as a mask. Then, the organic interlayer film and the inorganic interlayer film are etched using the cover mask as a mask to form a via hole. Simultaneously, the cover mask is removed to make the upper mask exposed. Thereafter, the organic interlayer film is etched using the upper mask as a mask to form an interconnect trench.

Abstract: A composition for removing side wall which includes an aqueous solution containing both nitric acid and at least one of carboxylic acids selected from the group consisting of polycarboxylic acid, aminocarboxylic acid, and salts thereof; a method of removing side wall; and a process for producing a semiconductor device. Use of the composition is effective in removing side wall at a low temperature in a short time in semiconductor device production without corroding the wiring material, e.g., an aluminium alloy. Thus, a semiconductor device having an aluminium alloy wiring which has undergone substantially no corrosion can be efficiently produced.

Abstract: In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.

Abstract: Particulate and metal ion contamination is removed from a surface, such as a semiconductor wafer containing copper damascene or dual damascene features, employing a fluoride-free aqueous composition comprising a dicarboxylic acid and/or salt thereof; and a hydroxycarboxylic acid and/or salt thereof or amine group containing acid.

Abstract: A method of fabricating a semiconductor device, including at least the steps of (a) forming a via-hole or trench throughout an electrically insulating layer, (b) forming a wiring material layer on the electrically insulating layer such that the via-hole or trench is filled with the wiring material layer, (c) annealing the wiring material layer, (d) cooling the wiring material layer down to a temperature equal to or lower than a predetermined temperature, and (e) applying chemical mechanical polishing (CMP) to the wiring material layer such that the wiring material layer exists only in the via-hole or trench. The step (c) is carried out prior to the step (e), and the step (d) is carried out after the step (c).

Abstract: A method of fabricating a semiconductor device using a damascene metal gate including the steps of forming a damascene gate oxide layer and a damascene gate electrode on a semiconductor substrate, forming a trench at an upper part of the damascene gate electrode by selectively etching a portion of the damascene gate electrode to a predetermined thickness, forming an insulating layer in the trench on the damascene gate electrode, forming an insulating interlayer on an upper surface of the entire structure, and forming a contact hole exposing a portion of the semiconductor substrate by selectively etching the insulating interlayer.

Abstract: A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer and depositing a second hard mask layer on the first hard mask layer, where the second hard mask layer is an amorphous silicon layer. Afterwards, formation of the dual damascene structure is completed by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material.

Abstract: In a method of forming damascene metallization lines on a substrate by electroplating and chemical mechanical polishing, the metal layer thickness profile is shaped in correspondence to the removal rate during the chemical mechanical polishing. Thus, any non-uniformity of the chemical mechanical polishing process may be compensated for by appropriately depositing the metal layer so that erosion and dishing of the finally obtained metal lines are within tightly selected manufacturing tolerances.

Abstract: A process for performing CMP in two steps is described. After trenches have been formed and over-filled with copper, in a first embodiment of the invention a hard pad is used initially to remove most of the copper until a point is reached where dishing effects would begin to appear. A soft pad is then substituted and CMP continued until all copper has been removed, except in the trenches. In a second embodiment, CMP is initiated using a pad to which high-pressure is applied and which rotates relatively slowly. As before, this combination is used until the point is reached where dishing effects would begin to appear. Then, relatively low pressure in combination with relatively high rotational speed is used until all copper has been removed, except in the trenches. Both of these embodiments result in trenches which are just-filled with copper, with little or no dishing effects, and with all traces of copper removed everywhere except in the trenches themselves.

Abstract: A process of forming an anti-fuse. First, an inter-metal dielectric layer, in which a funnel-shaped via is formed, is formed on a substrate. Next, a first conductive layer is formed over the substrate and filled into the funnel-shaped via. Subsequently, by, for example, a chemical mechanical polishing process, the first conductive layer outside the funnel-shaped via is removed to form a conductive plug. Afterward, an oxide chemical mechanical polishing process is performed to smooth the surface of the conductive plug. Next, a dielectric layer is formed on the top side of the conductive plug, and then a top plate is formed on the dielectric layer. Subsequently, an insulating layer is formed over the substrate, wherein the insulating layer is provided with a via and the via exposes the top plate. Finally, a second conductive layer is formed over the substrate and filled into the via.

Abstract: Planarization of the top surfaces of layers that are more than about a micron thick is beset with problems not encountered in thinner layers. These problems have been overcome by means of a process that, initially allows the formation of ‘horns’ in the surface that is to be planarized. Said horns are then selectively etched away while other parts of the surface are protected, following which CMP is initiated and the surface gets planarized. A total of four embodiments are disclosed.

Abstract: Shallow trench isolation techniques are disclosed in which a thin nitride layer is formed on a semiconductor substrate, and a trench is formed through the nitride layer and into the semiconductor substrate, which is then filled. The wafer is then planarized using a fixed-abrasive CMP process to mitigate or avoid step height in the shallow trench isolation process. The nitride layer is then removed following planarization.

Abstract: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (102), forming a dielectric layer (104) over the semiconductor substrate (102), and etching a trench structure (106) or a via structure (106) in the dielectric layer (104) to expose a portion of a surface of the semiconductor substrate (102). The method also includes the steps of treating a surface (104a) of the dielectric layer (104) with an adhesion solution, such as a reactive plasma including hydrogen, and forming a diffusion barrier layer (110) over the dielectric layer (104). Moreover, the adhesion solution chemically interacts with the surface (104a) of the dielectric layer (104) and enhances or increases adhesion between dielectric layer (104) and diffusion barrier layer (110).

Abstract: In a method of forming damascene metallization lines on a substrate by electroplating and chemical mechanical polishing, the metal layer thickness profile is shaped in correspondence to the removal rate during the chemical mechanical polishing. Thus, any non-uniformity of the chemical mechanical polishing process may be compensated for by appropriately depositing the metal layer so that erosion and dishing of the finally obtained metal lines are within tightly selected manufacturing tolerances.

Abstract: Disclosed is a method to achieve the planarization of a BPSG film and reduction of micro-scratches on a BPSG film by the CMP method. A BPSG film is deposited over a main surface of a substrate on which MISFETs have been formed, and then, a surface of the BPSG film is planarized by the CMP method. Thereafter, a thermal treatment is performed to the substrate to reflow the BPSG film, thereby removing the micro-scratches on the surface of the BPSG film caused by the polishing. At this time, the amount of polishing of the surface of the BPSG film is controlled within a range of 90 to 300 nm, preferably 100 to 250 nm, and more preferably 120 to 200 nm.

Abstract: A semiconductor manufacturing process that includes providing an insulating material, providing a first photoresist over the insulating material, defining and patterning the first photoresist, anisotropically etching the insulating material to form at least one groove in the insulating material, removing the first photoresist, providing a second photoresist over the insulating material, defining and patterning the second photoresist to form a plurality of tops and sidewalls, depositing a layer of carbon-fluoride material over the tops and sidewalls of the defined and patterned second photoresist, and anisotropically etching the insulating layer to form at least one opening, wherein the at least one opening is aligned with the at least one groove.

Abstract: An improved via and contact hole fill composition and method for using the composition in the dual damascene production of circuits is provided. Broadly, the fill compositions include a quantity of solid components including a polymer binder and a solvent system for the solid components. The boiling point of the solvent system is less than the cross-linking temperature of the composition. Preferred solvents for use in the solvent system include those selected from the group consisting of alcohols, ethers, glycol ethers, amides, ketones, and mixtures thereof. Preferred polymer binders are those having an aliphatic backbone and a molecular weight of less than about 80,000, with polyesters being particularly preferred.

Abstract: Within a damascene method for forming a patterned conductor layer having formed interposed between its patterns a dielectric layer formed of a comparatively low dielectric constant dielectric material method, there is employed a hard mask layer formed upon the dielectric layer. The hard mask layer is formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency power of from about 100 to about 500 watts per square centimeter substrate area. The hard mask layer provides for attenuated abrasive damage to the dielectric layer.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality. An alternating process can also be arranged by selection of pulse separation and/or pulse duration to achieve reduced conformality relative to a self-saturating, self-limiting atomic layer deposition (ALD) process. In still another arrangement, layers with anisotropic pore structures can be sealed by selectively melting upper surfaces. Blocking is followed by a self-limiting, self-saturating atomic layer deposition (ALD) reactions without significantly filling the pores.

Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.

Abstract: A method is provided for manufacturing a semiconductor device having a multilayer wiring structure in which at least one insulating film is formed with a set of conducting portions which are electrically connected to each other to have a surface area of no less than 500 &mgr;m2 and which include a wiring having a width of no more than l.0 &mgr;m. The method includes a polishing step (501) for flattening the conducting portions together with the insulating film by chemical mechanical polishing, a chemical cleaning step (502) for cleaning the flattened surface of the insulating film with a cleaning liquid, and a rising step (503) for removing the cleaning liquid using a rinsing liquid. The rinsing step is performed using water with a dissolved oxygen concentration decreased to no more than 6 ppm by weight as the rinsing liquid.