Abstract: A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.

Abstract: Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing process to form a copper wiring within a damascene pattern. At this time, the chemical mechanical polishing process is overly performed so that the top surface of the copper wiring is concaved and is lower than the surface of the interlayer insulating film of the low dielectric constant neighboring it. Furthermore, an annealing process is performed so that the top surface of the copper wiring is changed from the concaved shape to a convex shape while stabilizing the copper wiring. A copper anti-diffusion insulating film is then formed on the entire structure including the top surface of the copper wiring having the convex shape.

Abstract: The disclosure relates to a method and apparatus for enhancing copper film quality with a two-step deposition. The two step deposition may include depositing a first copper film by electrochemical plating, annealing the first copper film at a desired temperature for a duration of time to remove any impurities, depositing a second copper film and annealing the second copper film for a duration of time to remove impurities. The second copper film can be deposited by electrochemical plating without HCl/C-based additive. The second copper film can also be deposited by sputtering to avoid impurities including C, Cl and S.

Abstract: A method for forming metrology structures for a CMP process is described. A trench edge is formed in a base material or stack of materials which are preferably deposited as part of the process of fabricating the production structures on the wafer. A covering film of a second material with preferably with contrasting SEM properties is deposited over the trench edge in the base material. During CMP the covering film is preferentially worn away at the edge revealing the base material. The width of the base material which has been revealed is a measure of the progress of the CMP. Since the base material and the covering material are preferably selected to have contrasting images in an SEM, a CD-SEM can be used to precisely measure the CMP progress.

Abstract: A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.

Abstract: On a substrate are sequentially formed a first interconnection 203, a diffusion barrier film 205 and a second insulating film 207, and on the upper surface of the second insulating film 207 is then formed a sacrificial film 213. Next, a via hole 211 and an interconnection trench 217 are formed, and on the sacrificial film 213 are then formed a barrier metal film 219 and a copper film 221. CMP for removing the extraneous copper film 221 and barrier metal film 219 are conducted in a two-step process, i. e., the first polishing where polishing is stopped on the surface of the barrier metal film 219 and the second polishing where the remaining barrier metal film 219 and the tapered sacrificial film 213 are polished.

Abstract: In the forming process of buried wirings by filling wiring trenches formed in an insulator with a conductive film mainly made of Cu, the buried wirings are formed to have a uniform-height regardless of the width and density of the wiring trenches. When polishing a barrier conductor film comprised of a Ta film in the CMP process for forming the buried wirings, the polishing agent, which controls the removal rate of the underlying insulator of a silicon oxide film relative to the barrier conductor film to almost one twentieth or less, is used as the slurry, and the pad which is made of polyurethane with a hardness of 75 degrees or more measured by the Type E durometer in conformity with the JIS K6253 and which is comprised of the foam including non-uniform pores with a diameter of about 150 ?m or larger and a density of about 0.4–0.16 g/cm3, is used as the polishing pad.

Abstract: An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

Abstract: A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask layer and organic dielectric layer to leave a dummy portion overlying the via opening; forming an oxide liner over the dummy portion; forming a second dielectric insulating layer over the oxide liner to surround the dummy portion; planarizing the second dielectric insulating layer to expose the upper portion of the dummy portion; and, removing the organic dielectric layer to form a dual damascene opening including the oxide liner lining trench line portion sidewalls.

Abstract: A chemical mechanical polishing stopper film comprising at least one organic polymer, said film having a dielectric constant of 4 or lower, and a chemical mechanical polishing method. The chemical mechanical polishing method comprises forming a chemical mechanical polishing stopper film comprising at least one organic polymer on an insulating film so that the stopper film is interposed between the insulating film and a metal film to be removed by chemical mechanical polishing, and then removing the metal film with a chemical mechanical polishing slurry.

Abstract: The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, includes a substantially planar ferroelectric dielectric layer (165) located over a first electrode layer (160), wherein the substantially planar ferroelectric dielectric layer (165) has an average surface roughness of less than about 4 nm. The ferroelectric capacitor (100) further includes a second electrode layer (170) located over the substantially planar ferroelectric dielectric layer (165).

Abstract: The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer 140. The method further comprises exposing the opening and the underlying copper layer to a plasma-free reducing atmosphere 200 in the presence of a thermal anneal. The also comprises depositing a barrier layer in the exposed opening and on the exposed underlying copper layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.

Abstract: Damascene processing is implemented with dielectric barrier films (50, 90, 91) for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films (50, 31) to avoid misalignment problems. Embodiments further include dual damascene (100A, 100B) processing using Cu metallization (100).

Abstract: According to one exemplary embodiment, a method comprises a step of etching a trench in an ILD layer, said trench having sidewalls and a bottom surface. The method further comprises determining a height of the sidewalls of the trench. The method further comprises filling the trench with interconnect metal such the interconnect metal extends above the trench. According to this exemplary embodiment, the method further comprises performing a CMP process to remove a portion of the interconnect metal. In the present invention, the height of the sidewalls of the trench is utilized to control an amount of polishing performed in the CMP process. The remaining portion of interconnect metal in the trench forms an interconnect line, where the thickness of the interconnect line is controlled by utilizing the height of the sidewalls of the trench to control the amount of polishing in the CMP process.

Abstract: The present invention relates to a process for forming a near-planar or planar layer of a conducting material, such as copper, on a surface of a workpiece using an ECMPR technique. The process preferably uses at least two separate plating solution chemistries to form a near-planar or planar copper layer on a semiconductor substrate that has features or cavities on its surface.

Abstract: The invention generally provides methods and compositions for planarizing a substrate surface having underlying dielectric materials. Aspects of the invention provide compositions and methods using a combination of low polishing pressures, polishing compositions, various polishing speeds, selective polishing pads, and selective polishing temperatures, for removing barrier materials by a chemical mechanical polishing technique with minimal residues and minimal seam damage. Aspects of the invention are achieved by employing a strategic multi-step process including sequential CMP at low polishing pressure to remove the deposited barrier materials.

Abstract: Provided is a method for forming a metal line in a semiconductor device. The method forms round portions at top edges of an insulation film by means of a polymer and then etches the rest portion (i.e., sidewall parts) in an almost vertical direction, which makes it possible to shrink down a width of a patterned insulation film at maximum nevertheless of a dimension of a metal-line patterning mask. By way the method, an interval between adjacent metal lines is extended at maximum, preventing mutual interference between the metal lines.

Abstract: An interlayer insulation film for multilayer interconnect of a semiconductor integrated circuit is formed by forming a first insulation film on a substrate by plasma CVD using a silicon-containing hydrocarbon gas; and continuously forming a second insulation film on the first insulation film at a thickness less than the first insulation film in situ by plasma CVD using a silicon-containing hydrocarbon gas and an oxidizing gas. The second insulation film has a hardness of 6 GPa or higher and is used as a polishing stop layer.

Abstract: A method for forming dual damascene features in a dielectric layer. Vias are partially etched in the dielectric layer. A trench pattern mask is formed over the dielectric layer. Trenches are partially etched in the dielectric layer. The trench pattern mask is stripped. The dielectric layer is further etched to complete etch the vias and the trenches in the dielectric layer.

Abstract: In a method of forming a metal wiring line, a first insulating film is formed directly or indirectly on a semiconductor substrate. A second insulating film is formed on the first insulating film. A wiring line groove is formed to pass through the second insulating film to an inside of the first insulating film. A conductive film is formed to fill the wiring line groove and to cover the second insulating film. The conductive film and the second insulating film are removed by a first CMP polishing process, using the first insulating film as a stopper film, until the first insulating film is exposed.

Abstract: One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

Abstract: It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, disclosed is a method in which, e.g., a high density plasma silicon oxide film is deposited on wirings (e.g., a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell) by means of a high density plasma CVD technique, at a first temperature, and the structure is subjected to RTA (heat treatment) at a second temperature higher than the first temperature (e.g., 750° C.). Via holes are then formed in the high density plasma silicon oxide film, and first and second conductive films are then formed, the first conductive film being formed in the via holes and at a third temperature lower than the first temperature. The first and second conductive layers are then polished to remain selectively within the via holes.

Abstract: A method includes steps of: (a) providing a wafer on which a film has been deposited; (b) exposing an annular area in an edge exclusion zone of the wafer to radiation having a wavelength suitable for patterning the film in the annular area; and (c) modulating the radiation while exposing the annular area to form a pattern in the film in the annular area.

Abstract: Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed. In one embodiment, the method includes simultaneously generating BEOL wiring over a first circuit using a dual damascene structure in a first dielectric layer, and BEOL wiring over a second circuit using a single damascene via structure in the first dielectric layer. Then, simultaneously generating BEOL wiring over the first circuit using a dual damascene structure in a second dielectric layer, and BEOL wiring over the second circuit using a single damascene line wire structure in the second dielectric layer. The single damascene via structure has a width approximately twice that of a via portion of the dual damascene structures and the single damascene line wire structure has a width approximately twice that of a line wire portion of the dual damascene structures.

Abstract: A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.

Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The method comprises depositing a conductive material over a substrate to fill a contact opening, removing excess material from the substrate leaving the contact within the opening, and then heating treating the contact at a high temperature, preferably with a rapid thermal anneal process, in a reactive gas to remove an undesirable component from the contact, for example, thermal annealing a TiCl4-based titanium nitride in ammonia to remove chlorine from the contact, which can be corrosive to an overlying aluminum interconnect at a high concentration. The contacts are useful for providing electrical connection to active components in integrated circuits such as memory devices. In an embodiment of the invention, the contacts comprise boron-doped and/or undoped TiCl4-based titanium nitride having a low concentration of chlorine.

Abstract: Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a polishing pressures of about 2 psi or less and at platen rotational speeds of about 200 cps or greater. The polishing process may use an abrasive-containing polishing composition having up to about 1 wt. % of abrasives. The polishing process may be integrated into a multi-step polishing process.

Abstract: A buried film and a barrier film are polished together using a slurry in which the polishing rate on a substrate material (in particular, silicon oxide), that on a buried-film material (in particular, tungsten) and that on a barrier-film material (in particular, titanium oxide) are substantially equal to one another. This can materialize a buried structure free from any step or steps, at a high polishing rate.

Abstract: A method for forming a wire line by a damascene process includes forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a contact hole, and forming a first conductive layer over the first insulating layer that fills the contact hole. The first conductive layer is patterned, and a storage node contact is formed that fills the contact hole and is electrically connected to the semiconductor substrate. A hard mask is formed over the storage node contact and the first insulating layer is etched using the hard mask as an etch mask to form a trench in the first insulating layer. A bit line is formed in the trench that is electrically connected to the semiconductor substrate. A second insulating layer is formed that covers the bit line. The second insulating layer and the hard mask are planarized and a storage node of a capacitor is formed on the storage node contact.

Abstract: A structure incorporates very low dielectric constant (k) insulators with copper wiring to achieve high performance interconnects. The wiring is supported by a relatively durable low k dielectric such as SiLk or SiO2 and a very low k and less-robust gap fill dielectric is disposed in the remainder of the structure, so that the structure combines a durable layer for strength with a very low k dielectric for interconnect electrical performance.

Abstract: A process of removing excess conductive material from the exposed surface of a dielectric layer, the process comprising the steps of forming a shield layer on the dielectric layer, forming a sacrificial layer on top of the shield layer, depositing the conductive material on top of the sacrificial layer so that the conductive material is positioned within cavities in the dielectric material, and then using chemical mechanical planarization to remove the excess conductive material and the sacrificial layer. The use of a sacrificial layer interposed between the shield layer and the excess conductive material allows for chemical mechanical planarization to fully remove the sacrificial layer to facilitate more uniform removal of excess conductive material.

Abstract: A method for forming a metal interconnection layer of a semiconductor device comprises forming a film including a material selective to a medium used in an ashing process on an interlayer insulating film. The method comprises transforming the film during the ashing process to form an interconnection pattern having a dual damascene structure. A dielectric material such as copper is deposited on the interconnection pattern, which is planarized through CMP, thereby forming a via contact having a single damascene structure without a recess therein.

Abstract: A semiconductor device which effectively reduces copper oxide layers on copper conductive lines is disclosed. The method includes forming a first insulating layer on a semiconductor substrate; forming a first conductive line by depositing a conductive material on the first insulating layer and selectively patterning the conductive material. A second insulating layer is deposited on top of the substrate including on the first conductive line. A via hole is formed by selectively patterning the second insulating layer to expose a certain portion of the first conductive line. A natural oxide layer is removed by plasma-processing the natural oxide layer using H2+CO gas.

Abstract: Disclosed in a method of forming a metal line in a semiconductor device. The method includes the steps of sequentially forming a first etch stop film, a second interlayer insulating film and a BARC film on a first interlayer insulating film into which a metal line is buried, forming a photoresist pattern defining a trench in a given region of the BARC film, performing an etch process up to the second interlayer insulating film using the photoresist pattern as an etch mask to form a trench, removing the photoresist pattern and the BARC film by means of a first wet etch process, etching the first etch stop film by means of a second wet etch process using the second interlayer insulating film an as etch mask, and cleaning the resulting entire surface by means of a third wet etch process.

Abstract: A wiring of a semiconductor device and a method of manufacturing the same are disclosed. A first conductive layer is formed on a semiconductor substrate followed by a first insulation material which is deposited on the first conductive layer to form a first insulation layer. Then, a CMP process is implemented to form the first insulation layer. A second insulation layer is formed by depositing a second insulation material on the first insulation layer in order to cover a scratch formed on the first insulation layer after implementing the CMP process. A first etching pattern is formed by etching the second insulation layer to a thickness less than a thickness of the second insulation layer. Thereafter, a conductive material is deposited on the etching pattern and then a planarizing process is implemented to form a conductive pattern having a damascene shape.

Abstract: A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces.

Abstract: The present invention defines a system (200) for selectively controlling post-CMP dishing effects occurring in semiconductor wafers having copper metallization. The system has a CMP system (202) that performs copper overpolish and barrier polish on a copper-based semiconductor wafer (206). A profilometer (204) measures actual dishing occurring in the copper metallization after polishing. An input data set (220) includes a dishing target for the semiconductor wafer. A data integrity function (212) evaluates the profilometer's measurement, and generates an indicator of the reliability of the measurement. A modeling function (214) receives the measurement, the indicator, and the dishing target, and evaluates any differential between the dishing target and actual dishing. The modeling function generates a processing target to eliminate the differential, and modifies this process responsive to the indicator.

Abstract: A polishing slurry for CMP of an SiC series compound film, includes colloidal silica having a primary particle diameter ranging from 5 nm to 30 nm, and at least one acid selected from the group consisting of an amino acid having a benzene ring and an organic acid having a heterocycle.

Abstract: A method of protecting an underlying diffusion barrier layer in a dual damascene trench and via etch process with a coating of negative photoresist. The dual damascene process starts with via hole etching in an intermetal dielectric (IMD) layer. Next, the thin film barrier layer is deposited and patterned to fill the bottom of the vias. The key process step is a coating of negative photoresist which is exposed and developed to partially fill the via openings. This thick layer of negative photoresist in the vias protects the thin diffusion barrier layer from subsequent dual damascene etch processing.

Abstract: An interconnect structure for use in semiconductor devices which interconnects a plurality of dissimilar metal wiring layers, which are connected vias, by incorporating shaped voids in the metal layers. The invention also discloses a method by which such structures are constructed.

Abstract: A polishing method comprises supplying a polishing liquid to an upper portion of a film to be polished to carry out first polishing, the film being provided on a layer having a groove with a predetermined pattern so as to be filled therewith, after the first polishing, polishing the film to carry out clean polishing while supplying one of distilled water and a cleaning liquid thereto, and after the clean polishing, polishing a residual portion of the film remaining outside of the groove by supplying a polishing liquid to carry out second polishing.

Abstract: A method for reducing the topography from CMP of metal layers during the semiconductor manufacturing process is described. Small amounts of solute are introduced into the conductive metal layer before polishing, resulting in a material with electrical conductivity and electromigration properties that are very similar or superior to that of the pure metal, while having hardness that is more closely matched to that of the surrounding oxide dielectric layers. This may allow for better control of the CMP process, with less dishing and oxide erosion a result. A secondary benefit of this invention may be the elimination of superficial damage and embedded particles in the conductive layers caused by the abrasive particles in the slurries.

Abstract: A method for capping copper or copper alloy interconnects. A dielectric layer is formed overlaying a semiconductor substrate. An opening is formed in the dielectric layer and subsequently embedded copper or copper alloy form an interconnect structure. A silicon layer is formed on the copper or copper alloy by sputtering or chemical vapor deposition. A copper silicide layer is formed by reacting the silicon layer with the underlying copper or copper alloy as a capping layer.

Abstract: A low-k interconnect dielectric layer is strengthened by forming pillars of hardened material in the low-k film. An E-beam source is used to expose a plurality of pillar locations. The locations are exposed with a predetermined power and exposure time to convert the low-k film in the selected locations to pillars having higher hardness and strength than the surrounding portions of the low-k film.

Abstract: A scheme for filling plugs through chemical mechanical polishing comprises depositing a malleable conductive layer over a dielectric layer having openings formed therein. The malleable conductive layer is deposited such that a liner is formed within the openings, however the openings are not completely filled. A chemical mechanical polishing process using an alumina based slurry at a neutral or slightly basic pH and no oxidizer is used to smear the malleable conductive layer sufficiently to fill the remainder of the openings in the dielectric layer forming filled or substantially filled plugs.

Abstract: In one aspect, the present invention monitors a signal corresponding to a torque value of a motor that is used to maintain relative motion between a conductive top surface of a workpiece and a workpiece surface influencing device in the presence of physical contact between the conductive top surface of the workpiece and the workpiece surface influencing device. In another aspect, the present invention uses the signal to control a force applied to a top conductive surface of a workpiece during electrotreatment.

Abstract: A method of forming buried wiring, includes the steps of forming an insulating layer having a trench on a semiconductor substrate; forming a conductive layer mainly composed of copper on the insulating layer in such a manner that the trench is filled with the conductive layer; removing an oxide layer generated in a surface of the conductive layer by oxidation; forming a cap layer made of a material having less mechanical strength than the oxide layer, on the conductive layer; and removing the cap layer and a part of the conductive layer by chemical mechanical polishing in such a manner that the conductive layer is left in the trench.

Abstract: The present invention provides a method for forming a low-k dielectric structure on a substrate 10 that includes depositing, upon the substrate, a dielectric layer 12. A multi-film cap layer 18 is deposited upon the dielectric layer. The multi-film cap layer includes first 181 and second 182 films, with the second film being disposed between the dielectric layer and the first film. The first film typically has a removal rate associated therewith that is less than the removal rate associated with the second film. A deposition layer 20 is deposited upon the multi-film cap layer and subsequently removed. The properties of the multi-film cap layer are selected so as to prevent the dielectric layer from being exposed/removed during removal of the deposition film. In this manner, a deposition layer, having variable rates of removal, such as copper, may be planarized without damaging the underlying dielectric layer.

Abstract: Disclosed is a method for fabricating a semiconductor device. The method comprises the steps of: sequentially forming a first anti-reflection layer and a first photoresist film on a substrate; forming a first image layer; forming a second anti-reflection layer and a second photoresist film; forming a second image layer which opens wider than the first image layer; supplying oxygen plasma to a resultant in order to transfer a pattern of the second image layer on the second anti-reflection layer and to transfer a pattern of the first image layer on the first anti-reflection layer, thereby forming an opening; forming a metal layer; forming a metal pattern to fill the opening; and removing the second image layer, the second anti-reflection layer, the first image layer, and the first anti-reflection layer.

Abstract: A method for forming conductive plugs within an insulation material is described. The inventive process results in a plug of a material such as tungsten which is more even with the insulation layer surface than conventional plug formation techniques. Conventional processes result in recessed plugs which are not easily or reliably coupled with subsequent layers of sputtered aluminum or other conductors. The inventive process uses a two-step chemical mechanical planarization technique. An insulation layer with contact holes is formed, and a metal layer is formed thereover. A polishing pad rotates against the wafer surface while a slurry selective to the metal removes the metal overlying the wafer surface, and also recesses the metal within the contact holes due to the chemical nature and fibrous element of the polishing pad. A second CMP step uses a slurry having an acid or base selective to the insulation material to remove the insulator from around the metal.