Abstract: At the time of performing a polishing process on a tungsten film and a silicon oxide film, based on the relation between a residual step and pattern density preliminarily obtained while changing polishing parameters, from pattern density of plugs in the polishing step and a predetermined residual step required, polishing parameters are determined so that a residual step does not exceed a predetermined residual step “h”. With the determined polishing parameters, the polishing process is performed on the tungsten film and the silicon oxide film so that the films are planarized, and plugs are formed in contact holes. As a result, a semiconductor device in which a step does not exceeds a predetermined residual step by a polishing process is obtained.

Abstract: A method of reducing or substantially eliminating the number of tungsten plug pullouts and consequential chip failures by controlling the CMP step of removing the overfilled tungsten so as to leave a thin layer of tungsten instead of continuing the removal down to the top surface of the dielectric layer.

Abstract: Apparatus and methods forming electrostatic discharge and electrical overstress protection devices for integrated circuits wherein such devices include shared electrical contact between source regions and between drain regions for more efficient dissipation of an electrostatic discharge. The devices further include contact plugs and contact lands which render the fabrication of the devices less sensitive to alignment constraint in the formation of contacts for the device.

Abstract: A method for preventing peeling of a metal layer formed over a semiconductor wafer process surface during a chemical mechanical polishing (CMP) process including providing a semiconductor wafer having a process surface comprising a periphery portion and a central portion said central portion including active areas having semiconductor devices features formed therein the process surface including a dielectric insulating layer; forming a plurality of openings in the periphery portion to form closed communication with the dielectric insulating layer the plurality of openings having an aspect ratio of at least 2; blanket depositing a metal layer to cover the process surface including the periphery portion to include filling the plurality of openings to anchor the metal layer; and, performing a CMP process to remove at least a portion of the metal layer from the process surface.

Abstract: A gap-filling process is provided. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening therein. A gap-filling material layer is formed over the dielectric layer and inside the opening. A portion of the gap-filling material is removed from the gap-filling material layer to expose the dielectric layer. A gap-filling material treatment of the surface of the gap-filling material layer and the dielectric layer is carried out to planarize the gap-filling material layer so that a subsequently formed bottom anti-reflection coating or material layer over the gap-filling material layer can have a high degree of planarity.

Abstract: Methods in accordance with the present invention provide a quasi-planarized surface between one or more semiconductor devices and at least a portion of surrounding passivation material, where the devices have different elevations above a substrate. A hard mask defines the planarized surface as the interface between the hard mask and both the passivation layer and the device, after a passivation layer etching process. The resulting planarized surface has a small to zero step height, is insensitive to passivation layer non-uniformity and etch non-uniformity, provides full passivation of the device side wall, provides protection for the device against etch-induced damage, and prevents the detrimental effects of passivation layer voids.

Abstract: A method for fabricating a semiconductor device capable of preventing an electric short circuit between a storage node contact plug and a conductive pattern by forming an attack barrier layer or use of an insulation layer having a flow-fill property. The attack barrier layer for preventing the electric short circuit is formed by employing two methods. First, the attack barrier layer is formed on an entire surface of a structure containing the plugs after the CMP process and the cleaning process. Second, the attack barrier layer is formed on a structure including a storage node contact hole such that the attack barrier layer fills the lost portion of the insulating material-based layer. Also, instead of using the attack barrier layer, the insulation layer having a flow-fill property is deposited after the cleaning process.

Abstract: A semiconductor structure for providing metal interconnections (140) and a method for electropolishing a metal layer on a semiconductor structure. A semiconductor structure includes a dielectric layer (151) with recessed areas (151r) and non-recessed areas (151n), a metal layer formed on the structure fills the recessed areas to form interconnection lines, and a plurality of dummy structures (130) placed adjacent the interconnect lines. The method includes forming a dielectric layer with recessed and non-recessed areas on a semiconductor wafer. Forming dummy structures adjacent the recessed areas. Forming a metal layer to cover the dielectric layer and the dummy structures. The metal layer is then electropolished to expose the non-recessed area.

Abstract: A process for the formation of structures in microelectronic devices such as integrated circuit devices. Vias, interconnect metallization and wiring lines are formed using single and dual damascene techniques wherein dielectric layers are treated with a wide electron beam exposure.

Abstract: A damascene-formed conductive region having a recess formed at the top surface thereof by a chemical-mechanical polish (CMP) process is repaired or regrown using a displacement method. A displacement material is deposited over the recessed conductive material. The displacement material is removed from a top surface of the insulating layer surrounding the damascene conductive region, and the semiconductor device is placed in a solution. The displacement material reacts with the solution, and copper in the solution is grown as a result of the displacement over the recess of the conductive region. The displacement method results in reducing or eliminating the recess formed by the CMP process.

Abstract: A TaN film and a Cu film are deposited successively over an insulating film formed with trenches. Then, a first CMP process is performed by using a slurry having a polishing rate for Cu sufficiently higher than a polishing rate for TaN and containing an agent for forming a protective film for Cu in a sufficient amount. As a result, the upper surface of the portion of the Cu film located in each of the trenches is positioned flush with the upper surface of TaN. Then, a second CMP process is performed under such a condition that the polishing rate for Cu is equal to or higher than the polishing rate for TaN, thereby forming Cu wires. By properly changing conditions for the second CMP process in accordance with the level of the upper surface of the Cu film, the upper surface of the Cu film is positioned flush with or lower in level than the upper surface of the insulating film after the second CMP process so that the occurrence of defective wiring is reduced.

Abstract: A method of forming a composite intermetal dielectric structure is provided. An initial intermetal dielectric structure is provided, which includes a first dielectric layer and two conducting lines. The two conducting lines are located in the first dielectric layer. A portion of the first dielectric layer is removed between the conducting lines to form a trench. The trench is filled with a second dielectric material. The second dielectric material is a low-k dielectric having a dielectric constant less than that of the first dielectric layer.

Abstract: In order to reduce micro scratches which tend to occur during chemical-mechanical polishing, a polishing slurry is diluted with deionized water immediately before it is supplied in a gap between a polishing pad and the surface of a wafer to be polished. By diluting the polishing slurry with deionized water to increase its volume, the concentration of coagulated particles contained in the polishing slurry can be lowered. For a mixture ratio of the polishing slurry and deionized water, about 1 (polishing slurry): 1-1.2 (deionized water) is used, and the concentration of silica contained in the diluted polishing slurry is adjusted to about 3-9 weight %, preferably about 4-8 weight %, and more preferably about 8 weight %.

Abstract: In a method of planarizing a semiconductor wafer, the improvement comprising polishing above metal interconnect lines to uniformly polish the topography of the wafer to a predetermined endpoint on the wafer sufficiently close above the metal interconnect lines, yet far enough away from the lines to prevent damage to the lines, comprising:

Abstract: For 0.18 micron technology, it is common practice to use silicon oxynitride as an anti-reflective layer for defining the via etch patterns. It has however been found that, using current technology, residual particles of oxynitride get left behind. The present invention solves this problem by subjecting the surface from which the silicon oxynitride was removed to a high pressure rinse of an aqueous solution that includes a surfactant such as tetramethyl ammonium hydroxide or isopropyl alcohol. These surfactants serve to modify the hydrophobic behavior of the silicon oxynitride particles so that they no longer cling to the surface.

Abstract: An interconnect structure for a semiconductor device includes a metallization line formed within a low-k dielectric material, the metallization line being surrounded on bottom and side surfaces thereof by a liner material. An embedded dielectric cap is formed over a top surface of the metallization line, wherein the embedded dielectric cap has a sufficient thickness so as to separate a top surface of the liner material from a hardmask layer formed over the low-k dielectric material.

Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally liable groups with nitrous oxide, oxygen, ozone, or other source of reactive oxygen in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.

Abstract: Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a polishing pressures of about 2 psi or less and at platen rotational speeds of about 200 cps or greater. The polishing process may use an abrasive-containing polishing composition having up to about 1 wt. % of abrasives. The polishing process may be integrated into a multi-step polishing process.

Abstract: A method for manufacturing a semiconductor device which enables favorable back-surface grinding of a semiconductor substrate with preventing a warp in the substrate, thereby manufacturing a thickness-reduced semiconductor device. A projection electrode is formed on a surface of a wafer. A resin layer is formed on the wafer surface to a thickness to bury a top of the projection electrode. A cut groove is formed in the resin layer along a scribe line formed on the wafer. Thereafter, grinding is made on a back surface of the wafer by the use of a grinder or the like. A surface portion of the resin layer is removed by etching or the like, to expose the top of the projection electrode. The wafer is cut along the cut groove to obtain individual semiconductor chip pieces.

Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

Abstract: Methods are disclosed to improve the planarization of copper damascene by the steps of patterning on the copper damascene a photoresist using a reverse tone photo mask or a reverse tone photo mask of the metal lines, removing excess copper by reverse current plating or by dry or wet chemical etching, stripping the photo resist, and a subsequent chemical mechanical planarization of the copper damascene. Lastly a cap layer is applied to the planarized surface. In a variant of the disclosed method a more relaxed reverse tone photo mask of the metal lines is used, which may be more desirable for practical use. These steps provide benefits such as improved uniformity of the wafer surface, reduce the dishing of metal lines (trenches) and pads, and reduce oxide erosion.

Abstract: This invention relates to a method of dual damascene integration for manufacture of integrating circuits using three top hard mask layers having alternating etch selectivity characteristics.

Abstract: A process and structure for copper damascene interconnects including a tungsten-nitride (WN2) barrier layer formed by atomic layer deposition is disclosed. The process method includes of forming a copper damascene structure by forming a first opening through a first insulating layer. A second opening is formed through a second insulating layer which is provided over the first insulating layer. The first opening being in communication with the second opening. A tungsten-nitride (WN2) layer is formed in contact with the first and second openings. And, a copper layer is provided in the first and second openings. Copper is selectively deposited using a selective electroless deposition technique at low temperature to provide improved interconnects having lower electrical resistivity and more electro/stress-migration resistance than conventional interconnects. Additionally, metal adhesion to the underlying substrate materials is improved and the amount of associated waste disposal problems is reduced.

Abstract: An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds prescribed integrated circuit manufacturing limits in at least one dimension. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. The non-conducting region includes a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.

Abstract: In a new method of plating metal onto dielectric layers including small diameter vias and large diameter trenches, a surface roughness is created at least on non-patterned regions of the dielectric layer to enhance the uniformity of material removal in a subsequent chemical mechanical polishing (CMP) process.

Abstract: A CMP process for selectively polishing an overlying material layer with an underlying layer comprising at least one material in a semiconductor device fabrication process including providing a semiconductor wafer process surface including a first material layer overlying a second layer including one material; mixing at least two slurry mixtures including a first CMP slurry formulation optimized for removing the first material layer and a second CMP slurry formulation optimized for removing the at least a second layer to form a slurry formulation mixture; and, carrying out a CMP process using the slurry formulation mixture to remove the first material layer and at least a portion of the at least a second layer.

Abstract: A new method is provided for the creation of copper interconnects. An opening is created in a layer of dielectric, a layer of barrier material is deposited. The layer of barrier material extends over the surface of the layer of dielectric. A film of copper is deposited over the surface of the layer of barrier material. The copper film is polished down to the surface of the layer of barrier material, creating a first copper interconnect. The created first copper interconnect is subjected to a thermal anneal, inducing copper hillocks in the surface of the first copper interconnect by releasing copper film stress in the first copper interconnect. The copper hillocks are then removed by polishing the surface of the created first copper interconnect down to the surface of the surrounding layer of dielectric, creating a second and final copper interconnect.

Abstract: The present invention comprises the steps of performing a reforming process on a surface of a low dielectric constant insulation film formed on a substrate which includes one of a porous low dielectric constant insulation film and a non-porous low dielectric constant insulation film and forming an insulation film as at least one of an etching mask and a Chemical Mechanical Polishing stopper (CMP stopper) on the reformed surface of the low dielectric constant insulation film. For example, plasma is radiated as a reforming process mentioned above, the surface roughness of a low dielectric insulation film is increased and, as a result, adhesion between the films and also between the inter-layer insulation film and other neighboring films can be improved with so-called “anchor effect”.

Abstract: A polishing composition capable of satisfactorily polishing a semiconductor. The first polishing composition of the present invention includes silicon dioxide, at least one component selected from periodic acids and salts thereof, at least one component selected from tetraalkyl ammonium hydroxides and tetraalkyl ammonium chlorides, hydrochloric acid, and water, and contains substantially no iron. The second polishing composition of the present invention includes a predetermined amount of fumed silica, a predetermined amount of at least one component selected from periodic acids and salts thereof, a tetraalkyl ammonium salt represented by the following general formula (1), at least one component selected from ethylene glycol and propylene glycol, and water. The pH of the second polishing composition is greater than or equal to 1.8 and is less than 4.0.

Abstract: A semiconductor device and a method for making it involve the semiconductor device (10, 110, 210, 310) having a substrate (11, 311) with spaced source and drain regions (13-14, 316-318, 321-323). A gate section (21) projects upwardly from between an adjacent pair of these regions, into an insulating layer (46, 363). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (51), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (56-57) on opposite sides of and immediately adjacent the gate section. A conductive layer (61, 120) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections.

Abstract: A method of depositing a low dielectric constant film on a substrate. In one embodiment, the method includes the steps of positioning the substrate in a deposition chamber, providing a gas mixture to the deposition chamber, in which the gas mixture is comprised of one or more cyclic organosilicon compounds, one or more aliphatic compounds and one or more oxidizing gases. The method further includes reacting the gas mixture in the presence of an electric field to form the low dielectric constant film on the semiconductor substrate. The electric field is generated using a very high frequency power having a frequency in a range of about 20 MHz to about 100 MHz.

Abstract: A semiconductor device comprises a semiconductor substrate in which a semiconductor element is formed, an interlayer insulating film formed on the semiconductor substrate, an insulating barrier layer, formed on the interlayer insulating film by plasma nitriding, for preventing diffusion of a metal constituting a wiring layer, a conductive barrier layer, formed on the insulating barrier layer, for preventing diffusion of the metal, and a wiring layer formed of the metal on the conductive barrier layer. A bottom portion of the wiring layer is protected by the conductive barrier layer and the insulating barrier layer. Therefore, the diffusion of the metal constituting the wiring layer can be surely prevented.

Abstract: There is disclosed a CMP slurry which comprises a solvent, abrasive grains, and a silicone-based surfactant having an HLB value ranging from 7 to 20.

Abstract: An embodiment for a method for forming a self-passivated copper interconnect structure. An insulating layer is formed over a semiconductor structure. An opening is formed in the insulating layer. Next, we form a fill layer comprised of Cu and Ti over insulating layer. In a nitridation step, we nitridize the fill layer to form a self-passivation layer comprised of titanium nitride over the fill layer.

Abstract: At the end of a film-forming process of an insulator made of a silicon nitride film by a plasma CVD, introduction of the silane system gas is stopped, and thereafter a plasma discharge is performed for a predetermined time while introduction of the nitrogen-containing gas is continued, and then the plasma discharge is stopped. In this manner, it is possible to nitride an unreacted product on the silicon nitride film and to prevent drawbacks due to the unreacted product.

Abstract: A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposited upon the semiconductor wafer within the contact hole. A planarizing step isolates the first metal layer within the insulation layer in the form of a contact plug within the contact hole. A second metal layer is then deposited upon the semiconductor wafer over and upon the contact plug. Metallization lines are patterned and etched from the second metal layer. The contact hole may also be lined with a refractory metal nitride layer, with a refractory metal silicide interface being formed at the bottom of the contact hole as an interface between the contact plug and a silicon layer on the semiconductor substrate.

Abstract: Method and apparatus are provided for polishing substrates comprising conductive and low k dielectric materials with reduced or minimum substrate surface damage and delamination. In one aspect, a method is provided for processing a substrate including positioning a substrate having a conductive material formed thereon in a polishing apparatus having one or more rotational carrier heads and one or more rotatable platens, wherein the carrier head comprises a retaining ring and a membrane for securing a substrate and the platen has a polishing article disposed thereon, contacting the substrate surface and the polishing article to each other at a retaining ring contact pressure of about 0.4 psi or greater than a membrane pressure, and polishing the substrate to remove conductive material.

Abstract: A method of manufacturing a semiconductor device includes forming an insulation film having a recess above a semiconductor substrate, depositing a conductive film on the insulation film and filming conductive film in the recess, and polishing the conductive film by a CMP process using CMP slurry in order to selectively leave the conductive film in the recess, the CMP slurry including a polishing component and a restoring component, thereby reducing a scratch formed on at least one of the insulation film and the conductive film by causing the scratch to be filled.

Abstract: In a via-first Dual Damascene method, after a via hole and a wiring trench are formed, an SiN film, an exposed portion of an SiC film and an exposed portion of an SiC film are removed by etching. As a result, the via hole reaches a Cu wire, and the wiring trench reaches an SiOC film. A reaction product adheres mainly to a side wall portion of the wiring trench. The reaction product also adheres to other spots, but an amount of adherence to the side wall portion is the largest. Subsequently, oxygen plasma treatment is performed for insides of the via hole and the wiring trench. As a result of this oxygen plasma treatment, the reaction product is removed.

Abstract: Methods for removing residuals from the surface of an integrated circuit device. Such methods find particular application in the fabrication of a dual damascene structure following removal of excess portions of a silver-containing metal layer from a device surface. The methods facilitate removal of particulate residuals as well as unremoved portions of the metal layer in a single cleaning process. The cleaning solutions for use with the methods are dilute aqueous solutions containing hydrogen peroxide and at least one acidic component and are substantially free of particulate material. Acidic components include carboxylic acids and their salts.

Abstract: A common problem associated with damascene structures made of copper inlaid in FSG (fluorinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silicate glass) over the surface of the FSG layer prior to patterning and etching the latter to form the via hole and (for a dual damascene structure) the trench. After over-filling with copper, the structure is planarized using CMP. The USG layer acts both to prevent any fluorine from the FSG layer from reaching the copper and as an end-point detector during CMP. In this way defects that result from copper-fluorine interaction do not form and precise planarization is achieved.

Abstract: An embodiment of the invention is a method to reduce the corrosion of copper interconnects 90 by forming a thiol ligand coating 130 on the surface of the copper interconnects 90.

Abstract: A semiconductor device is fabricated by a method that includes forming a conductive pattern on a semiconductor substrate, covering the conductive pattern with a dielectric layer, and planarizing the dielectric layer by chemical-mechanical polishing. To avoid global height differences, a dummy pattern is added to the conductive pattern if a predetermined condition is satisfied. The condition is based on the calculated density of the conductive pattern in a region including the region in which the dummy pattern is to be added. The calculated density may be adjusted according to the type of equipment used to deposit the dielectric layer, and the dummy pattern dimensions may be adjusted according to the calculated density. Such calculations avoid the need for human judgment and lead to more uniform planarization.

Abstract: A damascene interconnect structure with a bi-layer capping film is provided. The damascene interconnect structure comprises a semiconductor layer and a dielectric layer disposed on the semiconductor layer. The dielectric layer has a main surface and at least one damascened recess provided on the main surface. A copper wire is embedded in the damascened recess. The copper wire has a chemical mechanical polished upper surface, which is substantially co-planar with the main surface of the dielectric layer. After polishing the upper surface of the copper wire, the upper surface is pre-treated and reduced in a conductive plasma environment at a temperature of below 300 ° C. A bi-layer capping film is thereafter disposed on the upper surface of the copper wire. The bi-layer capping film consists of a lower HDPCVD silicon nitride layer and an upper doped silicon carbide layer.

Abstract: A method for forming a wire line by a damascene process includes forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a contact hole, and forming a first conductive layer over the first insulating layer that fills the contact hole. The first conductive layer is patterned, and a storage node contact is formed that fills the contact hole and is electrically connected to the semiconductor substrate. A hard mask is formed over the storage node contact and the first insulating layer is etched using the hard mask as an etch mask to form a trench in the first insulating layer. A bit line is formed in the trench that is electrically connected to the semiconductor substrate. A second insulating layer is formed that covers the bit line. The second insulating layer and the hard mask are planarized and a storage node of a capacitor is formed on the storage node contact.

Abstract: There is disclosed a CMP slurry which comprises a solvent, abrasive grains, and a silicone-based surfactant having an HLB value ranging from 7 to 20.

Abstract: A substrate is prepared whose surface has a partial area exposing an insulating material containing fluorine and at least a partial area in the other area exposing a conductive material containing copper as a main composition. The surface of the substrate is exposed to hydrogen plasma to clean the surface. A first insulating film made of insulating material is formed on the cleaned surface. It is possible to form a lamination structure having a fluorine-doped interlayer insulating film hard to be peeled off.

Abstract: A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

Abstract: A method of planarizing wafers using shallow trench isolation is described. The method uses a very hard polishing pad and chemical mechanical polishing with no additional etching required. Trenches are formed in a substrate and filled with a trench dielectric, such as silicon dioxide deposited using high density plasma chemical vapor deposition. A layer of resist is then formed on the layer of trench dielectric. The wafer is then planarized using chemical mechanical polishing and a polishing pad having a hardness of at least Shore “D” 52. The hard polishing pad avoids scratch marks on the trench dielectric, the substrate surface, or any other materials deposited on the substrate surface.

Abstract: An evaluating pattern is comprised of a conductive pattern which has a rectangular configuration, an insulating layer which is formed on the conductive pattern, and a conductive material filled into contact holes which is formed in the insulating layer on the middle of the conductive pattern.