Abstract: A method of protecting a low k dielectric layer that is preferably comprised of a material containing Si, O, C, and H is described. The dielectric layer is subjected to a gas plasma that is generated from a CXHY gas which is preferably ethylene. Optionally, hydrogen may be added to the CXHY gas. Another alternative is a two step plasma process involving a first plasma treatment of CXHY or CXHY combined with H2 and a second plasma treatment with H2. The modified dielectric layer provides improved adhesion to anti-reflective layers and to a barrier metal layer in a damascene process. The modified dielectric layer also has a low CMP rate that prevents scratch defects and an oxide recess from occurring next to the metal layer on the surface of the damascene stack. The plasma treatments are preferably done in the same chamber in which the dielectric layer is deposited.

Abstract: Method and apparatus are provided for polishing substrates comprising conductive and low k dielectric materials with reduced or minimum substrate surface damage and delamination. In one aspect, a method is provided for processing a substrate including positioning a substrate having a conductive material formed thereon in a polishing apparatus having one or more rotational carrier heads and one or more rotatable platens, wherein the carrier head comprises a retaining ring and a membrane for securing a substrate and the platen has a polishing article disposed thereon, contacting the substrate surface and the polishing article to each other at a retaining ring contact pressure of about 0.4 psi or greater than a membrane pressure, and polishing the substrate to remove conductive material.

Abstract: In a new method of plating metal onto dielectric layers including small diameter vias and large diameter trenches, a surface roughness is created at least on non-patterned regions of the dielectric layer to enhance the uniformity of material removal in a subsequent chemical mechanical polishing (CMP) process.

Abstract: Disclosed is a method for depositing a silicon nitride layer of a semiconductor device. The method includes the steps of providing Al-based compound as a catalyst, and reacting DCS with NH3 by using the Al catalyst, thereby depositing the silicon nitride layer. DCS is reacted with NH3 by using the Al catalyst when depositing the silicon nitride layer, so dissolution of DCS is promoted by means of the Al catalyst, so that the silicon nitride layer is deposited at a high speed, thereby improving productivity of semiconductor devices. The silicon nitride layer is deposited by using DCS under a low-temperature condition of about 500 to 800° C., without deteriorating device characteristics.

Abstract: A fabricating system. A processing tool executes a film removal process on a wafer using a chemical mechanism. A metrology tool monitors surface characteristics of the wafer to obtain a measured film thickness thereof before and after a first removal process, wherein the first removal process lasts a first processing duration. The controller, coupled to the processing and metrology tools, determines whether the difference between the measured film thickness and a preset film thickness exceeds a preset value, and determines a second processing duration of a second removal process according to the measured and preset film thickness and the first processing duration.

Abstract: A method for fabricating semiconductor devices is disclosed, the method including forming a landing plug on a lower interlayer insulating film, successively depositing an upper interlayer insulating film and a nitride film, forming a bit line contact hole, depositing a conductive layer for a contact plug, and forming a contact plug through a CMP process.

Abstract: An oxide polishing process that is part of a CMP process flow is disclosed. After a copper layer is polished at a first polishing station and a diffusion barrier layer is polished at a second polishing station, a key sequence at a third polish station is the application of a first oxide slurry and a first DI water rinse followed by a second oxide slurry and then a second DI water rinse. As a result, defect counts are reduced from several thousand to less than 100. Another important factor is a low down force that enables more efficient particle removal. The improved oxide polishing process has the same throughput as a single oxide polish and a DI water rinse method and may be implemented in any three slurry copper CMP process flow.

Abstract: A scheme for filling plugs through chemical mechanical polishing comprises depositing a malleable conductive layer over a dielectric layer having openings formed therein. The malleable conductive layer is deposited such that a liner is formed within the openings, however the openings are not completely filled. A chemical mechanical polishing process using an alumina based slurry at a neutral or slightly basic pH and no oxidizer is used to smear the malleable conductive layer sufficiently to fill the remainder of the openings in the dielectric layer forming filled or substantially filled plugs.

Abstract: A recess is formed in an insulating film, and then a conductive film is deposited over the insulating film so as to fill the recess. Thereafter, the conductive film is subjected to a first heat treatment. Subsequently, part of the conductive film located outside the recess is removed, and then the remaining part of the conductive film is subjected to a second heat treatment with the surface thereof exposed.

Abstract: Numerous embodiments of a stacked device underfill and a method of formation are disclosed. In one embodiment, a method of forming stacked semiconductor device with an underfill comprises forming one or more layers of compliant material on at least a portion of the top surface of a substrate, said substrate, curing at least a portion of the semiconductor device, selectively removing a portion of the one or more layer of complaint material, and assembling the substrate into a stacked semiconductor device.

Abstract: A two-step chemical mechanical polishing (CMP) process is provided to minimize (reduce) dishing of metal lines in trenches in an insulation (oxide) layer of each of a plurality of semiconductor wafers during fabrication thereof. For each wafer, the first step involves CMP of a metal layer disposed on the oxide layer and having a lower portion located in the trenches for forming metal lines and an upper portion overlying the lower portion. The first step polishing uses a first polishing pad to remove the bulk of the metal layer upper portion while generating concomitant CMP residue, and leaves a minimized (reduced) remainder of the metal layer upper portion without dishing of the metal layer lower portion in the trenches. The second step continues the CMP with a second polishing pad to remove the remainder of the metal layer upper portion with minimized (reduced) dishing of the metal layer lower portion to an extent providing the metal lines as individual metal lines in the trenches.

Abstract: A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer.

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

Abstract: A method of forming a gate in a semiconductor device includes forming a dummy gate insulating layer on a semiconductor substrate having a field oxide layer isolating the device, depositing a dummy gate polysilicon layer and a hard mask layer on the dummy gate insulating layer sequentially, patterning the hard mask layer into a mask pattern and patterning the dummy gate polysilicon layer using the mask pattern as an etch barrier, forming spacers at both sidewalls of the dummy gate polysilicon layer, depositing an insulating interlayer on the resultant structure after forming the spacers, exposing a surface of the dummy gate polysilicon layer by carrying out an oxide layer CMP process having a high selection ratio against the dummy gate polysilicon layer, forming a damascene structure by removing the dummy gate polysilicon layer and the dummy gate insulating layer using the insulating interlayer as another etch barrier, depositing a gate insulating layer and a gate metal layer on the entire surface of the semic

Abstract: A substrate having a conductive layer is provided. A dielectric layer is then formed above the conductive layer. At least one via hole is then formed in the dielectric layer, to expose a portion of the conductive layer. The conductive layer is then covered with a gap fill polymer layer, to completely fill the via hole. A chemical mechanical polishing step is performed to remove the partial gap fill polymer layer on the outside of the via hole. An etching step, is performed to remove a portion of partial gap fill polymer layer remaining in the via hole, resulting in a partial gap fill polymer. A lithographic process is conducted to form a patterned photoresist layer over the dielectric layer. The photoresist layer has an opening that exposes the via hole and partial gap fill polymer. A portion of the dielectric layer exposed by the opening is etched away, to form a trench in the dielectric layer.

Abstract: A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.

Abstract: A copper-containing layer suitable for an electrical interconnect in a device such as an integrated circuit is created by a procedure in which a trench (104) is formed through a dielectric layer (102) down to a substrate (100). A diffusion barrier (106) is provided over the dielectric layer and into the trench. Copper (108) is deposited over the diffusion barrier and into the trench. Chemical mechanical polishing is utilized to remove the copper outside the trench down substantially to the diffusion-barrier material overlying the dielectric layer. A sputter etch, typically of the reactive type, is then performed to substantially remove the diffusion-barrier material overlying the dielectric layer. The sputter etch typically removes copper above and/or in the trench at approximately the same rate as the diffusion-barrier material so as to substantially avoid the undesirable dishing phenomenon.

Abstract: A method of manufacturing a semiconductor device uses a slurry for chemical polishing during the manufacturing process, the slurry containing polishing particles comprising colloidal particles whose primary particles have a diameter ranging from 5 to 30 nm, wherein the degree of association of the primary particles is 5 or less. This slurry for chemical mechanical polishing makes it possible to minimize erosion and scratching whenever a conductive material film is subjected to CMP treatment.

Abstract: A copper damascene structure formed by direct patterning of a low-dielectric constant material is disclosed. The copper damascene structure includes a tungsten nitride barrier layer formed by atomic layer deposition using sequential deposition reactions. Copper is selectively deposited by a CVD process and/or by an electroless deposition technique.

Abstract: Methods of manufacturing semiconductor devices are disclosed. In an illustrated method, a contact hole in an insulating layer is filled with a copper layer and the copper layer is planarized. During the planarzing, a CuO layer is parasitically formed on the surface of the copper layer. The CuO layer is removed by plasma processing using ammonia or nitrogen. A conductive CuN layer is formed on the surface of the copper layer. Stability of the removal process of CuO layer is secured.

Abstract: An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; a barrier layer located in the via opening; an interlayer of palladium and/or platinum on the barrier layer; and a layer of copper or copper alloy on the interlayer is provided.

Abstract: In a fabrication method for forming an electrical interconnection of CVD tungsten film, a contact hole is formed in a dielectric layer. A lower conductive layer is formed in the contact hole and over the dielectric layer. A portion of the lower conductive layer is removed. As a result, the dielectric layer is exposed. An upper conductive layer is formed over the lower conductive layer and over the dielectric layer. The lower conductive layer has a rough surface and the upper conductive layer has a smooth surface. In this manner, following patterning of conductive stripes over the conductive layer, residue is mitigated, and thus, inadvertent interconnection of neighboring stripes is eliminated.

Abstract: A method to reduce the copper corrosion of copper interconnects by forming 70 at least one conductive displacement plating layer on the copper interconnects. Also, a method to eliminate the copper corrosion of copper interconnects by forming 70 at least one conductive displacement plating layer on the copper interconnects.

Abstract: A semiconductor device has first interlayer insulating film having a wiring trench; a wiring portion having a first barrier metal layer formed over side walls and bottom surface of the wiring trench, a first conductor layer formed over the first barrier metal layer to embed the wiring trench, and a capping barrier metal film formed over the first conductor layer; second interlayer insulating film formed over the first interlayer insulating film and having a connecting hole; and a connecting portion having a second barrier metal layer formed over side walls and bottom surface of the connecting hole, and a second conductor layer formed over the second barrier metal layer to embed the connecting hole; wherein, at a joint between the connecting portion and wiring portion, at least one of the second barrier metal layer and capping barrier metal film on the bottom surface of the connecting hole is removed.

Abstract: A preceding wafer having an aluminum wiring and a silicon oxide film formed on an insulating film is chemico-mechanically polished. In the stage in which surface irregularities of the silicon oxide film are eliminated, polishing is discontinued. On the basis of the result, a polishing time is determined in accordance with the following formula: T=(D1?D2)/v+t1 where, D1 represents the thickness in the stage in which polishing is discontinued; D2, a target thickness; t1, a time required from the initial thickness to reach the thickness D1; and the polishing rate of the material of the silicon oxide film formed on a flat substrate is denoted as v.

Abstract: A method is provided for forming an electrical conductors, comprising forming electrically conductive segments incorporating electromigration-inhibiting plugs. A row of windows is formed in a planar surface and electromigration-inhibiting material is deposited over the planar surface and into the windows to provide, electromigration-inhibiting plugs in the windows. The plugs may be formed by depositing an electromigration-inhibiting liner in the windows and then depositing electrically conductive material to fill the windows. Portions of either or both of the plugs and conductive segments are removed such that the plugs and conductive segments have a coplanar surface. The plugs may be formed in windows in an electrically conductive layer defining the conductive segments.

Abstract: In one embodiment, a metal level includes a plurality of metal lines. A low-k dielectric is deposited over the metal level such that an air gap forms at least between two metal lines. The relatively low dielectric constant of the low-k dielectric reduces capacitance on metal lines regardless of whether an air gap forms or not. The air gap in the low-k dielectric further reduces capacitance on metal lines. The reduced capacitance translates to lower RC delay and faster signal propagation speeds.

Abstract: A damascene-formed conductive region having a recess formed at the top surface thereof by a chemical-mechanical polish (CMP) process is repaired or regrown using a displacement method. A displacement material is deposited over the recessed conductive material. The displacement material is removed from a top surface of the insulating layer surrounding the damascene conductive region, and the semiconductor device is placed in a solution. The displacement material reacts with the solution, and copper in the solution is grown as a result of the displacement over the recess of the conductive region. The displacement method results in reducing or eliminating the recess formed by the CMP process.

Abstract: A method of forming buried wiring, includes the steps of forming an insulating layer having a trench on a semiconductor substrate; forming a conductive layer mainly composed of copper on the insulating layer in such a manner that the trench is filled with the conductive layer; removing an oxide layer generated in a surface of the conductive layer by oxidation; forming a cap layer made of a material having less mechanical strength than the oxide layer, on the conductive layer; and removing the cap layer and a part of the conductive layer by chemical mechanical polishing in such a manner that the conductive layer is left in the trench.

Abstract: In a polishing apparatus having a cover body with fluid pressing mechanism, during polishing, vibration and migration of sticking portion between a retainer and a membrane generated in downstream of rotation of a polishing platen is prevented by reducing sticking force between the retainer and the membrane to less than force needed to wafer polishing with rotation of the cover body.

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, then forming a capping layer on the high-k gate dielectric layer. After oxidizing the capping layer to form a capping dielectric oxide on the high-k gate dielectric layer, a gate electrode is formed on the capping dielectric oxide.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a barrier conductor layer on a substrate, exposing the barrier conductor layer to a first reducing gas atmosphere at an elevated substrate temperature, forming a metal film on the barrier conductor layer by a CVD process, and exposing the metal film to a second gas atmosphere at an elevated substrate temperature.

Abstract: After a plurality of grooves are formed in an insulating film, a barrier metal film and a conductive film are deposited successively on the insulating film such that each of the grooves is filled completely therewith. Subsequently, the portions of the conductive film outside the grooves are removed by polishing and then the portions of the barrier metal film outside the grooves are removed by polishing. Thereafter, a foreign matter adhered to the surface to be polished during polishing is removed and then a surface of the insulating film is polished.

Abstract: Methods and apparatus for protecting the dielectric layer sidewalls of openings, such as vias and trenches, in semiconductor substrates are provided. A pre-liner and a liner are deposited over the sidewalls of the openings as part of integrated processing sequences that either do not remove the photoresist until subsequent processing or remove the photoresist with a plasma etch that does not contaminate the sidewalls of the openings.

Abstract: A method and apparatus for conditioning a polishing pad is described, wherein the polishing pad has a polishing surface for polishing the semiconductor wafer. The method includes positioning a sonic energy generator above the polishing surface of the polishing pad, and applying sonic energy to the polishing surface of the polishing pad. The apparatus a sonic energy generator adapted to be positioned above the polishing surface, the sonic energy generator including a transducer, and a liquid carrier in flow communication with the transducer, wherein the transducer transmits sonic energy into the liquid carrier and the liquid carrier is applied to the polishing surface of the polishing belt.

Abstract: A method for implementing a bismaleimide (BMI) polymer as a sacrificial material for an integrated circuit air gap dielectric. The method of one embodiment comprises forming a first and second metal interconnect lines on a substrate, wherein at least a portion of the first and second metal interconnect lines extend parallel to one another and wherein a trough is located between the parallel portion of said first and second metal interconnect lines. A layer of bismaleimide is spin coated over the substrate. The layer of bismaleimide is polished with a chemical mechanical polish, wherein the trough remains filled with the bismaleimide. A diffusion layer is formed over the substrate. The substrate is heated to activate a pyrolysis of the bismaleimide. An air gap is formed in the trough in the space vacated by the bismaleimide.

Abstract: An embodiment of the present invention includes a method to form an air gap in a multi-layer structure. A dual damascene structure is formed on a substrate. The dual damascene structure has a metallization layer, a barrier layer, a sacrificial layer, and a hard mask layer. The sacrificial layer is made of a first sacrificial material having substantial thermal stability and decomposable by an electron beam. The sacrificial layer is removed by the electron beam to create the air gap between the barrier layer and the hard mask layer.

Abstract: A semiconductor structure includes a substrate, a dielectric layer disposed on the substrate, a layer of undoped silicate glass disposed on the dielectric layer, a layer of borophosphorous silicate glass on the layer of undoped silicate glass, and a planar dielectric layer disposed on the layer of borophosphorous silicate glass, the layers of undoped silicate glass, borophosphorous silicate glass, and planar dielectric together forming a pre-metal dielectric stack. The planar dielectric may include plasma-enhanced tetraethyl orthosilicate.

Abstract: A planarization method includes providing a metal-containing surface (preferably, a Group VIII metal-containing surface, and more preferably a platinum-containing surface) and positioning it for contact with a polishing surface in the presence of a planarization composition that includes a halogen and a halide salt.

Abstract: A low-k dielectric layer (104) is treated with a dry-wet (D-W) or dry-wet-dry (D-W-D) process to improve patterning Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The D-W or D-W-D treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).

Abstract: Embodiments of the invention include a method for electro chemical mechanical polishing of a substrate. The process includes flowing an electro chemical mechanical polishing (ECMP) slurry having a high viscosity with a polishing agent over a portion of the substrate. Electrical current is passed through the slurry and substrate. The electrical current, in conjunction with the abrading action of the slurry as it flows over the surface of the substrate, serves to remove at least a portion of the metal layer from the substrate. The invention also includes various slurry embodiments.

Abstract: After a plurality of grooves are formed in an insulating film and in an antireflection film on the insulating film, a barrier metal film and a conductive film are deposited on the anti-reflection film such that each of the grooves is filled. Subsequently, the portions of the conductive film outside the grooves are removed by a first polishing step and then the portions of the barrier metal film outside the grooves are removed by polishing. Thereafter, foreign matter adhered to the surface of the anti-reflection film is removed and a third polishing step is conducted on the surface of the anti-reflection film using an abrasive agent of the same type as used in the first polishing step of the conductive film.

Abstract: A method of manufacturing a resistive semiconductor memory device (100), comprising depositing an insulating layer (132) over a workpiece (30), and defining a pattern for a plurality of alignment marks (128) and a plurality of conductive lines (112) within the insulating layer (132). A conductive material is deposited over the wafer to fill the alignment mark (128) and conductive line (112) patterns. The insulating layer (132) top surface is chemically-mechanically polished to remove excess conductive material from the insulating layer (132) and form conductive lines (112), while leaving conductive material remaining within the alignment marks (128). A masking layer (140) is formed over the conductive lines (112), and at least a portion of the conductive material is removed from within the alignment marks (128). The alignment marks (128) are used for alignment of subsequently deposited layers of the resistive memory device (100).

Abstract: Methods and solutions for forming self assembled organic monolayers that are covalently bound to metal interfaces are presented along with a device containing a self assembled organic monolayer. Embodiments of the present invention utilize self assembled thiolate monolayers to prevent the electromigration and surface diffusion of copper atoms while minimizing the resistance of the interconnect lines. Self assembled thiolate monolayers are used to cap the copper interconnect lines and chemically hold the copper atoms at the top of the lines in place, thus preventing surface diffusion. The use of self assembled thiolate monolayers minimizes the resistance of copper interconnect lines because only a single monolayer of approximately 10 ? and 20 ? in thickness is used.

Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

Abstract: A method for spin coating a polymeric material film upon a wafer rotatably mounted within a spin coater; the wafer having a surface, including the following steps. A first step of rotating the wafer on an axis perpendicular to the wafer surface while applying a predetermined amount of polymeric material while rotating the wafer at a rotational speed of from about 300 to 1200 rpm for from about 2.5 to 5 seconds to spread the polymeric material on the whole surface of the wafer. A second step of increasing the rotational speed of the wafer to about 5500 rpm for about 2.5 seconds. A third step of decreasing the rotational speed of the wafer to about 300 to 1200 rpm for about 2.5 seconds. A fourth step of increasing the rotational speed of the wafer to about 5500 rpm for about 20 seconds to form the polymeric material film having a predetermined thickness over the whole surface of the wafer.

Abstract: Methods in accordance with the present invention provide a quasi-planarized surface between one or more semiconductor devices and at least a portion of surrounding passivation material, where the devices have different elevations above a substrate. A hard mask defines the planarized surface as the interface between the hard mask and both the passivation layer and the device, after a passivation layer etching process. The resulting planarized surface has a small to zero step height, is insensitive to passivation layer non-uniformity and etch non-uniformity, provides full passivation of the device side wall, provides protection for the device against etch-induced damage, and prevents the detrimental effects of passivation layer voids.

Abstract: A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A cerium-conductor interconnect cap is disposed over the conductor core with a capping layer over the dielectric layer and the cerium-conductor interconnect cap.

Abstract: A method and an apparatus of removing a particle from a metal plug on a substrate is disclosed. The method comprises introducing a slurry onto the metal layer and polishing the metal layer. A solution comprising hydrogen peroxide is introduced onto the metal plug and at least one particle is removed from the metal plug.

Abstract: A method of forming a more uniform copper interconnect layer is described. A dielectric layer, electroconductive (EC) layer, and a photoresist layer are sequentially deposited on a substrate. An opening in the photoresist is etched through the dielectric layer while the EC layer serves as a hard mask. Following deposition of a diffusion barrier layer and copper seed layer on the EC layer and in the opening, the copper seed layer is removed above the EC layer by a first CMP step. The EC layer serves as a CMP stop to protect the dielectric layer and provides a more uniform surface for subsequent steps. Copper is selectively deposited on the seed layer within the opening. A second CMP step lowers the copper layer to be coplanar with the dielectric layer and removes the EC layer. The resulting copper interconnect layer has a more uniform thickness and surface for improved performance.